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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-09-24 18:45:31 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-09-24 18:45:31 -0700 |
| commit | 64d71dcbc5fa6790385b288de25224d386b047b0 (patch) | |
| tree | 05d1048d44f5347f39b4036163a758e0a75d1ea3 /fpga/usrp3/top/x300/x300_1ge.ucf | |
| parent | ecdd34c08b79117c4f739b336daeb4b9d2bc8df3 (diff) | |
| download | uhd-64d71dcbc5fa6790385b288de25224d386b047b0.tar.gz uhd-64d71dcbc5fa6790385b288de25224d386b047b0.tar.bz2 uhd-64d71dcbc5fa6790385b288de25224d386b047b0.zip | |
fpga: Multiple X300 FPGA bugfixes and enhancements
- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300
Diffstat (limited to 'fpga/usrp3/top/x300/x300_1ge.ucf')
| -rw-r--r-- | fpga/usrp3/top/x300/x300_1ge.ucf | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/fpga/usrp3/top/x300/x300_1ge.ucf b/fpga/usrp3/top/x300/x300_1ge.ucf index acd376251..bdcff1201 100644 --- a/fpga/usrp3/top/x300/x300_1ge.ucf +++ b/fpga/usrp3/top/x300/x300_1ge.ucf @@ -1,2 +1,7 @@ -NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8; -NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7; +NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8; +NET "ETH_CLK_p" TNM_NET = ETH_CLK_p; +TIMESPEC TS_ETH_CLK_p = PERIOD "ETH_CLK_p" 8 ns HIGH 50%; + +NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7; +NET "ETH_CLK_n" TNM_NET = ETH_CLK_n; +TIMESPEC TS_ETH_CLK_n = PERIOD "ETH_CLK_n" TS_ETH_CLK_p HIGH 50%; |