From 64d71dcbc5fa6790385b288de25224d386b047b0 Mon Sep 17 00:00:00 2001 From: Ashish Chaudhari Date: Wed, 24 Sep 2014 18:45:31 -0700 Subject: fpga: Multiple X300 FPGA bugfixes and enhancements - Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 --- fpga/usrp3/top/x300/x300_1ge.ucf | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'fpga/usrp3/top/x300/x300_1ge.ucf') diff --git a/fpga/usrp3/top/x300/x300_1ge.ucf b/fpga/usrp3/top/x300/x300_1ge.ucf index acd376251..bdcff1201 100644 --- a/fpga/usrp3/top/x300/x300_1ge.ucf +++ b/fpga/usrp3/top/x300/x300_1ge.ucf @@ -1,2 +1,7 @@ -NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8; -NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7; +NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8; +NET "ETH_CLK_p" TNM_NET = ETH_CLK_p; +TIMESPEC TS_ETH_CLK_p = PERIOD "ETH_CLK_p" 8 ns HIGH 50%; + +NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7; +NET "ETH_CLK_n" TNM_NET = ETH_CLK_n; +TIMESPEC TS_ETH_CLK_n = PERIOD "ETH_CLK_n" TS_ETH_CLK_p HIGH 50%; -- cgit v1.2.3