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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
| commit | ff1546f8137f7f92bb250f685561b0c34cc0e053 (patch) | |
| tree | 7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/top/x300/gen_ddrlvds_tb.build | |
| parent | 4f691d88123784c2b405816925f1a1aef69d18c1 (diff) | |
| download | uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2 uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.zip | |
Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/top/x300/gen_ddrlvds_tb.build')
| -rwxr-xr-x | fpga/usrp3/top/x300/gen_ddrlvds_tb.build | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x300/gen_ddrlvds_tb.build b/fpga/usrp3/top/x300/gen_ddrlvds_tb.build new file mode 100755 index 000000000..9427a7368 --- /dev/null +++ b/fpga/usrp3/top/x300/gen_ddrlvds_tb.build @@ -0,0 +1,21 @@ + +#!/bin/sh + +rm -rf isim* +rm -rf gen_ddrlvds_tb +rm -rf fuse* +\ +# --sourcelibdir ../../models \ + +vlogcomp \ + --sourcelibext .v \ + --sourcelibdir ../../coregen \ + --sourcelibdir ../../control_lib \ + --sourcelibdir . \ + --sourcelibdir $XILINX/verilog/src \ + --sourcelibdir $XILINX/verilog/src/unisims \ + --work work \ + gen_ddrlvds_tb.v + + +fuse -o gen_ddrlvds_tb gen_ddrlvds_tb
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