From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- fpga/usrp3/top/x300/gen_ddrlvds_tb.build | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100755 fpga/usrp3/top/x300/gen_ddrlvds_tb.build (limited to 'fpga/usrp3/top/x300/gen_ddrlvds_tb.build') diff --git a/fpga/usrp3/top/x300/gen_ddrlvds_tb.build b/fpga/usrp3/top/x300/gen_ddrlvds_tb.build new file mode 100755 index 000000000..9427a7368 --- /dev/null +++ b/fpga/usrp3/top/x300/gen_ddrlvds_tb.build @@ -0,0 +1,21 @@ + +#!/bin/sh + +rm -rf isim* +rm -rf gen_ddrlvds_tb +rm -rf fuse* +\ +# --sourcelibdir ../../models \ + +vlogcomp \ + --sourcelibext .v \ + --sourcelibdir ../../coregen \ + --sourcelibdir ../../control_lib \ + --sourcelibdir . \ + --sourcelibdir $XILINX/verilog/src \ + --sourcelibdir $XILINX/verilog/src/unisims \ + --work work \ + gen_ddrlvds_tb.v + + +fuse -o gen_ddrlvds_tb gen_ddrlvds_tb \ No newline at end of file -- cgit v1.2.3