fpga: Updating FPGA code for UHD-3.7.2-rc1

1 files changed, 4 insertions, 1 deletions

diff --git a/fpga/usrp3/top/x300/gen_ddrlvds.v b/fpga/usrp3/top/x300/gen_ddrlvds.v
index 396d5feda..680b10c84 100644
--- a/fpga/usrp3/top/x300/gen_ddrlvds.v
+++ b/fpga/usrp3/top/x300/gen_ddrlvds.v
@@ -31,6 +31,8 @@ module gen_ddrlvds
    reg 		rising_edge;
    wire [15:0] 	i_and_q_2x;
    reg 		sync_2x;
+   reg 		sync_dacs_reg;
+   
    
    
    genvar 	z;
@@ -55,6 +57,7 @@ module gen_ddrlvds
      begin
 	i_reg <= i;
 	q_reg <= q;
+	sync_dacs_reg <= sync_dacs;
      end  
 
    always @(posedge tx_clk_2x)
@@ -67,7 +70,7 @@ module gen_ddrlvds
 	// To sync multiple AD9146 DAC's an extended assertion of FRAME is required,
 	// when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME,
 	// also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for.
-	sync_2x <=  (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
+	sync_2x <=  (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs_reg) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
 	rising_edge <= (phase_eq_phase2x && ~sync_2x);
 	phase_2x <= phase;
      end