Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

2 files changed, 270 insertions, 0 deletions

diff --git a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile
new file mode 100644
index 000000000..bf4922c21
--- /dev/null
+++ b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright 2015 Ettus Research LLC
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../..)
+# Include viv_sim_preample after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Define part using PART_ID (<device>/<package>/<speedgrade>)
+ARCH = zynq
+PART_ID= xc7z020/clg484/-1
+
+DESIGN_SRCS = $(abspath ../../e310_io.v) \
+  $(abspath $(addprefix $(BASE_DIR)/../lib/control/, \
+  synchronizer.v \
+  synchronizer_impl.v))
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = e310_io_tb
+
+SIM_SRCS = \
+$(abspath e310_io_tb.sv)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv b/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv
new file mode 100644
index 000000000..66e086644
--- /dev/null
+++ b/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv
@@ -0,0 +1,230 @@
+//
+// Copyright 2015 Ettus Research
+//
+// Test bench for E310 I/O interface to AD9361.
+
+`timescale 1ns/1ps
+`define SIM_TIMEOUT_US 20
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 6
+
+`include "sim_clks_rsts.vh"
+`include "sim_exec_report.vh"
+
+module e310_io_tb();
+  `TEST_BENCH_INIT("e310_io_tb",`NUM_TEST_CASES,`NS_PER_TICK)
+
+  // Define all clocks and resets
+  `DEFINE_CLK(rx_clk, 16.27, 50) // ~61.44 MHz clock from AD9361
+  `DEFINE_RESET(areset, 0, 100)  // 100ns reset
+
+  reg mimo;
+  wire radio_clk, radio_rst;
+  wire [11:0] rx_i0, rx_i1, rx_q0, rx_q1;
+  wire rx_stb;
+  reg [11:0] tx_i0, tx_i1, tx_q0, tx_q1;
+  wire tx_stb;
+  reg rx_frame;
+  reg [11:0] rx_data;
+  wire tx_clk;
+  wire tx_frame;
+  wire [11:0] tx_data;
+  e310_io e310_io (
+    .areset(areset),
+    .mimo(mimo),
+    .radio_clk(radio_clk),
+    .radio_rst(radio_rst),
+    .rx_i0(rx_i0),
+    .rx_q0(rx_q0),
+    .rx_i1(rx_i1),
+    .rx_q1(rx_q1),
+    .rx_stb(rx_stb),
+    .tx_i0(tx_i0),
+    .tx_q0(tx_q0),
+    .tx_i1(tx_i1),
+    .tx_q1(tx_q1),
+    .tx_stb(tx_stb),
+    .rx_clk(rx_clk),
+    .rx_frame(rx_frame),
+    .rx_data(rx_data),
+    .tx_clk(tx_clk),
+    .tx_frame(tx_frame),
+    .tx_data(tx_data));
+
+  /********************************************************
+  ** Test Bench
+  ********************************************************/
+  initial begin : tb_main
+    mimo     <= 1'b0;
+    tx_i0    <= 'd0;
+    tx_q0    <= 'd0;
+    tx_i1    <= 'd0;
+    tx_q1    <= 'd0;
+    rx_data  <= 'd0;
+    rx_frame <= 1'b0;
+    `TEST_CASE_START("Wait for reset");
+    while (areset) @(posedge radio_clk);
+    `TEST_CASE_DONE((~areset));
+
+    repeat (10) @(posedge radio_clk);
+
+    `TEST_CASE_START("Test RX channel 0,1");
+    mimo      <= 1'b0;
+    rx_data   <= 'd0;
+    repeat (10) @(posedge radio_clk);
+    fork
+      begin
+        for (int i = 1; i < 64; i = i + 2) begin
+          @(posedge radio_clk);
+          rx_frame  <= 1'b1;
+          rx_data   <= i;
+          @(negedge radio_clk);
+          rx_frame  <= 1'b0;
+          rx_data   <= i+1;
+        end
+      end
+      begin
+        while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk);
+        for (int i = 1; i < 64; i = i + 2) begin
+          // RX should be replicated across both ports
+          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");
+          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");
+          `ASSERT_ERROR(rx_i1 == i,   "RX1 I incorrect!");
+          `ASSERT_ERROR(rx_q1 == i+1, "RX1 Q incorrect!");
+          @(posedge radio_clk);
+        end
+      end
+    join
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Test RX channels 0 & 1 (MIMO mode)");
+    mimo      <= 1'b1;
+    rx_frame  <= 1'b0;
+    rx_data   <= 'd0;
+    repeat (10) @(posedge radio_clk);
+    fork
+      begin
+        for (int i = 1; i < 64; i = i + 2) begin
+          @(posedge radio_clk);
+          rx_frame  <= ~rx_frame;
+          rx_data   <= i;
+          @(negedge radio_clk);
+          rx_data   <= i+1;
+        end
+      end
+      begin
+        while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk);
+        for (int i = 1; i < 32; i = i + 4) begin
+          // RX should be replicated across both ports
+          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");
+          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");
+          @(posedge radio_clk);
+          `ASSERT_ERROR(rx_i1 == i+2, "RX1 I incorrect!");
+          `ASSERT_ERROR(rx_q1 == i+3, "RX1 Q incorrect!");
+          @(posedge radio_clk);
+        end
+      end
+    join
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Test TX channel 0");
+    mimo  <= 1'b0;
+    tx_i0 <= 'd0;
+    tx_q0 <= 'd0;
+    tx_i1 <= 'd0;
+    tx_q1 <= 'd0;
+    repeat (10) @(posedge radio_clk);
+    // TX0
+    fork
+      begin
+        for (int i = 1; i < 64; i = i + 2) begin
+          tx_i0 <= i;
+          tx_q0 <= i+1;
+          @(posedge radio_clk);
+        end
+      end
+      begin
+        while (tx_data == 12'd0) @(posedge tx_clk);
+        for (int i = 1; i < 64; i = i + 2) begin
+          // RX should be replicated across both ports
+          `ASSERT_ERROR(tx_data  == i, "TX0 I data incorrect!");
+          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
+          @(negedge tx_clk);
+          `ASSERT_ERROR(tx_data  == i+1, "TX0 Q data incorrect!");
+          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
+          @(posedge tx_clk);
+        end
+      end
+    join
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Test TX channel 1");
+    mimo  <= 1'b0;
+    tx_i0 <= 'd0;
+    tx_q0 <= 'd0;
+    tx_i1 <= 'd0;
+    tx_q1 <= 'd0;
+    repeat (10) @(posedge radio_clk);
+    fork
+      begin
+        for (int i = 1; i < 64; i = i + 2) begin
+          tx_i1 <= i;
+          tx_q1 <= i+1;
+          @(posedge radio_clk);
+        end
+      end
+      begin
+        while (tx_data == 12'd0) @(posedge tx_clk);
+        for (int i = 1; i < 64; i = i + 2) begin
+          `ASSERT_ERROR(tx_data  == i, "TX1 I data incorrect!");
+          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
+          @(negedge tx_clk);
+          `ASSERT_ERROR(tx_data  == i+1, "TX1 Q data incorrect!");
+          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
+          @(posedge tx_clk);
+        end
+      end
+    join
+    `TEST_CASE_DONE(1);
+
+    `TEST_CASE_START("Test TX channel 0 & 1 (MIMO)");
+    mimo  <= 1'b1;
+    tx_i0 <= 'd0;
+    tx_q0 <= 'd0;
+    tx_i1 <= 'd0;
+    tx_q1 <= 'd0;
+    repeat (10) @(posedge radio_clk);
+    fork
+      begin
+        for (int i = 1; i < 32; i = i + 4) begin
+          tx_i0 <= i;
+          tx_q0 <= i+1;
+          tx_i1 <= i+2;
+          tx_q1 <= i+3;
+          @(posedge radio_clk);
+          while (tx_stb) @(posedge radio_clk);
+        end
+      end
+      begin
+        while (tx_data == 12'd0) @(posedge tx_clk);
+        for (int i = 1; i < 32; i = i + 4) begin
+          `ASSERT_ERROR(tx_data  == i, "TX0 I data incorrect!");
+          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
+          @(negedge tx_clk);
+          `ASSERT_ERROR(tx_data  == i+1, "TX0 Q data incorrect!");
+          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
+          @(posedge tx_clk);
+          `ASSERT_ERROR(tx_data  == i+2, "TX1 I data incorrect!");
+          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
+          @(negedge tx_clk);
+          `ASSERT_ERROR(tx_data  == i+3, "TX1 Q data incorrect!");
+          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
+          @(posedge tx_clk);
+        end
+      end
+    join
+    `TEST_CASE_DONE(1);
+    `TEST_BENCH_DONE;
+  end
+
+endmodule