diff options
Diffstat (limited to 'fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile')
| -rw-r--r-- | fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile new file mode 100644 index 000000000..bf4922c21 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile @@ -0,0 +1,40 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (<device>/<package>/<speedgrade>) +ARCH = zynq +PART_ID= xc7z020/clg484/-1 + +DESIGN_SRCS = $(abspath ../../e310_io.v) \ + $(abspath $(addprefix $(BASE_DIR)/../lib/control/, \ + synchronizer.v \ + synchronizer_impl.v)) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = e310_io_tb + +SIM_SRCS = \ +$(abspath e310_io_tb.sv) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |