Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

21 files changed, 34984 insertions, 0 deletions

diff --git a/fpga/usrp3/top/e31x/ip/.gitignore b/fpga/usrp3/top/e31x/ip/.gitignore
new file mode 100644
index 000000000..a68476493
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/.gitignore
@@ -0,0 +1,2 @@
+vivado*
+managed_ip_project
diff --git a/fpga/usrp3/top/e31x/ip/Makefile.inc b/fpga/usrp3/top/e31x/ip/Makefile.inc
new file mode 100644
index 000000000..76bec9cdd
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/Makefile.inc
@@ -0,0 +1,68 @@
+#
+# Copyright 2014 Ettus Research
+#
+
+#include $(IP_DIR)/axi4_dualport_sram/Makefile.inc
+#include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
+#include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc
+#include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc
+#include $(IP_DIR)/ddr3_32bit/Makefile.inc
+include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
+include $(IP_DIR)/fifo_short_2clk/Makefile.inc
+#include $(IP_DIR)/input_sample_fifo/Makefile.inc
+#include $(IP_DIR)/misc_clock_gen/Makefile.inc
+#include $(IP_DIR)/axi3_to_axi4lite_protocol_converter/Makefile.inc
+#include $(IP_DIR)/axis_fifo_to_axi4lite/Makefile.inc
+#include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc
+#include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc
+include $(IP_DIR)/e31x_ps_bd/Makefile.inc
+include $(IP_DIR)/mig_7series_0/Makefile.inc
+
+BD_SRCS = \
+$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \
+$(IP_E31X_PS_BD_SRCS)
+
+IP_XCI_SRCS = \
+$(IP_FIFO_SHORT_2CLK_SRCS) \
+$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
+$(IP_AXI64_8K_2CLK_FIFO_SRCS) \
+$(IP_MIG_7SERIES_0_SRCS) \
+$(IP_FIFO_4K_2CLK_SRCS) \
+#$(IP_AXI4_BRAM_SRCS) \
+#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) \
+#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) \
+#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) \
+#$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) \
+#$(IP_MISC_CLOCK_GEN_SRCS) \
+
+IP_DRAM_XCI_SRCS = \
+$(IP_DDR3_32BIT_SRCS)
+
+## Currently unused
+## $(IP_INPUT_SAMPLE_FIFO_SRCS) \
+
+IP_SYNTH_OUTPUTS = \
+$(IP_FIFO_SHORT_2CLK_OUTS) \
+$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
+$(IP_AXI64_8K_2CLK_FIFO_OUTS) \
+$(IP_FIFO_4K_2CLK_OUTS) \
+$(IP_MIG_7SERIES_0_OUTS) \
+#$(IP_AXI4_BRAM_OUTS) \
+#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) \
+#$(IP_AXI_INTERCONNECT_OUTS) \
+#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) \
+#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) \
+#$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \
+
+BD_OUTPUTS = \
+$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \
+$(IP_E31X_PS_BD_OUTS)
+
+# Currently unused
+# $(IP_INPUT_SAMPLE_FIFO_OUTS) \
+# $(IP_AXI_INTERCON_4X64_128_OUTS) \
+
+ip: $(IP_SYNTH_OUTPUTS) $(BD_OUTPUTS)
+
+.PHONY: ip
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/Makefile.inc b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/Makefile.inc
new file mode 100644
index 000000000..d70c96edd
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/Makefile.inc
@@ -0,0 +1,35 @@
+#
+# Copyright 2018 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+include $(LIB_DIR)/rfnoc/utils/Makefile.srcs
+
+IP_E31X_PS_ORIG_SRCS = $(addprefix $(IP_DIR)/e31x_ps_bd/, \
+e31x_ps_bd.tcl \
+chdr_dma_rx.tcl \
+chdr_dma_tx.tcl \
+chdr_dma_frame_size.tcl \
+chdr_dma_top.tcl \
+)
+
+IP_E31X_PS_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/e31x_ps_bd/, \
+e31x_ps_bd.tcl \
+chdr_dma_rx.tcl \
+chdr_dma_tx.tcl \
+chdr_dma_frame_size.tcl \
+chdr_dma_top.tcl \
+)
+
+IP_E31X_PS_HDL_SRCS = $(RFNOC_UTIL_SRCS)
+
+IP_E31X_PS_BD_SRCS = $(IP_BUILD_DIR)/e31x_ps_bd/e31x_ps_bd/e31x_ps_bd.bd
+
+BD_E31X_PS_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/e31x_ps_bd/, \
+e31x_ps_bd.bd.out \
+e31x_ps_bd/e31x_ps_bd_ooc.xdc \
+)
+
+$(IP_E31X_PS_BD_SRCS) $(BD_E31X_PS_BD_OUTS) $(IP_E31X_PS_BDTCL_SRCS): $(IP_E31X_PS_ORIG_SRCS) $(IP_E31X_PS_HDL_SRCS)
+	$(call BUILD_VIVADO_BDTCL,e31x_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E31X_PS_HDL_SRCS))
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_frame_size.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_frame_size.tcl
new file mode 100644
index 000000000..387f67d9c
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_frame_size.tcl
@@ -0,0 +1,59 @@
+# Hierarchical cell: mtu
+proc create_hier_cell_mtu { parentCell nameHier numPorts } {
+
+  if { $parentCell eq "" || $nameHier eq "" } {
+     puts "ERROR: create_hier_cell_mtu() - Empty argument(s)!"
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     puts "ERROR: Unable to find parent cell <$parentCell>!"
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  # Create cells and wire everything up
+  create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs
+  connect_bd_net -net mtu_regs_1 [get_bd_pins mtu_regs]
+  # BUG: Vivado 2015.4 does not connect nets the first time with just the driver
+  connect_bd_net -quiet -net mtu_regs_1 [get_bd_pins mtu_regs]
+
+  for {set i 0} {$i < $numPorts} {incr i} {
+     # Create instance: xlslice_0, and set properties
+     set xlslice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_$i ]
+     set_property -dict [ list \
+        CONFIG.DIN_FROM [expr $i * 32 + 15] \
+        CONFIG.DIN_TO [expr $i * 32] \
+        CONFIG.DIN_WIDTH [expr $numPorts * 32] \
+        CONFIG.DOUT_WIDTH {16} \
+     ] $xlslice
+
+     connect_bd_net -net mtu_regs_1 [get_bd_pins $xlslice/Din]
+
+     create_bd_pin -dir O -from 15 -to 0 mtu$i
+     connect_bd_net [get_bd_pins mtu$i] [get_bd_pins $xlslice/Dout]
+  }
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_rx.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_rx.tcl
new file mode 100644
index 000000000..500771071
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_rx.tcl
@@ -0,0 +1,339 @@
+set scriptDir [file dirname [info script]]
+
+source "$scriptDir/chdr_dma_frame_size.tcl"
+
+proc create_hier_cell_rx_dma_channel { parentCell nameHier } {
+
+  if { $parentCell eq "" || $nameHier eq "" } {
+     puts "ERROR: create_hier_cell_dma() - Empty argument(s)!"
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     puts "ERROR: Unable to find parent cell <$parentCell>!"
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  #########################
+  # Pin list
+  #########################
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_dest_axi
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
+
+  create_bd_pin -dir I -from 15 -to 0 frame_size
+  create_bd_pin -dir O -type intr irq
+  create_bd_pin -dir I -type rst m_dest_axi_aresetn
+  create_bd_pin -dir I -type clk s_axi_aclk
+  create_bd_pin -dir I -type rst s_axi_aresetn
+  create_bd_pin -dir I -type clk s_axis_aclk
+
+  #########################
+  # Instantiate IPs
+  #########################
+  set reset_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_inv ]
+  set_property -dict [ list \
+     CONFIG.C_SIZE {1} \
+     CONFIG.C_OPERATION {not} \
+  ] $reset_inv
+
+  set chdr_padder [ create_bd_cell -type module -reference chdr_pad_packet chdr_padder ]
+  set_property -dict [ list \
+     CONFIG.CHDR_W {64} \
+  ] $chdr_padder
+  set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_pins chdr_padder/rst]
+
+  set axi_rx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_rx_dmac ]
+  set_property -dict [ list \
+     CONFIG.ASYNC_CLK_DEST_REQ {true} \
+     CONFIG.ASYNC_CLK_REQ_SRC {true} \
+     CONFIG.ASYNC_CLK_SRC_DEST {false} \
+     CONFIG.DMA_AXI_PROTOCOL_DEST {1} \
+     CONFIG.DMA_TYPE_SRC {1} \
+     CONFIG.SYNC_TRANSFER_START {false} \
+  ] $axi_rx_dmac
+
+  #########################
+  # Wiring
+  #########################
+
+  # Top-level connections
+  connect_bd_net -net aclk_1 \
+     [get_bd_pins s_axis_aclk] \
+     [get_bd_pins chdr_padder/clk] \
+     [get_bd_pins axi_rx_dmac/m_dest_axi_aclk] \
+     [get_bd_pins axi_rx_dmac/s_axis_aclk]
+  connect_bd_net -net aresetn_1 \
+     [get_bd_pins m_dest_axi_aresetn] \
+     [get_bd_pins reset_inv/Op1] \
+     [get_bd_pins axi_rx_dmac/m_dest_axi_aresetn]
+  connect_bd_net -net areset_1 \
+     [get_bd_pins reset_inv/Res] \
+     [get_bd_pins chdr_padder/rst]
+  connect_bd_net -net s_axi_aclk_1 \
+     [get_bd_pins s_axi_aclk] \
+     [get_bd_pins axi_rx_dmac/s_axi_aclk]
+  connect_bd_net -net s_axi_aresetn_1 \
+     [get_bd_pins s_axi_aresetn] \
+     [get_bd_pins axi_rx_dmac/s_axi_aresetn]
+  connect_bd_net -net axi_rx_dmac_irq \
+     [get_bd_pins irq] \
+     [get_bd_pins axi_rx_dmac/irq]
+  connect_bd_net -net mtu \
+     [get_bd_pins frame_size] \
+     [get_bd_pins chdr_padder/len]
+
+  # Control and DMA ports
+  connect_bd_intf_net -intf_net axi_rx_dmac_s_axi \
+     [get_bd_intf_pins s_axi] \
+     [get_bd_intf_pins axi_rx_dmac/s_axi]
+  connect_bd_intf_net -intf_net axi_rx_dmac_m_dest_axi \
+     [get_bd_intf_pins m_dest_axi] \
+     [get_bd_intf_pins axi_rx_dmac/m_dest_axi]
+
+  # AXI-Stream ports
+  connect_bd_intf_net -intf_net s_axis_dma \
+     [get_bd_intf_pins S_AXIS] \
+     [get_bd_intf_pins chdr_padder/s_axis]
+  connect_bd_intf_net -intf_net s_axis_dma_padded \
+     [get_bd_intf_pins chdr_padder/m_axis] \
+     [get_bd_intf_pins axi_rx_dmac/s_axis]
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
+# Hierarchical cell: rx
+proc create_hier_cell_rx_dma { parentCell nameHier numPorts } {
+
+  if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } {
+     puts "ERROR: create_hier_cell_rx() - Empty argument(s)!"
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     puts "ERROR: Unable to find parent cell <$parentCell>!"
+     return
+  }
+
+  if { $numPorts < 1 } {
+     puts "ERROR: numPorts invalid: $numPorts"
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  #########################
+  # Pin list
+  #########################
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_DMA
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac
+
+  create_bd_pin -dir I bus_clk
+  create_bd_pin -dir I bus_rstn
+  create_bd_pin -dir I clk40
+  create_bd_pin -dir I clk40_rstn
+  create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq
+  create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs
+  #########################
+  # Instantiate IPs
+  #########################
+  # For sharing one S_AXI_HP port across all RX DMA engines
+  set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
+  set_property -dict [ list \
+     CONFIG.CONNECTIVITY_MODE {SASD} \
+     CONFIG.NUM_MI {1} \
+     CONFIG.NUM_SI $numPorts \
+     CONFIG.R_REGISTER {1} \
+  ] $axi_crossbar_0
+
+  # For fanning out AXI-Lite bus to all RX DMA engines
+  set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
+  set_property -dict [ list \
+     CONFIG.NUM_MI $numPorts \
+  ] $axi_interconnect_0
+
+  # Routes AXI-Stream to appropriate RX DMA engine
+  set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ]
+  set_property -dict [ list \
+     CONFIG.DECODER_REG {1} \
+     CONFIG.NUM_MI $numPorts \
+     CONFIG.NUM_SI {1} \
+  ] $axis_switch_0
+
+  # Cross domains from incoming AXI-Stream to RX DMA engines domain
+  # Note that the fifo_generator_0 is hard-coded to have 4 TDEST bits, so we
+  # are limited to 16 RX DMA channels
+  set fifo_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 ]
+  set_property -dict [ list \
+     CONFIG.Clock_Type_AXI {Independent_Clock} \
+     CONFIG.Empty_Threshold_Assert_Value_axis {1021} \
+     CONFIG.Empty_Threshold_Assert_Value_rach {13} \
+     CONFIG.Empty_Threshold_Assert_Value_rdch {1021} \
+     CONFIG.Empty_Threshold_Assert_Value_wach {13} \
+     CONFIG.Empty_Threshold_Assert_Value_wdch {1021} \
+     CONFIG.Empty_Threshold_Assert_Value_wrch {13} \
+     CONFIG.Enable_TLAST {true} \
+     CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} \
+     CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} \
+     CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} \
+     CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} \
+     CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} \
+     CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} \
+     CONFIG.Full_Flags_Reset_Value {1} \
+     CONFIG.Full_Threshold_Assert_Value_axis {1023} \
+     CONFIG.Full_Threshold_Assert_Value_rach {15} \
+     CONFIG.Full_Threshold_Assert_Value_wach {15} \
+     CONFIG.Full_Threshold_Assert_Value_wrch {15} \
+     CONFIG.HAS_TKEEP {false} \
+     CONFIG.INTERFACE_TYPE {AXI_STREAM} \
+     CONFIG.Input_Depth_axis {1024} \
+     CONFIG.Reset_Type {Asynchronous_Reset} \
+     CONFIG.TDATA_NUM_BYTES {8} \
+     CONFIG.TDEST_WIDTH {4} \
+     CONFIG.TKEEP_WIDTH {0} \
+     CONFIG.TSTRB_WIDTH {8} \
+     CONFIG.TUSER_WIDTH {0} \
+  ] $fifo_generator_0
+
+  set rx_dmac_irq_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rx_dmac_irq_concat ]
+  set_property -dict [ list \
+     CONFIG.NUM_PORTS $numPorts \
+  ] $rx_dmac_irq_concat
+
+  create_hier_cell_mtu $hier_obj mtu $numPorts
+
+  #########################
+  # Wiring
+  #########################
+  connect_bd_intf_net -intf_net S00_AXIS_1 \
+     [get_bd_intf_pins S_AXIS_DMA] \
+     [get_bd_intf_pins fifo_generator_0/S_AXIS]
+
+  connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \
+     [get_bd_intf_pins M_AXI_RX_DMA] \
+     [get_bd_intf_pins axi_crossbar_0/M00_AXI]
+
+  connect_bd_intf_net -intf_net fifo_generator_0_M_AXIS \
+     [get_bd_intf_pins axis_switch_0/S00_AXIS] \
+     [get_bd_intf_pins fifo_generator_0/M_AXIS]
+
+  connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \
+     [get_bd_intf_pins s_axi_rx_dmac] \
+     [get_bd_intf_pins axi_interconnect_0/S00_AXI]
+
+  connect_bd_net -net aresetn_1 \
+     [get_bd_pins bus_rstn] \
+     [get_bd_pins fifo_generator_0/s_aresetn]
+  connect_bd_net -net bus_clk \
+     [get_bd_pins bus_clk] \
+     [get_bd_pins fifo_generator_0/s_aclk]
+
+  connect_bd_net -net clk40 \
+     [get_bd_pins clk40] \
+     [get_bd_pins axi_crossbar_0/aclk] \
+     [get_bd_pins axi_interconnect_0/ACLK] \
+     [get_bd_pins axi_interconnect_0/S00_ACLK] \
+     [get_bd_pins axis_switch_0/aclk] \
+     [get_bd_pins fifo_generator_0/m_aclk]
+
+  connect_bd_net -net clk40_rstn \
+     [get_bd_pins clk40_rstn] \
+     [get_bd_pins axi_crossbar_0/aresetn] \
+     [get_bd_pins axi_interconnect_0/ARESETN] \
+     [get_bd_pins axi_interconnect_0/S00_ARESETN] \
+     [get_bd_pins axis_switch_0/aresetn]
+
+  connect_bd_net -net mtu_regs_1 \
+     [get_bd_pins mtu_regs] \
+     [get_bd_pins mtu/mtu_regs]
+
+  connect_bd_net -net rx_dmac_irq_concat_dout \
+     [get_bd_pins irq] \
+     [get_bd_pins rx_dmac_irq_concat/dout]
+
+  #########################
+  # Per-port Section
+  #########################
+  for {set i 0} {$i < $numPorts} {incr i} {
+     puts "Instantiating rx_dma port ${i}"
+     create_hier_cell_rx_dma_channel $hier_obj dma$i
+
+     set_property -dict [ list \
+        [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} \
+     ] $axi_crossbar_0
+
+     connect_bd_intf_net -intf_net [format "axis_switch_0_M%02d_AXIS" ${i}] \
+        [get_bd_intf_pins [format "axis_switch_0/M%02d_AXIS" ${i}]] \
+        [get_bd_intf_pins dma${i}/S_AXIS]
+
+     connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \
+        [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \
+        [get_bd_intf_pins dma${i}/s_axi]
+
+     connect_bd_intf_net -intf_net dma${i}_m_dest_axi \
+        [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \
+        [get_bd_intf_pins dma${i}/m_dest_axi]
+
+     connect_bd_net -net clk40 \
+        [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]] \
+        [get_bd_pins dma${i}/s_axi_aclk] \
+        [get_bd_pins dma${i}/s_axis_aclk]
+
+     connect_bd_net -net clk40_rstn \
+        [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \
+        [get_bd_pins dma${i}/m_dest_axi_aresetn] \
+        [get_bd_pins dma${i}/s_axi_aresetn]
+
+     connect_bd_net -net dma${i}_irq \
+        [get_bd_pins dma${i}/irq] \
+        [get_bd_pins rx_dmac_irq_concat/In${i}]
+
+     connect_bd_net -net frame_size_${i} \
+        [get_bd_pins dma${i}/frame_size] \
+        [get_bd_pins mtu/mtu${i}]
+  }
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_top.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_top.tcl
new file mode 100644
index 000000000..9a4e832aa
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_top.tcl
@@ -0,0 +1,159 @@
+set scriptDir [file dirname [info script]]
+
+source "$scriptDir/chdr_dma_rx.tcl"
+source "$scriptDir/chdr_dma_tx.tcl"
+
+# Hierarchical cell: dma
+proc create_hier_cell_dma { parentCell nameHier numPorts } {
+
+  if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } {
+     puts "ERROR: create_hier_cell_dma() - Empty argument(s)!"
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     puts "ERROR: Unable to find parent cell <$parentCell>!"
+     return
+  }
+
+  if { $numPorts < 2 } {
+     puts "ERROR: numPorts invalid: $numPorts"
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  #########################
+  # Pin list
+  #########################
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_regfile
+
+  create_bd_pin -dir I bus_clk
+  create_bd_pin -dir I bus_rstn
+  create_bd_pin -dir I clk40
+  create_bd_pin -dir I clk40_rstn
+  create_bd_pin -dir O rx_irq
+  create_bd_pin -dir O tx_irq
+
+  #########################
+  # Instantiate IPs
+  #########################
+  # Create instance: rx
+  create_hier_cell_rx_dma $hier_obj rx $numPorts
+
+  # Create instance: tx
+  create_hier_cell_tx_dma $hier_obj tx $numPorts
+
+  # Used to set frame size of RX DMA engines
+  set axi_regfile_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_regfile:1.0 axi_regfile_0 ]
+  set_property -dict [ list \
+CONFIG.NUM_REGS $numPorts \
+ ] $axi_regfile_0
+
+  set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ]
+  set_property -dict [ list \
+CONFIG.C_OPERATION {or} \
+CONFIG.C_SIZE $numPorts \
+ ] $util_reduced_logic_0
+
+  set util_reduced_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_1 ]
+  set_property -dict [ list \
+CONFIG.C_OPERATION {or} \
+CONFIG.C_SIZE $numPorts \
+ ] $util_reduced_logic_1
+
+  #########################
+  # Wiring
+  #########################
+  # Clocks and resets
+  connect_bd_net -net bus_clk_1 \
+     [get_bd_pins bus_clk] \
+     [get_bd_pins rx/bus_clk] \
+     [get_bd_pins tx/bus_clk]
+  connect_bd_net -net bus_rstn_1 \
+     [get_bd_pins bus_rstn] \
+     [get_bd_pins rx/bus_rstn] \
+     [get_bd_pins tx/bus_rstn]
+  connect_bd_net -net clk40_1 \
+     [get_bd_pins clk40] \
+     [get_bd_pins rx/clk40] \
+     [get_bd_pins tx/clk40] \
+     [get_bd_pins axi_regfile_0/S_AXI_ACLK]
+  connect_bd_net -net clk40_rstn_1 \
+     [get_bd_pins clk40_rstn] \
+     [get_bd_pins axi_regfile_0/S_AXI_ARESETN] \
+     [get_bd_pins rx/clk40_rstn] \
+     [get_bd_pins tx/clk40_rstn]
+
+  # AXI buses
+  connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \
+     [get_bd_intf_pins s_axi_rx_dmac] \
+     [get_bd_intf_pins rx/s_axi_rx_dmac]
+  connect_bd_intf_net -intf_net rx_dma_M_AXI_RX_DMA \
+     [get_bd_intf_pins M_AXI_RX_DMA] \
+     [get_bd_intf_pins rx/M_AXI_RX_DMA]
+  connect_bd_intf_net -intf_net s_axi_tx_dmac_1 \
+     [get_bd_intf_pins s_axi_tx_dmac] \
+     [get_bd_intf_pins tx/s_axi_tx_dmac]
+  connect_bd_intf_net -intf_net tx_M_AXI_TX_DMA \
+     [get_bd_intf_pins M_AXI_TX_DMA] \
+     [get_bd_intf_pins tx/M_AXI_TX_DMA]
+  connect_bd_intf_net -intf_net s_axi_regfile_1 \
+     [get_bd_intf_pins s_axi_regfile] \
+     [get_bd_intf_pins axi_regfile_0/S_AXI]
+
+  # RX CHDR
+  connect_bd_intf_net -intf_net s_axis_dma_1 \
+     [get_bd_intf_pins s_axis_dma] \
+     [get_bd_intf_pins rx/S_AXIS_DMA]
+
+  # TX CHDR
+  connect_bd_intf_net -intf_net m_axis_dma_1 \
+     [get_bd_intf_pins tx/M_AXIS_DMA] \
+     [get_bd_intf_pins m_axis_dma]
+
+  # IRQs and Frame Sizes
+  connect_bd_net -net frame_sizes \
+     [get_bd_pins axi_regfile_0/regs] \
+     [get_bd_pins rx/mtu_regs]
+  connect_bd_net -net rx_irq1 \
+     [get_bd_pins rx/irq] \
+     [get_bd_pins util_reduced_logic_0/Op1]
+  connect_bd_net -net tx_irq1 \
+     [get_bd_pins tx/irq] \
+     [get_bd_pins util_reduced_logic_1/Op1]
+  connect_bd_net -net util_reduced_logic_0_Res \
+     [get_bd_pins rx_irq] \
+     [get_bd_pins util_reduced_logic_0/Res]
+  connect_bd_net -net util_reduced_logic_1_Res \
+     [get_bd_pins tx_irq] \
+     [get_bd_pins util_reduced_logic_1/Res]
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_tx.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_tx.tcl
new file mode 100644
index 000000000..e2d160f69
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_tx.tcl
@@ -0,0 +1,193 @@
+# Hierarchical cell: tx
+proc create_hier_cell_tx_dma { parentCell nameHier numPorts } {
+
+  if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } {
+     puts "ERROR: create_hier_cell_tx() - Empty argument(s)!"
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     puts "ERROR: Unable to find parent cell <$parentCell>!"
+     return
+  }
+
+  if { $numPorts < 1 } {
+     puts "ERROR: numPorts invalid: $numPorts"
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  #########################
+  # Pin list
+  #########################
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DMA
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac
+
+  create_bd_pin -dir I bus_clk
+  create_bd_pin -dir I bus_rstn
+  create_bd_pin -dir I clk40
+  create_bd_pin -dir I clk40_rstn
+  create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq
+
+  #########################
+  # Instantiate IPs
+  #########################
+  set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
+  set_property -dict [ list \
+     CONFIG.NUM_MI $numPorts \
+ ] $axi_interconnect_0
+
+  set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
+  set_property -dict [ list \
+     CONFIG.NUM_MI {1} \
+     CONFIG.NUM_SI $numPorts
+ ] $axi_crossbar_0
+
+  set axis_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_0 ]
+  set_property -dict [ list \
+     CONFIG.ARB_ON_TLAST {1} \
+     CONFIG.ARB_ON_MAX_XFERS {0} \
+     CONFIG.ENABLE_ADVANCED_OPTIONS {1} \
+     CONFIG.M00_HAS_REGSLICE {1} \
+     CONFIG.NUM_MI {1} \
+     CONFIG.NUM_SI $numPorts \
+  ] $axis_interconnect_0
+
+  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+  set_property -dict [ list \
+     CONFIG.NUM_PORTS $numPorts \
+  ] $xlconcat_0
+
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+  set_property -dict [ list \
+CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+  #########################
+  # Wiring
+  #########################
+  connect_bd_net -net bus_clk \
+     [get_bd_pins bus_clk] \
+     [get_bd_pins axis_interconnect_0/ACLK] \
+     [get_bd_pins axis_interconnect_0/M00_AXIS_ACLK]
+  connect_bd_net -net bus_rstn \
+     [get_bd_pins bus_rstn] \
+     [get_bd_pins axis_interconnect_0/ARESETN] \
+     [get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN]
+  connect_bd_net -net clk40 \
+     [get_bd_pins clk40] \
+     [get_bd_pins axi_crossbar_0/aclk] \
+     [get_bd_pins axi_interconnect_0/ACLK] \
+     [get_bd_pins axi_interconnect_0/S00_ACLK]
+  connect_bd_net -net clk40_rstn \
+     [get_bd_pins clk40_rstn] \
+     [get_bd_pins axi_crossbar_0/aresetn] \
+     [get_bd_pins axi_interconnect_0/ARESETN] \
+     [get_bd_pins axi_interconnect_0/S00_ARESETN]
+
+  connect_bd_net -net xlconstant_0_dout \
+     [get_bd_pins xlconstant_0/dout]
+  connect_bd_net -net xlconcat_0_dout \
+     [get_bd_pins irq] \
+     [get_bd_pins xlconcat_0/dout]
+
+  connect_bd_intf_net -intf_net M_AXI_TX_DMAC_1 \
+     [get_bd_intf_pins s_axi_tx_dmac] \
+     [get_bd_intf_pins axi_interconnect_0/S00_AXI]
+  connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \
+     [get_bd_intf_pins M_AXI_TX_DMA] \
+     [get_bd_intf_pins axi_crossbar_0/M00_AXI]
+  connect_bd_intf_net -intf_net axis_interconnect_0_M00_AXIS \
+     [get_bd_intf_pins M_AXIS_DMA] \
+     [get_bd_intf_pins axis_interconnect_0/M00_AXIS]
+
+  #########################
+  # Per-port Section
+  #########################
+  for {set i 0} {$i < $numPorts} {incr i} {
+     # Configure each port on axi_crossbar and axis_interconnect
+     puts "Creating TX dma port ${i}"
+     set_property [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} $axi_crossbar_0
+     set_property -dict [ list \
+        [format "CONFIG.S%02d_HAS_REGSLICE" ${i}] {1} \
+     ] $axis_interconnect_0
+
+     set axi_tx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_tx_dmac_$i ]
+     set_property -dict [ list \
+        CONFIG.DMA_TYPE_DEST {1} \
+        CONFIG.DMA_TYPE_SRC {0} \
+     ] $axi_tx_dmac
+
+     # Add a tuser signal indicating which DMA channel originated the packet
+     # Hard-coded to handle up to 16 DMA channels
+     # Convert i (in decimal) to 4-bit binary:
+     binary scan [binary format c ${i}] B* i_binary
+     set i_binary [string range ${i_binary} end-3 end]
+
+     set tuser_appender [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_${i} ]
+     set_property -dict [ list \
+        CONFIG.M_TUSER_WIDTH.VALUE_SRC USER \
+     ] $tuser_appender
+     set_property -dict [ list \
+        CONFIG.M_TUSER_WIDTH {4} \
+        CONFIG.TUSER_REMAP 4'b${i_binary} \
+     ] $tuser_appender
+
+     connect_bd_intf_net -intf_net [format "axis_subset_converter_%d_S_AXIS" ${i}] \
+        [get_bd_intf_pins $axi_tx_dmac/m_axis] \
+        [get_bd_intf_pins ${tuser_appender}/S_AXIS]
+     connect_bd_intf_net -intf_net [format "S%02d_AXIS_1" ${i}] \
+        [get_bd_intf_pins ${tuser_appender}/M_AXIS] \
+        [get_bd_intf_pins [format "axis_interconnect_0/S%02d_AXIS" ${i}]]
+     connect_bd_intf_net -intf_net axi_dmac_${i}_m_src_axi \
+        [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \
+        [get_bd_intf_pins $axi_tx_dmac/m_src_axi]
+     connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \
+        [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \
+        [get_bd_intf_pins $axi_tx_dmac/s_axi]
+
+     connect_bd_net [get_bd_pins $axi_tx_dmac/irq] [get_bd_pins xlconcat_0/In${i}]
+
+     connect_bd_net -net clk40 \
+        [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]]\
+        [get_bd_pins $axi_tx_dmac/m_axis_aclk] \
+        [get_bd_pins $axi_tx_dmac/m_src_axi_aclk] \
+        [get_bd_pins $axi_tx_dmac/s_axi_aclk] \
+	[get_bd_pins $tuser_appender/aclk] \
+        [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ACLK" ${i}]]
+
+     connect_bd_net -net clk40_rstn \
+        [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \
+        [get_bd_pins $axi_tx_dmac/m_src_axi_aresetn] \
+        [get_bd_pins $axi_tx_dmac/s_axi_aresetn] \
+	[get_bd_pins $tuser_appender/aresetn] \
+        [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ARESETN" ${i}]]
+
+     connect_bd_net -net xlconstant_0_dout \
+        [get_bd_pins [format "axis_interconnect_0/S%02d_ARB_REQ_SUPPRESS" ${i}]]
+  }
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps.tcl
new file mode 100644
index 000000000..b54ef7efc
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps.tcl
@@ -0,0 +1,432 @@
+proc getPresetInfo {} {
+  return [dict create name {e31x_ps} description {e31x_ps}  vlnv xilinx.com:ip:processing_system7:5.5 display_name {e31x_ps} ]
+}
+
+proc validate_preset {IPINST} { return true }
+
+
+proc apply_preset {IPINST} {
+  return [dict create \
+    CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF}  \
+    CONFIG.PCW_FCLK_CLK1_BUF {TRUE}  \
+    CONFIG.PCW_FCLK_CLK2_BUF {TRUE}  \
+    CONFIG.PCW_FCLK_CLK3_BUF {TRUE}  \
+    CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3}  \
+    CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15}  \
+    CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10}  \
+    CONFIG.PCW_UIPARAM_DDR_CL {7}  \
+    CONFIG.PCW_UIPARAM_DDR_CWL {6}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RCD {7}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RP {7}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RC {48.75}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0}  \
+    CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090}  \
+    CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000}  \
+    CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666}  \
+    CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {144.444443}  \
+    CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40}  \
+    CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667}  \
+    CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200}  \
+    CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {866.666687}  \
+    CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374}  \
+    CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730}  \
+    CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000}  \
+    CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000}  \
+    CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000}  \
+    CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672}  \
+    CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {144.444443}  \
+    CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000}  \
+    CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000}  \
+    CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672}  \
+    CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {144.444443}  \
+    CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {144.444443}  \
+    CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {144.444443}  \
+    CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {144.444443}  \
+    CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {144.444443}  \
+    CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {144.444443}  \
+    CONFIG.PCW_CLK0_FREQ {100000000}  \
+    CONFIG.PCW_CLK1_FREQ {40000000}  \
+    CONFIG.PCW_CLK2_FREQ {166666672}  \
+    CONFIG.PCW_CLK3_FREQ {200000000}  \
+    CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2}  \
+    CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2}  \
+    CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20}  \
+    CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20}  \
+    CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {12}  \
+    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5}  \
+    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10}  \
+    CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4}  \
+    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5}  \
+    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4}  \
+    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5}  \
+    CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {3}  \
+    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {16}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15}  \
+    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7}  \
+    CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10}  \
+    CONFIG.PCW_ARMPLL_CTRL_FBDIV {52}  \
+    CONFIG.PCW_IOPLL_CTRL_FBDIV {60}  \
+    CONFIG.PCW_DDRPLL_CTRL_FBDIV {32}  \
+    CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1733.333}  \
+    CONFIG.PCW_IO_IO_PLL_FREQMHZ {2000.000}  \
+    CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_VALID {1}  \
+    CONFIG.PCW_SPI_PERIPHERAL_VALID {1}  \
+    CONFIG.PCW_UART_PERIPHERAL_VALID {1}  \
+    CONFIG.PCW_EN_EMIO_ENET0 {0}  \
+    CONFIG.PCW_EN_EMIO_GPIO {1}  \
+    CONFIG.PCW_EN_EMIO_I2C1 {0}  \
+    CONFIG.PCW_EN_EMIO_PJTAG {0}  \
+    CONFIG.PCW_EN_EMIO_SPI0 {1}  \
+    CONFIG.PCW_EN_EMIO_SPI1 {1}  \
+    CONFIG.PCW_EN_EMIO_UART0 {0}  \
+    CONFIG.PCW_USE_S_AXI_GP0 {0}  \
+    CONFIG.PCW_USE_S_AXI_GP1 {0}  \
+    CONFIG.PCW_USE_S_AXI_HP0 {0}  \
+    CONFIG.PCW_USE_S_AXI_HP1 {1}  \
+    CONFIG.PCW_USE_S_AXI_HP2 {1}  \
+    CONFIG.PCW_USE_S_AXI_HP3 {0}  \
+    CONFIG.PCW_USE_FABRIC_INTERRUPT {1}  \
+    CONFIG.PCW_USE_HIGH_OCM {1}  \
+    CONFIG.PCW_USE_PS_SLCR_REGISTERS {1}  \
+    CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64}  \
+    CONFIG.PCW_EN_ENET0 {1}  \
+    CONFIG.PCW_EN_GPIO {1}  \
+    CONFIG.PCW_EN_I2C0 {1}  \
+    CONFIG.PCW_EN_I2C1 {0}  \
+    CONFIG.PCW_EN_PJTAG {0}  \
+    CONFIG.PCW_EN_SDIO0 {1}  \
+    CONFIG.PCW_EN_SPI0 {1}  \
+    CONFIG.PCW_EN_SPI1 {1}  \
+    CONFIG.PCW_EN_UART0 {1}  \
+    CONFIG.PCW_EN_UART1 {1}  \
+    CONFIG.PCW_EN_USB0 {1}  \
+    CONFIG.PCW_EN_CLK1_PORT {1}  \
+    CONFIG.PCW_EN_CLK2_PORT {1}  \
+    CONFIG.PCW_EN_CLK3_PORT {1}  \
+    CONFIG.PCW_EN_RST1_PORT {0}  \
+    CONFIG.PCW_EN_RST2_PORT {0}  \
+    CONFIG.PCW_EN_RST3_PORT {0}  \
+    CONFIG.PCW_IRQ_F2P_INTR {1}  \
+    CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}  \
+    CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}  \
+    CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}  \
+    CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits}  \
+    CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits}  \
+    CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}  \
+    CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}  \
+    CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}  \
+    CONFIG.PCW_ENET_RESET_ENABLE {1}  \
+    CONFIG.PCW_ENET_RESET_SELECT {Share reset pin}  \
+    CONFIG.PCW_ENET0_RESET_ENABLE {1}  \
+    CONFIG.PCW_ENET0_RESET_IO {MIO 3}  \
+    CONFIG.PCW_ENET1_RESET_ENABLE {0}  \
+    CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45}  \
+    CONFIG.PCW_SD0_GRP_CD_ENABLE {0}  \
+    CONFIG.PCW_SD0_GRP_WP_ENABLE {0}  \
+    CONFIG.PCW_SD0_GRP_POW_ENABLE {0}  \
+    CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15}  \
+    CONFIG.PCW_UART0_GRP_FULL_ENABLE {0}  \
+    CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49}  \
+    CONFIG.PCW_UART1_GRP_FULL_ENABLE {0}  \
+    CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_SPI0_SPI0_IO {EMIO}  \
+    CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1}  \
+    CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO}  \
+    CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1}  \
+    CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO}  \
+    CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1}  \
+    CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO}  \
+    CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_SPI1_SPI1_IO {EMIO}  \
+    CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1}  \
+    CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO}  \
+    CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1}  \
+    CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO}  \
+    CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1}  \
+    CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO}  \
+    CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_PJTAG_PJTAG_IO {<Select>}  \
+    CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39}  \
+    CONFIG.PCW_USB_RESET_ENABLE {1}  \
+    CONFIG.PCW_USB_RESET_SELECT {Share reset pin}  \
+    CONFIG.PCW_USB0_RESET_ENABLE {1}  \
+    CONFIG.PCW_USB0_RESET_IO {MIO 4}  \
+    CONFIG.PCW_USB1_RESET_ENABLE {0}  \
+    CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47}  \
+    CONFIG.PCW_I2C0_GRP_INT_ENABLE {0}  \
+    CONFIG.PCW_I2C0_RESET_ENABLE {0}  \
+    CONFIG.PCW_I2C0_RESET_IO {<Select>}  \
+    CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_I2C1_I2C1_IO {<Select>}  \
+    CONFIG.PCW_I2C1_GRP_INT_ENABLE {0}  \
+    CONFIG.PCW_I2C_RESET_ENABLE {0}  \
+    CONFIG.PCW_I2C_RESET_SELECT {<Select>}  \
+    CONFIG.PCW_I2C1_RESET_ENABLE {0}  \
+    CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}  \
+    CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}  \
+    CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}  \
+    CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_MIO_0_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_0_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_0_SLEW {slow}  \
+    CONFIG.PCW_MIO_1_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_1_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_1_SLEW {slow}  \
+    CONFIG.PCW_MIO_2_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_2_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_2_SLEW {slow}  \
+    CONFIG.PCW_MIO_3_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_3_DIRECTION {out}  \
+    CONFIG.PCW_MIO_3_SLEW {slow}  \
+    CONFIG.PCW_MIO_4_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_4_DIRECTION {out}  \
+    CONFIG.PCW_MIO_4_SLEW {slow}  \
+    CONFIG.PCW_MIO_5_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_5_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_5_SLEW {slow}  \
+    CONFIG.PCW_MIO_6_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_6_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_6_SLEW {slow}  \
+    CONFIG.PCW_MIO_7_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_7_DIRECTION {out}  \
+    CONFIG.PCW_MIO_7_SLEW {slow}  \
+    CONFIG.PCW_MIO_8_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_8_DIRECTION {out}  \
+    CONFIG.PCW_MIO_8_SLEW {slow}  \
+    CONFIG.PCW_MIO_9_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_9_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_9_SLEW {slow}  \
+    CONFIG.PCW_MIO_10_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_10_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_10_SLEW {slow}  \
+    CONFIG.PCW_MIO_11_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_11_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_11_SLEW {slow}  \
+    CONFIG.PCW_MIO_12_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_12_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_12_SLEW {slow}  \
+    CONFIG.PCW_MIO_13_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_13_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_13_SLEW {slow}  \
+    CONFIG.PCW_MIO_14_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_14_DIRECTION {in}  \
+    CONFIG.PCW_MIO_14_SLEW {slow}  \
+    CONFIG.PCW_MIO_15_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_15_DIRECTION {out}  \
+    CONFIG.PCW_MIO_15_SLEW {slow}  \
+    CONFIG.PCW_MIO_16_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_16_DIRECTION {out}  \
+    CONFIG.PCW_MIO_16_SLEW {fast}  \
+    CONFIG.PCW_MIO_17_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_17_DIRECTION {out}  \
+    CONFIG.PCW_MIO_17_SLEW {fast}  \
+    CONFIG.PCW_MIO_18_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_18_DIRECTION {out}  \
+    CONFIG.PCW_MIO_18_SLEW {fast}  \
+    CONFIG.PCW_MIO_19_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_19_DIRECTION {out}  \
+    CONFIG.PCW_MIO_19_SLEW {fast}  \
+    CONFIG.PCW_MIO_20_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_20_DIRECTION {out}  \
+    CONFIG.PCW_MIO_20_SLEW {fast}  \
+    CONFIG.PCW_MIO_21_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_21_DIRECTION {out}  \
+    CONFIG.PCW_MIO_21_SLEW {fast}  \
+    CONFIG.PCW_MIO_22_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_22_DIRECTION {in}  \
+    CONFIG.PCW_MIO_22_SLEW {fast}  \
+    CONFIG.PCW_MIO_23_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_23_DIRECTION {in}  \
+    CONFIG.PCW_MIO_23_SLEW {fast}  \
+    CONFIG.PCW_MIO_24_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_24_DIRECTION {in}  \
+    CONFIG.PCW_MIO_24_SLEW {fast}  \
+    CONFIG.PCW_MIO_25_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_25_DIRECTION {in}  \
+    CONFIG.PCW_MIO_25_SLEW {fast}  \
+    CONFIG.PCW_MIO_26_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_26_DIRECTION {in}  \
+    CONFIG.PCW_MIO_26_SLEW {fast}  \
+    CONFIG.PCW_MIO_27_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_27_DIRECTION {in}  \
+    CONFIG.PCW_MIO_27_SLEW {fast}  \
+    CONFIG.PCW_MIO_28_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_28_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_28_SLEW {slow}  \
+    CONFIG.PCW_MIO_29_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_29_DIRECTION {in}  \
+    CONFIG.PCW_MIO_29_SLEW {slow}  \
+    CONFIG.PCW_MIO_30_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_30_DIRECTION {out}  \
+    CONFIG.PCW_MIO_30_SLEW {slow}  \
+    CONFIG.PCW_MIO_31_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_31_DIRECTION {in}  \
+    CONFIG.PCW_MIO_31_SLEW {slow}  \
+    CONFIG.PCW_MIO_32_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_32_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_32_SLEW {slow}  \
+    CONFIG.PCW_MIO_33_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_33_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_33_SLEW {slow}  \
+    CONFIG.PCW_MIO_34_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_34_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_34_SLEW {slow}  \
+    CONFIG.PCW_MIO_35_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_35_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_35_SLEW {slow}  \
+    CONFIG.PCW_MIO_36_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_36_DIRECTION {in}  \
+    CONFIG.PCW_MIO_36_SLEW {slow}  \
+    CONFIG.PCW_MIO_37_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_37_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_37_SLEW {slow}  \
+    CONFIG.PCW_MIO_38_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_38_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_38_SLEW {slow}  \
+    CONFIG.PCW_MIO_39_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_39_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_39_SLEW {slow}  \
+    CONFIG.PCW_MIO_40_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_40_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_40_SLEW {slow}  \
+    CONFIG.PCW_MIO_41_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_41_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_41_SLEW {slow}  \
+    CONFIG.PCW_MIO_42_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_42_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_42_SLEW {slow}  \
+    CONFIG.PCW_MIO_43_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_43_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_43_SLEW {slow}  \
+    CONFIG.PCW_MIO_44_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_44_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_44_SLEW {slow}  \
+    CONFIG.PCW_MIO_45_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_45_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_45_SLEW {slow}  \
+    CONFIG.PCW_MIO_46_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_46_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_46_SLEW {slow}  \
+    CONFIG.PCW_MIO_47_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_47_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_47_SLEW {slow}  \
+    CONFIG.PCW_MIO_48_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_48_DIRECTION {out}  \
+    CONFIG.PCW_MIO_48_SLEW {slow}  \
+    CONFIG.PCW_MIO_49_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_49_DIRECTION {in}  \
+    CONFIG.PCW_MIO_49_SLEW {slow}  \
+    CONFIG.PCW_MIO_50_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_50_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_50_SLEW {slow}  \
+    CONFIG.PCW_MIO_51_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_51_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_51_SLEW {slow}  \
+    CONFIG.PCW_MIO_52_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_52_DIRECTION {out}  \
+    CONFIG.PCW_MIO_52_SLEW {slow}  \
+    CONFIG.PCW_MIO_53_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_53_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_53_SLEW {slow}  \
+    CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#ENET Reset#USB Reset#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0}  \
+    CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#reset#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio}  \
+    CONFIG.PCW_FPGA_FCLK0_ENABLE {1}  \
+    CONFIG.PCW_FPGA_FCLK1_ENABLE {1}  \
+    CONFIG.PCW_FPGA_FCLK2_ENABLE {1}  \
+    CONFIG.PCW_FPGA_FCLK3_ENABLE {1}  \
+  ]
+}
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
new file mode 100644
index 000000000..b6b3cb1e5
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
@@ -0,0 +1,720 @@
+# CHANGE DESIGN NAME HERE
+set design_name e31x_ps_bd
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+create_bd_design $design_name
+current_bd_design $design_name
+
+if { $nRet != 0 } {
+   puts $errMsg
+   return $nRet
+}
+
+set scriptDir [file dirname [info script]]
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+source "$scriptDir/chdr_dma_top.tcl"
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     puts "ERROR: Unable to find parent cell <$parentCell>!"
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+  set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ]
+  set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ]
+  set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ]
+  set_property -dict [ list \
+   CONFIG.HAS_TLAST 1 \
+   CONFIG.TDATA_NUM_BYTES 8 \
+   CONFIG.TDEST_WIDTH 4 \
+  ] $s_axis_dma
+  set m_axi_pmu [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_pmu ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.DATA_WIDTH {32} \
+   CONFIG.FREQ_HZ {40000000} \
+   CONFIG.HAS_BURST {0} \
+   CONFIG.HAS_CACHE {0} \
+   CONFIG.HAS_LOCK {0} \
+   CONFIG.HAS_PROT {0} \
+   CONFIG.HAS_QOS {0} \
+   CONFIG.HAS_WSTRB {0} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.PROTOCOL {AXI4LITE} \
+   ] $m_axi_pmu
+  set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.DATA_WIDTH {32} \
+   CONFIG.FREQ_HZ {40000000} \
+   CONFIG.HAS_BURST {0} \
+   CONFIG.HAS_CACHE {0} \
+   CONFIG.HAS_LOCK {0} \
+   CONFIG.HAS_PROT {0} \
+   CONFIG.HAS_QOS {0} \
+   CONFIG.HAS_WSTRB {0} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.PROTOCOL {AXI4LITE} \
+   ] $m_axi_xbar
+  set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ]
+
+  # Create ports
+  set DDR_VRN [ create_bd_port -dir IO DDR_VRN ]
+  set DDR_VRP [ create_bd_port -dir IO DDR_VRP ]
+  set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
+  set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ]
+  set FCLK_CLK2 [ create_bd_port -dir O -type clk FCLK_CLK2 ]
+  set FCLK_CLK3 [ create_bd_port -dir O -type clk FCLK_CLK3 ]
+  set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ]
+  set IRQ_F2P [ create_bd_port -dir I -from 15 -to 0 -type intr IRQ_F2P ]
+  set_property -dict [ list \
+   CONFIG.PortWidth {16} \
+   CONFIG.SENSITIVITY {EDGE_RISING} \
+ ] $IRQ_F2P
+  set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ]
+  set PS_CLK [ create_bd_port -dir IO PS_CLK ]
+  set PS_PORB [ create_bd_port -dir IO PS_PORB ]
+  set PS_SRSTB [ create_bd_port -dir IO PS_SRSTB ]
+  set SPI0_MISO_I [ create_bd_port -dir I SPI0_MISO_I ]
+  set SPI0_MISO_O [ create_bd_port -dir O SPI0_MISO_O ]
+  set SPI0_MISO_T [ create_bd_port -dir O SPI0_MISO_T ]
+  set SPI0_MOSI_I [ create_bd_port -dir I SPI0_MOSI_I ]
+  set SPI0_MOSI_O [ create_bd_port -dir O SPI0_MOSI_O ]
+  set SPI0_MOSI_T [ create_bd_port -dir O SPI0_MOSI_T ]
+  set SPI0_SCLK_I [ create_bd_port -dir I SPI0_SCLK_I ]
+  set SPI0_SCLK_O [ create_bd_port -dir O SPI0_SCLK_O ]
+  set SPI0_SCLK_T [ create_bd_port -dir O SPI0_SCLK_T ]
+  set SPI0_SS1_O [ create_bd_port -dir O SPI0_SS1_O ]
+  set SPI0_SS2_O [ create_bd_port -dir O SPI0_SS2_O ]
+  set SPI0_SS_I [ create_bd_port -dir I SPI0_SS_I ]
+  set SPI0_SS_O [ create_bd_port -dir O SPI0_SS_O ]
+  set SPI0_SS_T [ create_bd_port -dir O SPI0_SS_T ]
+  set SPI1_MISO_I [ create_bd_port -dir I SPI1_MISO_I ]
+  set SPI1_MISO_O [ create_bd_port -dir O SPI1_MISO_O ]
+  set SPI1_MISO_T [ create_bd_port -dir O SPI1_MISO_T ]
+  set SPI1_MOSI_I [ create_bd_port -dir I SPI1_MOSI_I ]
+  set SPI1_MOSI_O [ create_bd_port -dir O SPI1_MOSI_O ]
+  set SPI1_MOSI_T [ create_bd_port -dir O SPI1_MOSI_T ]
+  set SPI1_SCLK_I [ create_bd_port -dir I SPI1_SCLK_I ]
+  set SPI1_SCLK_O [ create_bd_port -dir O SPI1_SCLK_O ]
+  set SPI1_SCLK_T [ create_bd_port -dir O SPI1_SCLK_T ]
+  set SPI1_SS1_O [ create_bd_port -dir O SPI1_SS1_O ]
+  set SPI1_SS2_O [ create_bd_port -dir O SPI1_SS2_O ]
+  set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ]
+  set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ]
+  set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ]
+  set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \
+   CONFIG.FREQ_HZ {40000000} \
+ ] $S_AXI_GP0_ACLK
+  set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ]
+  set bus_clk [ create_bd_port -dir I -type clk bus_clk ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \
+   CONFIG.ASSOCIATED_RESET {bus_rstn} \
+   CONFIG.FREQ_HZ {200000000} \
+ ] $bus_clk
+  set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ]
+  set clk40 [ create_bd_port -dir I -type clk clk40 ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {m_axi_xbar:m_axi_pmu} \
+   CONFIG.ASSOCIATED_RESET {clk40_rstn} \
+   CONFIG.FREQ_HZ {40000000} \
+ ] $clk40
+  set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
+
+  # Create instance: axi_interconnect_0, and set properties
+  set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
+  set_property -dict [ list \
+   CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
+   CONFIG.NUM_MI {5} \
+ ] $axi_interconnect_0
+
+  # Create instance: dma
+  create_hier_cell_dma [current_bd_instance .] dma 5
+
+  # Create instance: processing_system7_0, and set properties
+  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+  set_property -dict [ list \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000} \
+   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672} \
+   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
+   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_CLK0_FREQ {100000000} \
+   CONFIG.PCW_CLK1_FREQ {40000000} \
+   CONFIG.PCW_CLK2_FREQ {166666672} \
+   CONFIG.PCW_CLK3_FREQ {200000000} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+   CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
+   CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+   CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET0_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET0_RESET_IO {MIO 11} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_EN_CLK1_PORT {1} \
+   CONFIG.PCW_EN_CLK2_PORT {1} \
+   CONFIG.PCW_EN_CLK3_PORT {1} \
+   CONFIG.PCW_EN_EMIO_ENET0 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {1} \
+   CONFIG.PCW_EN_EMIO_I2C1 {0} \
+   CONFIG.PCW_EN_EMIO_PJTAG {0} \
+   CONFIG.PCW_EN_EMIO_SPI0 {1} \
+   CONFIG.PCW_EN_EMIO_SPI1 {1} \
+   CONFIG.PCW_EN_EMIO_UART0 {0} \
+   CONFIG.PCW_EN_ENET0 {1} \
+   CONFIG.PCW_EN_GPIO {1} \
+   CONFIG.PCW_EN_I2C0 {1} \
+   CONFIG.PCW_EN_I2C1 {0} \
+   CONFIG.PCW_EN_PJTAG {0} \
+   CONFIG.PCW_EN_RST1_PORT {0} \
+   CONFIG.PCW_EN_RST2_PORT {0} \
+   CONFIG.PCW_EN_RST3_PORT {0} \
+   CONFIG.PCW_EN_SDIO0 {1} \
+   CONFIG.PCW_EN_SPI0 {1} \
+   CONFIG.PCW_EN_SPI1 {1} \
+   CONFIG.PCW_EN_UART0 {1} \
+   CONFIG.PCW_EN_UART1 {1} \
+   CONFIG.PCW_EN_USB0 {1} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {3} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
+   CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \
+   CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \
+   CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \
+   CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
+   CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+   CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47} \
+   CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C0_RESET_IO {<Select>} \
+   CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
+   CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_I2C_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+   CONFIG.PCW_IRQ_F2P_INTR {1} \
+   CONFIG.PCW_MIO_0_DIRECTION {inout} \
+   CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_0_PULLUP {enabled} \
+   CONFIG.PCW_MIO_0_SLEW {slow} \
+   CONFIG.PCW_MIO_10_DIRECTION {inout} \
+   CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_10_PULLUP {enabled} \
+   CONFIG.PCW_MIO_10_SLEW {slow} \
+   CONFIG.PCW_MIO_11_DIRECTION {out} \
+   CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_11_PULLUP {enabled} \
+   CONFIG.PCW_MIO_11_SLEW {slow} \
+   CONFIG.PCW_MIO_12_DIRECTION {inout} \
+   CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_12_PULLUP {enabled} \
+   CONFIG.PCW_MIO_12_SLEW {slow} \
+   CONFIG.PCW_MIO_13_DIRECTION {inout} \
+   CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_13_PULLUP {enabled} \
+   CONFIG.PCW_MIO_13_SLEW {slow} \
+   CONFIG.PCW_MIO_14_DIRECTION {in} \
+   CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_14_PULLUP {enabled} \
+   CONFIG.PCW_MIO_14_SLEW {slow} \
+   CONFIG.PCW_MIO_15_DIRECTION {out} \
+   CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_15_PULLUP {enabled} \
+   CONFIG.PCW_MIO_15_SLEW {slow} \
+   CONFIG.PCW_MIO_16_DIRECTION {out} \
+   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_16_PULLUP {disabled} \
+   CONFIG.PCW_MIO_16_SLEW {fast} \
+   CONFIG.PCW_MIO_17_DIRECTION {out} \
+   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_17_PULLUP {disabled} \
+   CONFIG.PCW_MIO_17_SLEW {fast} \
+   CONFIG.PCW_MIO_18_DIRECTION {out} \
+   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_18_PULLUP {disabled} \
+   CONFIG.PCW_MIO_18_SLEW {fast} \
+   CONFIG.PCW_MIO_19_DIRECTION {out} \
+   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_19_PULLUP {disabled} \
+   CONFIG.PCW_MIO_19_SLEW {fast} \
+   CONFIG.PCW_MIO_1_DIRECTION {inout} \
+   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_1_PULLUP {enabled} \
+   CONFIG.PCW_MIO_1_SLEW {slow} \
+   CONFIG.PCW_MIO_20_DIRECTION {out} \
+   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_20_PULLUP {disabled} \
+   CONFIG.PCW_MIO_20_SLEW {fast} \
+   CONFIG.PCW_MIO_21_DIRECTION {out} \
+   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_21_PULLUP {disabled} \
+   CONFIG.PCW_MIO_21_SLEW {fast} \
+   CONFIG.PCW_MIO_22_DIRECTION {in} \
+   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_22_PULLUP {disabled} \
+   CONFIG.PCW_MIO_22_SLEW {fast} \
+   CONFIG.PCW_MIO_23_DIRECTION {in} \
+   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_23_PULLUP {disabled} \
+   CONFIG.PCW_MIO_23_SLEW {fast} \
+   CONFIG.PCW_MIO_24_DIRECTION {in} \
+   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_24_PULLUP {disabled} \
+   CONFIG.PCW_MIO_24_SLEW {fast} \
+   CONFIG.PCW_MIO_25_DIRECTION {in} \
+   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_25_PULLUP {disabled} \
+   CONFIG.PCW_MIO_25_SLEW {fast} \
+   CONFIG.PCW_MIO_26_DIRECTION {in} \
+   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_26_PULLUP {disabled} \
+   CONFIG.PCW_MIO_26_SLEW {fast} \
+   CONFIG.PCW_MIO_27_DIRECTION {in} \
+   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_27_PULLUP {disabled} \
+   CONFIG.PCW_MIO_27_SLEW {fast} \
+   CONFIG.PCW_MIO_28_DIRECTION {inout} \
+   CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_28_PULLUP {enabled} \
+   CONFIG.PCW_MIO_28_SLEW {slow} \
+   CONFIG.PCW_MIO_29_DIRECTION {in} \
+   CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_29_PULLUP {enabled} \
+   CONFIG.PCW_MIO_29_SLEW {slow} \
+   CONFIG.PCW_MIO_2_DIRECTION {inout} \
+   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_2_PULLUP {disabled} \
+   CONFIG.PCW_MIO_2_SLEW {slow} \
+   CONFIG.PCW_MIO_30_DIRECTION {out} \
+   CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_30_PULLUP {enabled} \
+   CONFIG.PCW_MIO_30_SLEW {slow} \
+   CONFIG.PCW_MIO_31_DIRECTION {in} \
+   CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_31_PULLUP {enabled} \
+   CONFIG.PCW_MIO_31_SLEW {slow} \
+   CONFIG.PCW_MIO_32_DIRECTION {inout} \
+   CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_32_PULLUP {enabled} \
+   CONFIG.PCW_MIO_32_SLEW {slow} \
+   CONFIG.PCW_MIO_33_DIRECTION {inout} \
+   CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_33_PULLUP {enabled} \
+   CONFIG.PCW_MIO_33_SLEW {slow} \
+   CONFIG.PCW_MIO_34_DIRECTION {inout} \
+   CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_34_PULLUP {enabled} \
+   CONFIG.PCW_MIO_34_SLEW {slow} \
+   CONFIG.PCW_MIO_35_DIRECTION {inout} \
+   CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_35_PULLUP {enabled} \
+   CONFIG.PCW_MIO_35_SLEW {slow} \
+   CONFIG.PCW_MIO_36_DIRECTION {in} \
+   CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_36_PULLUP {enabled} \
+   CONFIG.PCW_MIO_36_SLEW {slow} \
+   CONFIG.PCW_MIO_37_DIRECTION {inout} \
+   CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_37_PULLUP {enabled} \
+   CONFIG.PCW_MIO_37_SLEW {slow} \
+   CONFIG.PCW_MIO_38_DIRECTION {inout} \
+   CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_38_PULLUP {enabled} \
+   CONFIG.PCW_MIO_38_SLEW {slow} \
+   CONFIG.PCW_MIO_39_DIRECTION {inout} \
+   CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_39_PULLUP {enabled} \
+   CONFIG.PCW_MIO_39_SLEW {slow} \
+   CONFIG.PCW_MIO_3_DIRECTION {inout} \
+   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_3_PULLUP {disabled} \
+   CONFIG.PCW_MIO_3_SLEW {slow} \
+   CONFIG.PCW_MIO_40_DIRECTION {inout} \
+   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_40_PULLUP {enabled} \
+   CONFIG.PCW_MIO_40_SLEW {slow} \
+   CONFIG.PCW_MIO_41_DIRECTION {inout} \
+   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_41_PULLUP {enabled} \
+   CONFIG.PCW_MIO_41_SLEW {slow} \
+   CONFIG.PCW_MIO_42_DIRECTION {inout} \
+   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_42_PULLUP {enabled} \
+   CONFIG.PCW_MIO_42_SLEW {slow} \
+   CONFIG.PCW_MIO_43_DIRECTION {inout} \
+   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_43_PULLUP {enabled} \
+   CONFIG.PCW_MIO_43_SLEW {slow} \
+   CONFIG.PCW_MIO_44_DIRECTION {inout} \
+   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_44_PULLUP {enabled} \
+   CONFIG.PCW_MIO_44_SLEW {slow} \
+   CONFIG.PCW_MIO_45_DIRECTION {inout} \
+   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_45_PULLUP {enabled} \
+   CONFIG.PCW_MIO_45_SLEW {slow} \
+   CONFIG.PCW_MIO_46_DIRECTION {inout} \
+   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_46_PULLUP {enabled} \
+   CONFIG.PCW_MIO_46_SLEW {slow} \
+   CONFIG.PCW_MIO_47_DIRECTION {inout} \
+   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_47_PULLUP {enabled} \
+   CONFIG.PCW_MIO_47_SLEW {slow} \
+   CONFIG.PCW_MIO_48_DIRECTION {out} \
+   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_48_PULLUP {enabled} \
+   CONFIG.PCW_MIO_48_SLEW {slow} \
+   CONFIG.PCW_MIO_49_DIRECTION {in} \
+   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_49_PULLUP {enabled} \
+   CONFIG.PCW_MIO_49_SLEW {slow} \
+   CONFIG.PCW_MIO_4_DIRECTION {inout} \
+   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_4_PULLUP {disabled} \
+   CONFIG.PCW_MIO_4_SLEW {slow} \
+   CONFIG.PCW_MIO_50_DIRECTION {inout} \
+   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_50_PULLUP {enabled} \
+   CONFIG.PCW_MIO_50_SLEW {slow} \
+   CONFIG.PCW_MIO_51_DIRECTION {inout} \
+   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_51_PULLUP {enabled} \
+   CONFIG.PCW_MIO_51_SLEW {slow} \
+   CONFIG.PCW_MIO_52_DIRECTION {out} \
+   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_52_PULLUP {enabled} \
+   CONFIG.PCW_MIO_52_SLEW {slow} \
+   CONFIG.PCW_MIO_53_DIRECTION {inout} \
+   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_53_PULLUP {enabled} \
+   CONFIG.PCW_MIO_53_SLEW {slow} \
+   CONFIG.PCW_MIO_5_DIRECTION {inout} \
+   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_5_PULLUP {disabled} \
+   CONFIG.PCW_MIO_5_SLEW {slow} \
+   CONFIG.PCW_MIO_6_DIRECTION {inout} \
+   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_6_PULLUP {disabled} \
+   CONFIG.PCW_MIO_6_SLEW {slow} \
+   CONFIG.PCW_MIO_7_DIRECTION {out} \
+   CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_7_PULLUP {disabled} \
+   CONFIG.PCW_MIO_7_SLEW {slow} \
+   CONFIG.PCW_MIO_8_DIRECTION {out} \
+   CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_8_PULLUP {disabled} \
+   CONFIG.PCW_MIO_8_SLEW {slow} \
+   CONFIG.PCW_MIO_9_DIRECTION {out} \
+   CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_9_PULLUP {enabled} \
+   CONFIG.PCW_MIO_9_SLEW {slow} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#USB Reset#GPIO#ENET Reset#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#reset#gpio[10]#reset#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
+   CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \
+   CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \
+   CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \
+   CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SPI0_SPI0_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
+   CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {6} \
+   CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+   CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
+   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \
+   CONFIG.PCW_UIPARAM_DDR_CL {7} \
+   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \
+   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
+   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
+   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+   CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB0_RESET_ENABLE {1} \
+   CONFIG.PCW_USB0_RESET_IO {MIO 9} \
+   CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+   CONFIG.PCW_USB1_RESET_ENABLE {0} \
+   CONFIG.PCW_USB_RESET_ENABLE {1} \
+   CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
+   CONFIG.PCW_USE_HIGH_OCM {1} \
+   CONFIG.PCW_USE_PS_SLCR_REGISTERS {1} \
+   CONFIG.PCW_USE_S_AXI_GP0 {0} \
+   CONFIG.PCW_USE_S_AXI_GP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {0} \
+   CONFIG.PCW_USE_S_AXI_HP1 {1} \
+   CONFIG.PCW_USE_S_AXI_HP2 {1} \
+   CONFIG.PCW_USE_S_AXI_HP3 {0} \
+ ] $processing_system7_0
+
+  # Create instance: xlconcat_0, and set properties
+  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+  set_property -dict [ list \
+   CONFIG.IN0_WIDTH {8} \
+   CONFIG.NUM_PORTS {9} \
+ ] $xlconcat_0
+
+  # Create instance: xlslice_2, and set properties
+  set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {7} \
+   CONFIG.DIN_TO {0} \
+   CONFIG.DIN_WIDTH {16} \
+   CONFIG.DOUT_WIDTH {8} \
+ ] $xlslice_2
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
+  connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_xbar] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
+  connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac]
+  connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_pmu] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
+  connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
+  connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2]
+  connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma]
+  connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma]
+  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+  connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
+  connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0]
+  connect_bd_intf_net -intf_net s_axi_regfile_1 [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins dma/s_axi_regfile]
+  connect_bd_intf_net -intf_net s_axi_rx_dmac_1 [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac]
+
+  # Create port connections
+  connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din]
+  connect_bd_net -net SPI0_MISO_I_1 [get_bd_ports SPI0_MISO_I] [get_bd_pins processing_system7_0/SPI0_MISO_I]
+  connect_bd_net -net SPI0_MOSI_I_1 [get_bd_ports SPI0_MOSI_I] [get_bd_pins processing_system7_0/SPI0_MOSI_I]
+  connect_bd_net -net SPI0_SCLK_I_1 [get_bd_ports SPI0_SCLK_I] [get_bd_pins processing_system7_0/SPI0_SCLK_I]
+  connect_bd_net -net SPI0_SS_I_1 [get_bd_ports SPI0_SS_I] [get_bd_pins processing_system7_0/SPI0_SS_I]
+  connect_bd_net -net SPI1_MISO_I_0_1 [get_bd_ports SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MISO_I]
+  connect_bd_net -net SPI1_MOSI_I_0_1 [get_bd_ports SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I]
+  connect_bd_net -net SPI1_SCLK_I_0_1 [get_bd_ports SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I]
+  connect_bd_net -net SPI1_SS_I_0_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
+  connect_bd_net -net S_AXI_GP0_ACLK_1 [get_bd_ports S_AXI_GP0_ACLK] [get_bd_pins axi_interconnect_0/ACLK]
+  connect_bd_net -net S_AXI_GP0_ARESETN_1 [get_bd_ports S_AXI_GP0_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN]
+  connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk]
+  connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn]
+  connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK]
+  connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn]
+  connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN]
+  connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP]
+  connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2]
+  connect_bd_net -net mio [get_bd_ports MIO] [get_bd_pins processing_system7_0/MIO]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0]
+  connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1]
+  connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7_0/FCLK_CLK2]
+  connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_ports FCLK_CLK3] [get_bd_pins processing_system7_0/FCLK_CLK3]
+  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
+  connect_bd_net -net processing_system7_0_SPI0_MISO_O [get_bd_ports SPI0_MISO_O] [get_bd_pins processing_system7_0/SPI0_MISO_O]
+  connect_bd_net -net processing_system7_0_SPI0_MISO_T [get_bd_ports SPI0_MISO_T] [get_bd_pins processing_system7_0/SPI0_MISO_T]
+  connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_O] [get_bd_pins processing_system7_0/SPI0_MOSI_O]
+  connect_bd_net -net processing_system7_0_SPI0_MOSI_T [get_bd_ports SPI0_MOSI_T] [get_bd_pins processing_system7_0/SPI0_MOSI_T]
+  connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_O] [get_bd_pins processing_system7_0/SPI0_SCLK_O]
+  connect_bd_net -net processing_system7_0_SPI0_SCLK_T [get_bd_ports SPI0_SCLK_T] [get_bd_pins processing_system7_0/SPI0_SCLK_T]
+  connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_SS1_O] [get_bd_pins processing_system7_0/SPI0_SS1_O]
+  connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_ports SPI0_SS2_O] [get_bd_pins processing_system7_0/SPI0_SS2_O]
+  connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_SS_O] [get_bd_pins processing_system7_0/SPI0_SS_O]
+  connect_bd_net -net processing_system7_0_SPI0_SS_T [get_bd_ports SPI0_SS_T] [get_bd_pins processing_system7_0/SPI0_SS_T]
+  connect_bd_net -net processing_system7_0_SPI1_MISO_O [get_bd_ports SPI1_MISO_O] [get_bd_pins processing_system7_0/SPI1_MISO_O]
+  connect_bd_net -net processing_system7_0_SPI1_MISO_T [get_bd_ports SPI1_MISO_T] [get_bd_pins processing_system7_0/SPI1_MISO_T]
+  connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI1_MOSI_O] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
+  connect_bd_net -net processing_system7_0_SPI1_MOSI_T [get_bd_ports SPI1_MOSI_T] [get_bd_pins processing_system7_0/SPI1_MOSI_T]
+  connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI1_SCLK_O] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
+  connect_bd_net -net processing_system7_0_SPI1_SCLK_T [get_bd_ports SPI1_SCLK_T] [get_bd_pins processing_system7_0/SPI1_SCLK_T]
+  connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI1_SS1_O] [get_bd_pins processing_system7_0/SPI1_SS1_O]
+  connect_bd_net -net processing_system7_0_SPI1_SS2_O [get_bd_ports SPI1_SS2_O] [get_bd_pins processing_system7_0/SPI1_SS2_O]
+  connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI1_SS_O] [get_bd_pins processing_system7_0/SPI1_SS_O]
+  connect_bd_net -net processing_system7_0_SPI1_SS_T [get_bd_ports SPI1_SS_T] [get_bd_pins processing_system7_0/SPI1_SS_T]
+  connect_bd_net -net ps_clk [get_bd_ports PS_CLK] [get_bd_pins processing_system7_0/PS_CLK]
+  connect_bd_net -net ps_porb [get_bd_ports PS_PORB] [get_bd_pins processing_system7_0/PS_PORB]
+  connect_bd_net -net ps_srstb [get_bd_ports PS_SRSTB] [get_bd_pins processing_system7_0/PS_SRSTB]
+  connect_bd_net -net rx_dma_irq [get_bd_pins dma/rx_irq] [get_bd_pins xlconcat_0/In1]
+  connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout]
+  connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg
+  create_bd_addr_seg -range 0x00001000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs
+  create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite
+  create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite1
+  create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite2
+  create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite3
+  create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite4
+  create_bd_addr_seg -range 0x00010000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_tx_dmac_0_axi_lite
+  create_bd_addr_seg -range 0x00010000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_tx_dmac_1_axi_lite
+  create_bd_addr_seg -range 0x00010000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_tx_dmac_2_axi_lite
+  create_bd_addr_seg -range 0x00010000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_tx_dmac_3_axi_lite
+  create_bd_addr_seg -range 0x00010000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_tx_dmac_4_axi_lite
+  create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_pmu/Reg] SEG_m_axi_pmu_Reg
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init.c b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init.c
new file mode 100644
index 000000000..1ad91d83a
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init.c
@@ -0,0 +1,13335 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
+* otherwise to promote the sale, use or other dealings in this Software without prior written
+* authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include "ps7_init.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000154[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000158[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000158[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000158[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xc
+    // .. ==> 0XF8000158[13:8] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000C00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x5
+    // .. .. ==> 0XF8000180[25:20] = 0x00000005U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x4
+    // .. .. ==> 0XF8000190[13:8] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000400U
+    // .. .. DIVISOR1 = 0x3
+    // .. .. ==> 0XF8000190[25:20] = 0x00000003U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x2
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000002U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF800612C[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7a
+    // .. .. ==> 0XF800612C[19:10] = 0x0000007AU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006130[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006130[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006134[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006134[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1
+    // .. .. ==> 0XF8006138[9:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000001U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x78
+    // .. .. ==> 0XF8006138[19:10] = 0x00000078U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006154[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF8006158[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF800615C[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x81
+    // .. .. ==> 0XF8006160[9:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000081U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcf
+    // .. .. ==> 0XF8006168[10:0] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CFU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF800616C[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF8006170[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcd
+    // .. .. ==> 0XF8006174[10:0] = 0x000000CDU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CDU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000704[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000708[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800070C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000710[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000714[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000718[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000720[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000724[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000724[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000728[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000728[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF800072C[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000730[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000730[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000734[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000734[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF8000738[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF800073C[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007B8[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007BC[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C0[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C4[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 56
+    // .. ==> 0XF8000830[21:16] = 0x00000038U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. BDIV = 0x6
+    // .. ==> 0XE0000034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0000018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0000000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0000000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0000000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0000000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0000000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0000000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0000000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0000000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0000000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0000004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0000004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0000004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0000004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0000004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000154[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000158[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000158[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000158[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xc
+    // .. ==> 0XF8000158[13:8] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000C00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x5
+    // .. .. ==> 0XF8000180[25:20] = 0x00000005U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x4
+    // .. .. ==> 0XF8000190[13:8] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000400U
+    // .. .. DIVISOR1 = 0x3
+    // .. .. ==> 0XF8000190[25:20] = 0x00000003U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x2
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000002U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF800612C[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7a
+    // .. .. ==> 0XF800612C[19:10] = 0x0000007AU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006130[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006130[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006134[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006134[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1
+    // .. .. ==> 0XF8006138[9:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000001U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x78
+    // .. .. ==> 0XF8006138[19:10] = 0x00000078U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006154[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF8006158[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF800615C[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x81
+    // .. .. ==> 0XF8006160[9:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000081U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcf
+    // .. .. ==> 0XF8006168[10:0] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CFU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF800616C[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF8006170[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcd
+    // .. .. ==> 0XF8006174[10:0] = 0x000000CDU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CDU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000704[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000708[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800070C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000710[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000714[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000718[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000720[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000724[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000724[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000728[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000728[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF800072C[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000730[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000730[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000734[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000734[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF8000738[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF800073C[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007B8[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007BC[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C0[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C4[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 56
+    // .. ==> 0XF8000830[21:16] = 0x00000038U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. BDIV = 0x6
+    // .. ==> 0XE0000034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0000018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0000000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0000000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0000000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0000000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0000000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0000000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0000000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0000000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0000000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0000004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0000004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0000004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0000004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0000004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0000004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0000004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000154[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000158[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000158[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000158[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xc
+    // .. ==> 0XF8000158[13:8] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000C00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x5
+    // .. .. ==> 0XF8000180[25:20] = 0x00000005U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x4
+    // .. .. ==> 0XF8000190[13:8] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000400U
+    // .. .. DIVISOR1 = 0x3
+    // .. .. ==> 0XF8000190[25:20] = 0x00000003U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x2
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000002U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF800612C[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7a
+    // .. .. ==> 0XF800612C[19:10] = 0x0000007AU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006130[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006130[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006134[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006134[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1
+    // .. .. ==> 0XF8006138[9:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000001U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x78
+    // .. .. ==> 0XF8006138[19:10] = 0x00000078U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006154[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF8006158[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF800615C[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x81
+    // .. .. ==> 0XF8006160[9:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000081U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcf
+    // .. .. ==> 0XF8006168[10:0] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CFU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF800616C[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF8006170[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcd
+    // .. .. ==> 0XF8006174[10:0] = 0x000000CDU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CDU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000704[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000708[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800070C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000710[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000714[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000718[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000720[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000724[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000724[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000728[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000728[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF800072C[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000730[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000730[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000734[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000734[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF8000738[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF800073C[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007B8[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007BC[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C0[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C4[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 56
+    // .. ==> 0XF8000830[21:16] = 0x00000038U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. BDIV = 0x6
+    // .. ==> 0XE0000034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0000018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0000000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0000000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0000000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0000000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0000000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0000000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0000000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0000000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0000000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0000004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0000004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0000004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0000004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0000004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0000004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0000004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+  
+  return err_msg;  
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;    
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;   
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init) 
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+    
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ ) 
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+        
+        
+        switch ( opcode ) {
+            
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+            
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer(); 
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+  
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);  
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data); 
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	); 
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay) 
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+   
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer() 
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg1.c b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg1.c
new file mode 100644
index 000000000..89d3d6f04
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg1.c
@@ -0,0 +1,1087 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+*
+*  You should have received a copy of the GNU General Public License along
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U),
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500500U),
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00200300U),
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U),
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_debug_3_0[] = {
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U),
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500500U),
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00200300U),
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U),
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_debug_2_0[] = {
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U),
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500500U),
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00200300U),
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U),
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_debug_1_0[] = {
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    EMIT_EXIT(),
+
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+
+  return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+    unsigned long *ptr = ps7_config_init;
+
+
+
+
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ )
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+
+
+        switch ( opcode ) {
+
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer();
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init()
+{
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+  }
+
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	);
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+  return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg3.c b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg3.c
new file mode 100644
index 000000000..8a8a9f04b
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg3.c
@@ -0,0 +1,1087 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+*
+*  You should have received a copy of the GNU General Public License along
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00034000U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_debug_3_0[] = {
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00034000U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_debug_2_0[] = {
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00034000U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U),
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U),
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    EMIT_EXIT(),
+
+};
+
+unsigned long ps7_debug_1_0[] = {
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    EMIT_EXIT(),
+
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+
+  return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+    unsigned long *ptr = ps7_config_init;
+
+
+
+
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ )
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+
+
+        switch ( opcode ) {
+
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer();
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init()
+{
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+  }
+
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	);
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+  return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl.c b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl.c
new file mode 100644
index 000000000..dd9994e98
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl.c
@@ -0,0 +1,13326 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see <http://www.gnu.org/licenses/>
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000154[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000158[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000158[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000158[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xc
+    // .. ==> 0XF8000158[13:8] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000C00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x5
+    // .. .. ==> 0XF8000180[25:20] = 0x00000005U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x4
+    // .. .. ==> 0XF8000190[13:8] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000400U
+    // .. .. DIVISOR1 = 0x3
+    // .. .. ==> 0XF8000190[25:20] = 0x00000003U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x2
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000002U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF800612C[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7a
+    // .. .. ==> 0XF800612C[19:10] = 0x0000007AU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006130[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006130[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006134[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006134[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1
+    // .. .. ==> 0XF8006138[9:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000001U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x78
+    // .. .. ==> 0XF8006138[19:10] = 0x00000078U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006154[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF8006158[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF800615C[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x81
+    // .. .. ==> 0XF8006160[9:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000081U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcf
+    // .. .. ==> 0XF8006168[10:0] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CFU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF800616C[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF8006170[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcd
+    // .. .. ==> 0XF8006174[10:0] = 0x000000CDU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CDU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000704[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000708[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800070C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000710[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000714[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000718[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000720[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000724[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000724[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000728[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000728[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF800072C[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000730[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000730[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000734[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000734[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF8000738[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF800073C[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007B8[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007BC[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C0[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C4[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 56
+    // .. ==> 0XF8000830[21:16] = 0x00000038U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. BDIV = 0x6
+    // .. ==> 0XE0000034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0000018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0000000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0000000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0000000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0000000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0000000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0000000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0000000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0000000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0000000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0000004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0000004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0000004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0000004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0000004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000154[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000158[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000158[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000158[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xc
+    // .. ==> 0XF8000158[13:8] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000C00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x5
+    // .. .. ==> 0XF8000180[25:20] = 0x00000005U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x4
+    // .. .. ==> 0XF8000190[13:8] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000400U
+    // .. .. DIVISOR1 = 0x3
+    // .. .. ==> 0XF8000190[25:20] = 0x00000003U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x2
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000002U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF800612C[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7a
+    // .. .. ==> 0XF800612C[19:10] = 0x0000007AU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006130[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006130[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006134[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006134[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1
+    // .. .. ==> 0XF8006138[9:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000001U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x78
+    // .. .. ==> 0XF8006138[19:10] = 0x00000078U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006154[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF8006158[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF800615C[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x81
+    // .. .. ==> 0XF8006160[9:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000081U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcf
+    // .. .. ==> 0XF8006168[10:0] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CFU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF800616C[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF8006170[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcd
+    // .. .. ==> 0XF8006174[10:0] = 0x000000CDU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CDU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000704[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000708[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800070C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000710[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000714[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000718[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000720[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000724[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000724[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000728[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000728[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF800072C[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000730[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000730[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000734[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000734[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF8000738[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF800073C[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007B8[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007BC[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C0[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C4[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 56
+    // .. ==> 0XF8000830[21:16] = 0x00000038U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. BDIV = 0x6
+    // .. ==> 0XE0000034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0000018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0000000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0000000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0000000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0000000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0000000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0000000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0000000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0000000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0000000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0000004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0000004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0000004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0000004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0000004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0000004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0000004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000154[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000158[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000158[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000158[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xc
+    // .. ==> 0XF8000158[13:8] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000C00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x5
+    // .. .. ==> 0XF8000180[25:20] = 0x00000005U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x4
+    // .. .. ==> 0XF8000190[13:8] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000400U
+    // .. .. DIVISOR1 = 0x3
+    // .. .. ==> 0XF8000190[25:20] = 0x00000003U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x2
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000002U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF800612C[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7a
+    // .. .. ==> 0XF800612C[19:10] = 0x0000007AU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006130[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006130[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x5
+    // .. .. ==> 0XF8006134[9:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000005U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x7b
+    // .. .. ==> 0XF8006134[19:10] = 0x0000007BU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001EC00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1
+    // .. .. ==> 0XF8006138[9:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000001U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x78
+    // .. .. ==> 0XF8006138[19:10] = 0x00000078U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0001E000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006154[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF8006158[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x85
+    // .. .. ==> 0XF800615C[9:0] = 0x00000085U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000085U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x81
+    // .. .. ==> 0XF8006160[9:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000081U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcf
+    // .. .. ==> 0XF8006168[10:0] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CFU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF800616C[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xd0
+    // .. .. ==> 0XF8006170[10:0] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000D0U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xcd
+    // .. .. ==> 0XF8006174[10:0] = 0x000000CDU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000CDU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc5
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000704[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000708[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800070C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000710[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000714[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000718[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000720[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000724[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF8000724[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000728[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000728[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF800072C[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000730[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000730[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000734[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 3
+    // .. ==> 0XF8000734[7:5] = 0x00000003U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000060U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF8000738[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF800073C[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007B8[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007BC[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C0[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C4[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 56
+    // .. ==> 0XF8000830[21:16] = 0x00000038U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. BDIV = 0x6
+    // .. ==> 0XE0000034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0000018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0000000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0000000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0000000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0000000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0000000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0000000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0000000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0000000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0000000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0000004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0000004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0000004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0000004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0000004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0000004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0000004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xffef
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFEF0000U
+    // .. .. .. .. DATA_0_LSW = 0x10
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000010U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x18
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x18
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000018U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xfff7
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFF70000U
+    // .. .. .. .. DATA_0_LSW = 0x8
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+  
+  return err_msg;  
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;    
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;   
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init) 
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+    
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ ) 
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+        
+        
+        switch ( opcode ) {
+            
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+            
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer(); 
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+  
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);  
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data); 
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	); 
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay) 
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+   
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer() 
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/Makefile.inc
new file mode 100644
index 000000000..e022d9a1c
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2014 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
+
+IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \
+fifo_4k_2clk.xci.out \
+synth/fifo_4k_2clk.vhd \
+) 
+
+$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
+	$(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/fifo_4k_2clk.xci
new file mode 100644
index 000000000..45633b29c
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/fifo_4k_2clk.xci
@@ -0,0 +1,575 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>fifo_4k_2clk</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_4k_2clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">511</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/top/e31x/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/e31x/ip/fifo_short_2clk/Makefile.inc
new file mode 100644
index 000000000..8c5c54213
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/fifo_short_2clk/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# Copyright 2014 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci
+
+IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \
+fifo_short_2clk.xci.out \
+synth/fifo_short_2clk.vhd \
+) 
+
+$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci
+	$(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
diff --git a/fpga/usrp3/top/e31x/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/e31x/ip/fifo_short_2clk/fifo_short_2clk.xci
new file mode 100644
index 000000000..a07af7845
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/fifo_short_2clk/fifo_short_2clk.xci
@@ -0,0 +1,577 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>fifo_short_2clk</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_short_2clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">30</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc b/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc
new file mode 100644
index 000000000..0be73f919
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc
@@ -0,0 +1,32 @@
+#
+# Copyright 2015 Ettus Research
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+IP_MIG_7SERIES_0_SRCS = $(IP_BUILD_DIR)/mig_7series_0/mig_7series_0.xci
+
+IP_MIG_7SERIES_0_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
+mig_7series_0.xci.out \
+mig_7series_0/user_design/rtl/mig_7series_0.v \
+mig_7series_0/user_design/rtl/mig_7series_0_mig.v \
+)
+
+IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
+mig_7series_0/example_design/rtl/example_top.v \
+mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \
+mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \
+mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v  \
+mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \
+mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \
+)
+
+IP_MIG_7SERIES_0_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
+mig_7series_0/example_design/sim/ddr3_model.sv \
+mig_7series_0/example_design/sim/ddr3_model_parameters.vh \
+)
+
+$(IP_MIG_7SERIES_0_SRCS) $(IP_MIG_7SERIES_0_OUTS) : $(IP_DIR)/mig_7series_0/mig_7series_0.xci $(IP_DIR)/mig_7series_0/mig_*.prj
+	ln -fs mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/mig_7series_0/mig_a.prj	# Hack: This won't allow parallel IP builds
+	$(call BUILD_VIVADO_IP,mig_7series_0,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
+	rm -f $(IP_DIR)/mig_7series_0/mig_a.prj
diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_7series_0.xci b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_7series_0.xci
new file mode 100644
index 000000000..5b99fe23c
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_7series_0.xci
@@ -0,0 +1,2648 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>mig_7series_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="mig_7series" spirit:version="4.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_CLOCK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_CLOCK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT0.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT1.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT2.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT3.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_CLOCK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CUSTOM_PARTS"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_CLOCK.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_CLOCK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_CLOCK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_CLOCK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ID_WIDTH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_VCO">1200.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_USE_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_ECC">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_FREQ_HZ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MEM_TYPE">DDR3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_VCO">1200.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_USE_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_ECC">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_FREQ_HZ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MEM_TYPE">DDR3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_VCO">1200.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_USE_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_ECC">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_FREQ_HZ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MEM_TYPE">DDR3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_VCO">1200.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_USE_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_ECC">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_FREQ_HZ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MEM_TYPE">DDR3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_VCO">1200.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_USE_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_ECC">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_FREQ_HZ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MEM_TYPE">DDR3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_VCO">1200.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_USE_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_ECC">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_FREQ_HZ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MEM_TYPE">DDR3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_VCO">1200.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_USE_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_ECC">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_FREQ_HZ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MEM_TYPE">DDR3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_VCO">1200.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_USE_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMBINED_INTERFACE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_MEM_SIZE">536870912</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_ROW_WIDTH">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_USE_CS_PORT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_nCK_PER_CLK">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ECC">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_TYPE">DDR3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_VCO">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NoOfControllers">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.POLARITY">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REFCLK_TYPE">NOBUF</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_DK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_QK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_DM_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYSCLK_TYPE">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TEMP_MON_CONTROL">INTERNAL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_AXI">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BOARD_MIG_PARAM">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">mig_7series_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XML_INPUT_FILE">mig_a.prj</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S0_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S1_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S3_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S4_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S5_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BOARD_MIG_PARAM" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.XML_INPUT_FILE" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj
new file mode 100644
index 000000000..f8c67329b
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj
@@ -0,0 +1,140 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+    <ModuleName>mig_7series_0</ModuleName>
+    <dci_inouts_inputs>1</dci_inouts_inputs>
+    <dci_inputs>1</dci_inputs>
+    <Debug_En>OFF</Debug_En>
+    <DataDepth_En>1024</DataDepth_En>
+    <LowPower_En>ON</LowPower_En>
+    <XADC_En>Enabled</XADC_En>
+    <TargetFPGA>xc7z020-clg484/-1</TargetFPGA>
+    <Version>4.0</Version>
+    <SystemClock>Single-Ended</SystemClock>
+    <ReferenceClock>No Buffer</ReferenceClock>
+    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+    <BankSelectionFlag>FALSE</BankSelectionFlag>
+    <InternalVref>1</InternalVref>
+    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+    <dci_cascade>0</dci_cascade>
+    <FPGADevice>
+        <selected>7z/xc7z020i-clg484</selected>
+    </FPGADevice>
+    <Controller number="0" >
+        <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>
+        <TimePeriod>2500</TimePeriod>
+        <VccAuxIO>1.8V</VccAuxIO>
+        <PHYRatio>4:1</PHYRatio>
+        <InputClkFreq>100</InputClkFreq>
+        <UIExtraClocks>0</UIExtraClocks>
+        <MMCM_VCO>800</MMCM_VCO>
+        <MMCMClkOut0> 1.000</MMCMClkOut0>
+        <MMCMClkOut1>1</MMCMClkOut1>
+        <MMCMClkOut2>1</MMCMClkOut2>
+        <MMCMClkOut3>1</MMCMClkOut3>
+        <MMCMClkOut4>1</MMCMClkOut4>
+        <DataWidth>16</DataWidth>
+        <DeepMemory>1</DeepMemory>
+        <DataMask>1</DataMask>
+        <ECC>Disabled</ECC>
+        <Ordering>Normal</Ordering>
+        <BankMachineCnt>4</BankMachineCnt>
+        <CustomPart>FALSE</CustomPart>
+        <NewPartName></NewPartName>
+        <RowAddress>15</RowAddress>
+        <ColAddress>10</ColAddress>
+        <BankAddress>3</BankAddress>
+        <MemoryVoltage>1.5V</MemoryVoltage>
+        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+        <PinSelection>
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V15" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W16" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W18" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W17" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB15" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V14" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB16" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA16" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA17" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V17" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U17" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U16" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U15" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y14" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W13" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V13" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y13" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y15" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W15" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB14" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V18" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA18" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T21" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA21" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB21" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB19" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB20" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y19" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA19" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U21" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T22" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U22" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W20" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W21" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U20" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V20" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA22" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB22" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W22" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y21" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V22" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y20" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U14" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA14" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="U19" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_we_n" IN_TERM="" />
+        </PinSelection>
+        <System_Clock>
+            <Pin PADName="Y18(MRCC_P)" Bank="33" name="sys_clk_i" />
+        </System_Clock>
+        <System_Control>
+            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+        </System_Control>
+        <TimingParameters>
+            <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />
+        </TimingParameters>
+        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+        <mrCasLatency name="CAS Latency" >6</mrCasLatency>
+        <mrMode name="Mode" >Normal</mrMode>
+        <mrDllReset name="DLL Reset" >No</mrDllReset>
+        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+        <emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection>
+        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+        <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+        <emrDQS name="TDQS enable" >Enabled</emrDQS>
+        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+        <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+        <PortInterface>AXI</PortInterface>
+        <AXIParameters>
+            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+            <C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH>
+            <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+            <C0_S_AXI_ID_WIDTH>12</C0_S_AXI_ID_WIDTH>
+            <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
+        </AXIParameters>
+    </Controller>
+
+</Project>
diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj
new file mode 100644
index 000000000..635ea1471
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj
@@ -0,0 +1,140 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+    <ModuleName>mig_7series_0</ModuleName>
+    <dci_inouts_inputs>1</dci_inouts_inputs>
+    <dci_inputs>1</dci_inputs>
+    <Debug_En>OFF</Debug_En>
+    <DataDepth_En>1024</DataDepth_En>
+    <LowPower_En>ON</LowPower_En>
+    <XADC_En>Enabled</XADC_En>
+    <TargetFPGA>xc7z020-clg484/-3</TargetFPGA>
+    <Version>4.0</Version>
+    <SystemClock>Single-Ended</SystemClock>
+    <ReferenceClock>No Buffer</ReferenceClock>
+    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+    <BankSelectionFlag>FALSE</BankSelectionFlag>
+    <InternalVref>1</InternalVref>
+    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+    <dci_cascade>0</dci_cascade>
+    <FPGADevice>
+        <selected>7z/xc7z020i-clg484</selected>
+    </FPGADevice>
+    <Controller number="0" >
+        <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>
+        <TimePeriod>2500</TimePeriod>
+        <VccAuxIO>1.8V</VccAuxIO>
+        <PHYRatio>4:1</PHYRatio>
+        <InputClkFreq>100</InputClkFreq>
+        <UIExtraClocks>0</UIExtraClocks>
+        <MMCM_VCO>800</MMCM_VCO>
+        <MMCMClkOut0> 1.000</MMCMClkOut0>
+        <MMCMClkOut1>1</MMCMClkOut1>
+        <MMCMClkOut2>1</MMCMClkOut2>
+        <MMCMClkOut3>1</MMCMClkOut3>
+        <MMCMClkOut4>1</MMCMClkOut4>
+        <DataWidth>16</DataWidth>
+        <DeepMemory>1</DeepMemory>
+        <DataMask>1</DataMask>
+        <ECC>Disabled</ECC>
+        <Ordering>Normal</Ordering>
+        <BankMachineCnt>4</BankMachineCnt>
+        <CustomPart>FALSE</CustomPart>
+        <NewPartName></NewPartName>
+        <RowAddress>15</RowAddress>
+        <ColAddress>10</ColAddress>
+        <BankAddress>3</BankAddress>
+        <MemoryVoltage>1.5V</MemoryVoltage>
+        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+        <PinSelection>
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V15" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W16" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W18" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W17" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB15" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V14" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB16" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA16" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA17" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V17" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U17" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U16" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U15" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y14" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W13" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V13" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y13" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y15" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W15" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB14" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V18" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA18" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T21" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA21" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB21" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB19" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB20" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y19" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA19" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U21" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T22" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U22" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W20" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W21" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U20" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V20" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA22" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB22" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W22" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y21" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V22" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y20" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U14" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA14" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="U19" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_we_n" IN_TERM="" />
+        </PinSelection>
+        <System_Clock>
+            <Pin PADName="Y18(MRCC_P)" Bank="33" name="sys_clk_i" />
+        </System_Clock>
+        <System_Control>
+            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+        </System_Control>
+        <TimingParameters>
+            <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />
+        </TimingParameters>
+        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+        <mrCasLatency name="CAS Latency" >6</mrCasLatency>
+        <mrMode name="Mode" >Normal</mrMode>
+        <mrDllReset name="DLL Reset" >No</mrDllReset>
+        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+        <emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection>
+        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+        <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+        <emrDQS name="TDQS enable" >Enabled</emrDQS>
+        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+        <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+        <PortInterface>AXI</PortInterface>
+        <AXIParameters>
+            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+            <C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH>
+            <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+            <C0_S_AXI_ID_WIDTH>12</C0_S_AXI_ID_WIDTH>
+            <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
+        </AXIParameters>
+    </Controller>
+
+</Project>