diff options
| author | Wade Fife <wade.fife@ettus.com> | 2022-01-29 20:47:36 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-02-10 18:13:44 -0700 |
| commit | 788fef11ef890c6dcee3be495fc381bcf2990d3b (patch) | |
| tree | 87e9c0da8b56e47e7f1a23aa0a6f8673dbe6d1e0 /fpga/usrp3/top/e31x/ip/ddr3_16bit | |
| parent | 8444f84add04f025b7e24855e0ba79446e615e01 (diff) | |
| download | uhd-788fef11ef890c6dcee3be495fc381bcf2990d3b.tar.gz uhd-788fef11ef890c6dcee3be495fc381bcf2990d3b.tar.bz2 uhd-788fef11ef890c6dcee3be495fc381bcf2990d3b.zip | |
fpga: e31x: Add DRAM support
This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:
DRAM=1 make E310_SG3
Diffstat (limited to 'fpga/usrp3/top/e31x/ip/ddr3_16bit')
| -rw-r--r-- | fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc | 32 | ||||
| -rw-r--r-- | fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci | 2649 | ||||
| -rw-r--r-- | fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj | 140 | ||||
| -rw-r--r-- | fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj | 140 |
4 files changed, 2961 insertions, 0 deletions
diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc b/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc new file mode 100644 index 000000000..66187c699 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_16BIT_SRCS = $(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit.xci + +IP_DDR3_16BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit.xci.out \ +ddr3_16bit/user_design/rtl/ddr3_16bit.v \ +ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \ +) + +IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit/example_design/rtl/example_top.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \ +) + +IP_DDR3_16BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit/example_design/sim/ddr3_model.sv \ +ddr3_16bit/example_design/sim/ddr3_model_parameters.vh \ +) + +$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS) : $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj + cp -f $(IP_DIR)/ddr3_16bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_16bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_16bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_16bit/mig_a.prj diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci b/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci new file mode 100644 index 000000000..7d467a859 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci @@ -0,0 +1,2649 @@ +<?xml version="1.0" encoding="UTF-8"?> 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xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S6_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BOARD_MIG_PARAM" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.XML_INPUT_FILE" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> + diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj new file mode 100644 index 000000000..74d75d1b7 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj @@ -0,0 +1,140 @@ +<?xml version='1.0' encoding='UTF-8'?> +<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. --> +<Project NoOfControllers="1" > + <ModuleName>ddr3_16bit</ModuleName> + <dci_inouts_inputs>1</dci_inouts_inputs> + <dci_inputs>1</dci_inputs> + <Debug_En>OFF</Debug_En> + <DataDepth_En>1024</DataDepth_En> + <LowPower_En>ON</LowPower_En> + <XADC_En>Enabled</XADC_En> + <TargetFPGA>xc7z020-clg484/-1</TargetFPGA> + <Version>4.0</Version> + <SystemClock>Single-Ended</SystemClock> + <ReferenceClock>No Buffer</ReferenceClock> + <SysResetPolarity>ACTIVE HIGH</SysResetPolarity> + <BankSelectionFlag>FALSE</BankSelectionFlag> + <InternalVref>1</InternalVref> + <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs> + <dci_cascade>0</dci_cascade> + <FPGADevice> + <selected>7z/xc7z020i-clg484</selected> + </FPGADevice> + <Controller number="0" > + <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice> + <TimePeriod>2500</TimePeriod> + <VccAuxIO>1.8V</VccAuxIO> + <PHYRatio>4:1</PHYRatio> + <InputClkFreq>100</InputClkFreq> + <UIExtraClocks>0</UIExtraClocks> + <MMCM_VCO>800</MMCM_VCO> + <MMCMClkOut0> 1.000</MMCMClkOut0> + <MMCMClkOut1>1</MMCMClkOut1> + <MMCMClkOut2>1</MMCMClkOut2> + <MMCMClkOut3>1</MMCMClkOut3> + <MMCMClkOut4>1</MMCMClkOut4> + <DataWidth>16</DataWidth> + <DeepMemory>1</DeepMemory> + <DataMask>1</DataMask> + <ECC>Disabled</ECC> + <Ordering>Normal</Ordering> + <BankMachineCnt>4</BankMachineCnt> + <CustomPart>FALSE</CustomPart> + <NewPartName></NewPartName> + <RowAddress>15</RowAddress> + <ColAddress>10</ColAddress> + <BankAddress>3</BankAddress> + <MemoryVoltage>1.5V</MemoryVoltage> + <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap> + <PinSelection> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V15" SLEW="" name="ddr3_addr[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_addr[10]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W16" SLEW="" name="ddr3_addr[11]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W18" SLEW="" name="ddr3_addr[12]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W17" SLEW="" name="ddr3_addr[13]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB15" SLEW="" name="ddr3_addr[14]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V14" SLEW="" name="ddr3_addr[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB16" SLEW="" name="ddr3_addr[2]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA16" SLEW="" name="ddr3_addr[3]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_addr[4]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA17" SLEW="" name="ddr3_addr[5]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V17" SLEW="" name="ddr3_addr[6]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U17" SLEW="" name="ddr3_addr[7]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U16" SLEW="" name="ddr3_addr[8]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U15" SLEW="" name="ddr3_addr[9]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y14" SLEW="" name="ddr3_ba[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W13" SLEW="" name="ddr3_ba[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V13" SLEW="" name="ddr3_ba[2]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y13" SLEW="" name="ddr3_cas_n" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y15" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W15" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB14" SLEW="" name="ddr3_cke[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V18" SLEW="" name="ddr3_dm[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA18" SLEW="" name="ddr3_dm[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T21" SLEW="" name="ddr3_dq[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA21" SLEW="" name="ddr3_dq[10]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB21" SLEW="" name="ddr3_dq[11]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB19" SLEW="" name="ddr3_dq[12]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB20" SLEW="" name="ddr3_dq[13]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y19" SLEW="" name="ddr3_dq[14]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA19" SLEW="" name="ddr3_dq[15]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U21" SLEW="" name="ddr3_dq[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T22" SLEW="" name="ddr3_dq[2]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U22" SLEW="" name="ddr3_dq[3]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W20" SLEW="" name="ddr3_dq[4]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W21" SLEW="" name="ddr3_dq[5]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U20" SLEW="" name="ddr3_dq[6]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V20" SLEW="" name="ddr3_dq[7]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA22" SLEW="" name="ddr3_dq[8]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB22" SLEW="" name="ddr3_dq[9]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W22" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y21" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V22" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y20" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U14" SLEW="" name="ddr3_odt[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA14" SLEW="" name="ddr3_ras_n" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="U19" SLEW="" name="ddr3_reset_n" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_we_n" IN_TERM="" /> + </PinSelection> + <System_Clock> + <Pin PADName="Y18(MRCC_P)" Bank="33" name="sys_clk_i" /> + </System_Clock> + <System_Control> + <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" /> + <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" /> + <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" /> + </System_Control> + <TimingParameters> + <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" /> + </TimingParameters> + <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength> + <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType> + <mrCasLatency name="CAS Latency" >6</mrCasLatency> + <mrMode name="Mode" >Normal</mrMode> + <mrDllReset name="DLL Reset" >No</mrDllReset> + <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode> + <emrDllEnable name="DLL Enable" >Enable</emrDllEnable> + <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength> + <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection> + <emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection> + <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT> + <emrPosted name="Additive Latency (AL)" >0</emrPosted> + <emrOCD name="Write Leveling Enable" >Disabled</emrOCD> + <emrDQS name="TDQS enable" >Enabled</emrDQS> + <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS> + <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh> + <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency> + <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh> + <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange> + <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR> + <PortInterface>AXI</PortInterface> + <AXIParameters> + <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM> + <C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH> + <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH> + <C0_S_AXI_ID_WIDTH>12</C0_S_AXI_ID_WIDTH> + <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST> + </AXIParameters> + </Controller> + +</Project> diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj new file mode 100644 index 000000000..9494d07ae --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj @@ -0,0 +1,140 @@ +<?xml version='1.0' encoding='UTF-8'?> +<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. --> +<Project NoOfControllers="1" > + <ModuleName>ddr3_16bit</ModuleName> + <dci_inouts_inputs>1</dci_inouts_inputs> + <dci_inputs>1</dci_inputs> + <Debug_En>OFF</Debug_En> + <DataDepth_En>1024</DataDepth_En> + <LowPower_En>ON</LowPower_En> + <XADC_En>Enabled</XADC_En> + <TargetFPGA>xc7z020-clg484/-3</TargetFPGA> + <Version>4.0</Version> + <SystemClock>Single-Ended</SystemClock> + <ReferenceClock>No Buffer</ReferenceClock> + <SysResetPolarity>ACTIVE HIGH</SysResetPolarity> + <BankSelectionFlag>FALSE</BankSelectionFlag> + <InternalVref>1</InternalVref> + <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs> + <dci_cascade>0</dci_cascade> + <FPGADevice> + <selected>7z/xc7z020i-clg484</selected> + </FPGADevice> + <Controller number="0" > + <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice> + <TimePeriod>2500</TimePeriod> + <VccAuxIO>1.8V</VccAuxIO> + <PHYRatio>4:1</PHYRatio> + <InputClkFreq>100</InputClkFreq> + <UIExtraClocks>0</UIExtraClocks> + <MMCM_VCO>800</MMCM_VCO> + <MMCMClkOut0> 1.000</MMCMClkOut0> + <MMCMClkOut1>1</MMCMClkOut1> + <MMCMClkOut2>1</MMCMClkOut2> + <MMCMClkOut3>1</MMCMClkOut3> + <MMCMClkOut4>1</MMCMClkOut4> + <DataWidth>16</DataWidth> + <DeepMemory>1</DeepMemory> + <DataMask>1</DataMask> + <ECC>Disabled</ECC> + <Ordering>Normal</Ordering> + <BankMachineCnt>4</BankMachineCnt> + <CustomPart>FALSE</CustomPart> + <NewPartName></NewPartName> + <RowAddress>15</RowAddress> + <ColAddress>10</ColAddress> + <BankAddress>3</BankAddress> + <MemoryVoltage>1.5V</MemoryVoltage> + <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap> + <PinSelection> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V15" SLEW="" name="ddr3_addr[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_addr[10]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W16" SLEW="" name="ddr3_addr[11]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W18" SLEW="" name="ddr3_addr[12]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W17" SLEW="" name="ddr3_addr[13]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB15" SLEW="" name="ddr3_addr[14]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V14" SLEW="" name="ddr3_addr[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB16" SLEW="" name="ddr3_addr[2]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA16" SLEW="" name="ddr3_addr[3]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_addr[4]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA17" SLEW="" name="ddr3_addr[5]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V17" SLEW="" name="ddr3_addr[6]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U17" SLEW="" name="ddr3_addr[7]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U16" SLEW="" name="ddr3_addr[8]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U15" SLEW="" name="ddr3_addr[9]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y14" SLEW="" name="ddr3_ba[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W13" SLEW="" name="ddr3_ba[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V13" SLEW="" name="ddr3_ba[2]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y13" SLEW="" name="ddr3_cas_n" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y15" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W15" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB14" SLEW="" name="ddr3_cke[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V18" SLEW="" name="ddr3_dm[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA18" SLEW="" name="ddr3_dm[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T21" SLEW="" name="ddr3_dq[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA21" SLEW="" name="ddr3_dq[10]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB21" SLEW="" name="ddr3_dq[11]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB19" SLEW="" name="ddr3_dq[12]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB20" SLEW="" name="ddr3_dq[13]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y19" SLEW="" name="ddr3_dq[14]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA19" SLEW="" name="ddr3_dq[15]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U21" SLEW="" name="ddr3_dq[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T22" SLEW="" name="ddr3_dq[2]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U22" SLEW="" name="ddr3_dq[3]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W20" SLEW="" name="ddr3_dq[4]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W21" SLEW="" name="ddr3_dq[5]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U20" SLEW="" name="ddr3_dq[6]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V20" SLEW="" name="ddr3_dq[7]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA22" SLEW="" name="ddr3_dq[8]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB22" SLEW="" name="ddr3_dq[9]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W22" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y21" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V22" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y20" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U14" SLEW="" name="ddr3_odt[0]" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA14" SLEW="" name="ddr3_ras_n" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="U19" SLEW="" name="ddr3_reset_n" IN_TERM="" /> + <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_we_n" IN_TERM="" /> + </PinSelection> + <System_Clock> + <Pin PADName="Y18(MRCC_P)" Bank="33" name="sys_clk_i" /> + </System_Clock> + <System_Control> + <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" /> + <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" /> + <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" /> + </System_Control> + <TimingParameters> + <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" /> + </TimingParameters> + <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength> + <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType> + <mrCasLatency name="CAS Latency" >6</mrCasLatency> + <mrMode name="Mode" >Normal</mrMode> + <mrDllReset name="DLL Reset" >No</mrDllReset> + <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode> + <emrDllEnable name="DLL Enable" >Enable</emrDllEnable> + <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength> + <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection> + <emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection> + <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT> + <emrPosted name="Additive Latency (AL)" >0</emrPosted> + <emrOCD name="Write Leveling Enable" >Disabled</emrOCD> + <emrDQS name="TDQS enable" >Enabled</emrDQS> + <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS> + <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh> + <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency> + <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh> + <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange> + <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR> + <PortInterface>AXI</PortInterface> + <AXIParameters> + <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM> + <C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH> + <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH> + <C0_S_AXI_ID_WIDTH>12</C0_S_AXI_ID_WIDTH> + <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST> + </AXIParameters> + </Controller> + +</Project> |