From 788fef11ef890c6dcee3be495fc381bcf2990d3b Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Sat, 29 Jan 2022 20:47:36 -0600 Subject: fpga: e31x: Add DRAM support This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 --- fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc | 32 + fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci | 2649 ++++++++++++++++++++ .../top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj | 140 ++ .../top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj | 140 ++ 4 files changed, 2961 insertions(+) create mode 100644 fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc create mode 100644 fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci create mode 100644 fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj create mode 100644 fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj (limited to 'fpga/usrp3/top/e31x/ip/ddr3_16bit') diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc b/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc new file mode 100644 index 000000000..66187c699 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_16BIT_SRCS = $(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit.xci + +IP_DDR3_16BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit.xci.out \ +ddr3_16bit/user_design/rtl/ddr3_16bit.v \ +ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \ +) + +IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit/example_design/rtl/example_top.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \ +) + +IP_DDR3_16BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit/example_design/sim/ddr3_model.sv \ +ddr3_16bit/example_design/sim/ddr3_model_parameters.vh \ +) + +$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS) : $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj + cp -f $(IP_DIR)/ddr3_16bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_16bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_16bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_16bit/mig_a.prj diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci b/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci new file mode 100644 index 000000000..7d467a859 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci @@ -0,0 +1,2649 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr3_16bit + + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + 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OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj new file mode 100644 index 000000000..74d75d1b7 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj @@ -0,0 +1,140 @@ + + + + ddr3_16bit + 1 + 1 + OFF + 1024 + ON + Enabled + xc7z020-clg484/-1 + 4.0 + Single-Ended + No Buffer + ACTIVE HIGH + FALSE + 1 + 50 Ohms + 0 + + 7z/xc7z020i-clg484 + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 2500 + 1.8V + 4:1 + 100 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Disable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 29 + 128 + 12 + 1 + + + + diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj new file mode 100644 index 000000000..9494d07ae --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj @@ -0,0 +1,140 @@ + + + + ddr3_16bit + 1 + 1 + OFF + 1024 + ON + Enabled + xc7z020-clg484/-3 + 4.0 + Single-Ended + No Buffer + ACTIVE HIGH + FALSE + 1 + 50 Ohms + 0 + + 7z/xc7z020i-clg484 + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 2500 + 1.8V + 4:1 + 100 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Disable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 29 + 128 + 12 + 1 + + + + -- cgit v1.2.3