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| author | Wade Fife <wade.fife@ettus.com> | 2022-01-29 20:47:36 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-02-10 18:13:44 -0700 |
| commit | 788fef11ef890c6dcee3be495fc381bcf2990d3b (patch) | |
| tree | 87e9c0da8b56e47e7f1a23aa0a6f8673dbe6d1e0 /fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc | |
| parent | 8444f84add04f025b7e24855e0ba79446e615e01 (diff) | |
| download | uhd-788fef11ef890c6dcee3be495fc381bcf2990d3b.tar.gz uhd-788fef11ef890c6dcee3be495fc381bcf2990d3b.tar.bz2 uhd-788fef11ef890c6dcee3be495fc381bcf2990d3b.zip | |
fpga: e31x: Add DRAM support
This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:
DRAM=1 make E310_SG3
Diffstat (limited to 'fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc')
| -rw-r--r-- | fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc b/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc new file mode 100644 index 000000000..66187c699 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_16BIT_SRCS = $(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit.xci + +IP_DDR3_16BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit.xci.out \ +ddr3_16bit/user_design/rtl/ddr3_16bit.v \ +ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \ +) + +IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit/example_design/rtl/example_top.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \ +) + +IP_DDR3_16BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit/example_design/sim/ddr3_model.sv \ +ddr3_16bit/example_design/sim/ddr3_model_parameters.vh \ +) + +$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS) : $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj + cp -f $(IP_DIR)/ddr3_16bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_16bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_16bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_16bit/mig_a.prj |