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authorBen Hilburn <ben.hilburn@ettus.com>2014-05-14 11:42:19 -0700
committerBen Hilburn <ben.hilburn@ettus.com>2014-05-14 11:42:19 -0700
commit00711ba213dde8aa0a099d2b18d3da0a33e6af79 (patch)
tree612f616ebbf8080b5dc9cb5d64a8062e9aa3a498 /fpga/usrp3/top/b200/planahead/planahead.data/sources_1
parent5de0bfce3f03cc45a1eed93dc1b8df1b188b5040 (diff)
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fpga: updating b200 and x300 FPGA source code for latest images
Diffstat (limited to 'fpga/usrp3/top/b200/planahead/planahead.data/sources_1')
-rw-r--r--fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml26
1 files changed, 26 insertions, 0 deletions
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml
new file mode 100644
index 000000000..b0421e4c2
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
+ <Attr Name="ImportTime" Val="1359508205"/>
+ <Attr Name="UsedInSynthesis" Val="1"/>
+ <Attr Name="UsedInImplementation" Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/coregen/fifo_4k_2clk.ngc">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../coregen/fifo_4k_2clk.ngc"/>
+ <Attr Name="ImportTime" Val="1359144134"/>
+ <Attr Name="UsedInSynthesis" Val="1"/>
+ <Attr Name="UsedInImplementation" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="GateLvl"/>
+ <Option Name="TopModule" Val="b200"/>
+ </Config>
+ </FileSet>
+</DARoots>