From 00711ba213dde8aa0a099d2b18d3da0a33e6af79 Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Wed, 14 May 2014 11:42:19 -0700
Subject: fpga: updating b200 and x300 FPGA source code for latest images

---
 .../planahead/planahead.data/sources_1/fileset.xml | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml

(limited to 'fpga/usrp3/top/b200/planahead/planahead.data/sources_1')

diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml
new file mode 100644
index 000000000..b0421e4c2
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
+        <Attr Name="ImportTime" Val="1359508205"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/coregen/fifo_4k_2clk.ngc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../coregen/fifo_4k_2clk.ngc"/>
+        <Attr Name="ImportTime" Val="1359144134"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="GateLvl"/>
+      <Option Name="TopModule" Val="b200"/>
+    </Config>
+  </FileSet>
+</DARoots>
-- 
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