diff options
| author | Martin Braun <martin.braun@ettus.com> | 2020-01-23 16:10:22 -0800 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2020-01-28 09:35:36 -0800 |
| commit | bafa9d95453387814ef25e6b6256ba8db2df612f (patch) | |
| tree | 39ba24b5b67072d354775272e687796bb511848d /fpga/usrp3/lib/vivado_ipi | |
| parent | 3075b981503002df3115d5f1d0b97d2619ba30f2 (diff) | |
| download | uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.tar.gz uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.tar.bz2 uhd-bafa9d95453387814ef25e6b6256ba8db2df612f.zip | |
Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.
This commit also updates the license files and paths therein.
We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.
== Original Codebase and Rebasing ==
The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/
It can be used for bisecting, reference, and a more detailed history.
The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.
If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:
- Create a directory to store patches (this should be an empty
directory):
mkdir ~/patches
- Now make sure that your FPGA codebase is based on the same state as
the code that was merged:
cd src/fpga # Or wherever your FPGA code is stored
git rebase v4.0.0.0-pre-uhd-merge
Note: The rebase command may look slightly different depending on what
exactly you're trying to rebase.
- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:
git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches
Note: Make sure that only patches are stored in your output directory.
It should otherwise be empty. Make sure that you picked the correct
range of commits, and only commits you wanted to rebase were exported
as patch files.
- Go to the UHD repository and apply the patches:
cd src/uhd # Or wherever your UHD repository is stored
git am --directory fpga ~/patches/*
rm -rf ~/patches # This is for cleanup
== Contributors ==
The following people have contributed mainly to these files (this list
is not complete):
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Diffstat (limited to 'fpga/usrp3/lib/vivado_ipi')
64 files changed, 14582 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd new file mode 100644 index 000000000..322f706a4 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd @@ -0,0 +1,223 @@ +-- +-- Copyright 2018 Ettus Research, A National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0 +-- +-- Module: axi_bitq +-- Description: Simple IP to shift bits in/out (primarily for JTAG) +-- axi_bitq is the processor interface to the bitq_fsm module + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.bitq_fsm; + +entity axi_bitq is +port ( + bit_clk : inout std_logic; + bit_in : in std_logic; + bit_out : inout std_logic; + bit_stb : inout std_logic; + + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(3 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(3 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic +); +end axi_bitq; + +architecture arch of axi_bitq is + signal read_token : std_logic; + signal write_addr : std_logic_vector(3 downto 0); + signal write_strb : std_logic_vector(3 downto 0); + signal write_addr_token : std_logic; + signal write_data : std_logic_vector(31 downto 0); + signal write_data_token : std_logic; + + signal wr_data : std_logic_vector(31 downto 0); + signal stb_data : std_logic_vector(31 downto 0); + signal rd_data : std_logic_vector(31 downto 0); + signal prescalar : std_logic_vector(7 downto 0); + signal len : std_logic_vector(4 downto 0); + signal ready : std_logic; + signal start : std_logic; + signal bitq_rstn : std_logic; + signal bitq_soft_rst : std_logic; + +begin + + S_AXI_ARREADY <= not read_token; + S_AXI_RVALID <= read_token; + S_AXI_RRESP <= "00"; + + S_AXI_AWREADY <= not write_addr_token; + S_AXI_WREADY <= not write_data_token; + S_AXI_BVALID <= write_addr_token and write_data_token; + S_AXI_BRESP <= "00"; + + --Register reads + read_proc : process (S_AXI_ACLK) + variable read_addr : std_logic_vector(S_AXI_ARADDR'left downto S_AXI_ARADDR'right+2); + begin + if rising_edge(S_AXI_ACLK) then + read_addr := S_AXI_ARADDR(S_AXI_ARADDR'left downto S_AXI_ARADDR'right+2); + + if (S_AXI_ARESETN = '0') then + read_token <= '0'; + elsif (S_AXI_ARVALID = '1') and (read_token = '0') then + read_token <= '1'; + elsif (S_AXI_RREADY = '1') and (read_token = '1') then + read_token <= '0'; + end if; + + if (S_AXI_ARVALID = '1') and (read_token = '0') then + S_AXI_RDATA <= (others => '0'); + + case read_addr is + when "00" => + S_AXI_RDATA(31 downto 0) <= wr_data; + when "01" => + S_AXI_RDATA(31 downto 0) <= stb_data; + when "10" => + S_AXI_RDATA(7 downto 0) <= prescalar; + S_AXI_RDATA(12 downto 8) <= len; + S_AXI_RDATA(31) <= ready; + when "11" => + S_AXI_RDATA(31 downto 0) <= rd_data; + when others => + null; + end case; + + end if; + end if; + end process read_proc; + + write_proc : process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if (S_AXI_ARESETN = '0') then + write_addr_token <= '0'; + write_data_token <= '0'; + write_strb <= (others => '0'); + else + if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then + write_addr_token <= '1'; + elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then + write_addr_token <= '0'; + end if; + + if (S_AXI_WVALID = '1') and (write_data_token = '0') then + write_data_token <= '1'; + elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then + write_data_token <= '0'; + end if; + end if; + + if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then + write_addr <= S_AXI_AWADDR; + end if; + + if (S_AXI_WVALID = '1') and (write_data_token = '0') then + write_data <= S_AXI_WDATA; + write_strb <= S_AXI_WSTRB; + end if; + end if; + end process write_proc; + + write_reg : process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + bitq_soft_rst <= '0'; + start <= '0'; + + if (S_AXI_ARESETN = '0') or (bitq_soft_rst = '1') then + bitq_soft_rst <= '0'; + start <= '0'; + elsif (write_addr_token = '1') and (write_data_token = '1') then + case write_addr(write_addr'left downto 2) is + when "00" => + if (write_strb(0) = '1') and (ready = '1') then + wr_data(7 downto 0) <= write_data(7 downto 0); + end if; + if (write_strb(1) = '1') and (ready = '1') then + wr_data(15 downto 8) <= write_data(15 downto 8); + end if; + if (write_strb(2) = '1') and (ready = '1') then + wr_data(23 downto 16) <= write_data(23 downto 16); + end if; + if (write_strb(3) = '1') and (ready = '1') then + wr_data(31 downto 24) <= write_data(31 downto 24); + end if; + when "01" => + if (write_strb(0) = '1') and (ready = '1') then + stb_data(7 downto 0) <= write_data(7 downto 0); + end if; + if (write_strb(1) = '1') and (ready = '1') then + stb_data(15 downto 8) <= write_data(15 downto 8); + end if; + if (write_strb(2) = '1') and (ready = '1') then + stb_data(23 downto 16) <= write_data(23 downto 16); + end if; + if (write_strb(3) = '1') and (ready = '1') then + stb_data(31 downto 24) <= write_data(31 downto 24); + end if; + when "10" => + if (write_strb(0) = '1') and (ready = '1') then + prescalar <= write_data(7 downto 0); + end if; + if (write_strb(1) = '1') and (ready = '1') then + len <= write_data(12 downto 8); + if (write_strb(3) = '0') or (write_data(31) = '0') then + start <= '1'; + end if; + end if; + if (write_strb(3) = '1') then + bitq_soft_rst <= write_data(31); + end if; + when "11" => --Read only register + null; + when others => + null; + end case; + end if; + end if; + end process write_reg; + + bitq_rstn <= '0' when (S_AXI_ARESETN = '0') or (bitq_soft_rst = '1') else '1'; + + bitq_ctrl : entity bitq_fsm + port map ( + clk => S_AXI_ACLK, + rstn => S_AXI_ARESETN, + prescalar => prescalar, + + bit_clk => bit_clk, + bit_in => bit_in, + bit_out => bit_out, + bit_stb => bit_stb, + start => start, + len => len, + ready => ready, + wr_data => wr_data, + stb_data => stb_data, + rd_data => rd_data + ); + +end arch; + diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd new file mode 100644 index 000000000..ed7ab4a50 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd @@ -0,0 +1,128 @@ +-- +-- Copyright 2018 Ettus Research, A National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0 +-- +-- Module: bitq_fsm +-- Description: Simple IP to shift bits in/out (primarily for JTAG) +-- bitq_fsm implements the state machine underlying the IP + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity bitq_fsm is +port ( + clk : in std_logic; + rstn : in std_logic; + prescalar : in std_logic_vector(7 downto 0); + + bit_clk : inout std_logic; + bit_in : in std_logic; + bit_out : inout std_logic; + bit_stb : inout std_logic; + start : in std_logic; + ready : out std_logic; + len : in std_logic_vector(4 downto 0); + wr_data : in std_logic_vector(31 downto 0); + stb_data : in std_logic_vector(31 downto 0); + rd_data : out std_logic_vector(31 downto 0) + +); + +end bitq_fsm; + +architecture arch of bitq_fsm is + type bitq_state_t is (IDLE, LOW, HIGH); + signal bitq_state : bitq_state_t; + + signal bit_clk_count : unsigned(7 downto 0); + signal bit_count : unsigned(5 downto 0); + + signal bit_out_r : std_logic; + signal bit_stb_r : std_logic; + + signal rd_data_r : std_logic_vector(31 downto 0); + +begin + rd_data <= rd_data_r; + + gen_io : process (bitq_state, bit_count, bit_out_r, bit_stb_r) + begin + case (bitq_state) is + when IDLE => + bit_clk <= 'Z'; + bit_out <= 'Z'; + bit_stb <= 'Z'; + ready <= '1'; + when LOW => + bit_clk <= '0'; + bit_out <= bit_out_r; + bit_stb <= bit_stb_r; + ready <= '0'; + when HIGH => + bit_clk <= '1'; + bit_out <= bit_out_r; + bit_stb <= bit_stb_r; + ready <= '0'; + when others => + bit_clk <= 'Z'; + bit_out <= 'Z'; + bit_stb <= 'Z'; + ready <= '1'; + end case; + end process; + + bit_clk_gen : process (clk) + begin + if rising_edge(clk) then + if (rstn = '0') or (bitq_state = IDLE) or + (bit_clk_count = 0) then + bit_clk_count <= unsigned(prescalar); + elsif (bit_clk_count /= 0) then + bit_clk_count <= bit_clk_count - 1; + end if; + end if; + end process bit_clk_gen; + + fsm : process (clk) + begin + if rising_edge(clk) then + if (rstn = '0') then + bitq_state <= IDLE; + bit_count <= to_unsigned(0, bit_count'length); + rd_data_r <= (others => '0'); + else + case bitq_state is + when IDLE => + bit_count <= to_unsigned(0, bit_count'length); + + if (start = '1') then + bitq_state <= LOW; + rd_data_r <= (others => '0'); + bit_out_r <= wr_data(0); + bit_stb_r <= stb_data(0); + end if; + when LOW => + if (bit_clk_count = 0) then + rd_data_r(to_integer(bit_count)) <= bit_in; + bit_count <= bit_count + 1; + bitq_state <= HIGH; --Rising edge + end if; + when HIGH => + if (bit_clk_count = 0) then + if (bit_count > unsigned('0' & len)) then + bitq_state <= IDLE; + else + bit_out_r <= wr_data(to_integer(bit_count)); + bit_stb_r <= stb_data(to_integer(bit_count)); + bitq_state <= LOW; --Falling edge + end if; + end if; + end case; + end if; + end if; + end process fsm; + +end arch; + diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml b/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml new file mode 100644 index 000000000..2f22a5911 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml @@ -0,0 +1,719 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ettus.com</spirit:vendor> + <spirit:library>ip</spirit:library> + <spirit:name>axi_bitq</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>S_AXI</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/> + <spirit:slave> + <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/> + </spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWADDR</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_AWADDR</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_AWVALID</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_AWREADY</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_WDATA</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WSTRB</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_WSTRB</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_WVALID</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_WREADY</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>BRESP</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_BRESP</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>BVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_BVALID</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>BREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_BREADY</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ARADDR</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_ARADDR</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ARVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_ARVALID</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ARREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_ARREADY</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_RDATA</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RRESP</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_RRESP</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_RVALID</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_RREADY</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S_AXI_ARESETN</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + 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<xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion> + <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2663de75"/> + <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="da330753"/> + <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3da6ad7f"/> + <xilinx:checksum xilinx:scope="ports" xilinx:value="15d3ec9b"/> + <xilinx:checksum xilinx:scope="parameters" xilinx:value="0252408f"/> + </xilinx:packagingInfo> + </spirit:vendorExtensions> +</spirit:component> diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd new file mode 100644 index 000000000..a7bc95fe6 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd @@ -0,0 +1,95 @@ +-- +-- Copyright 2018 Ettus Research, A National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0 +-- +-- Module: bitq_fsm_test +-- Description: Manually-checked tester for bitq_fsm +-- + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.bitq_fsm; + +entity bitq_fsm_test is +end bitq_fsm_test; + +architecture sim of bitq_fsm_test is + signal clk : std_logic := '0'; + signal rstn : std_logic; + + signal wr_data : std_logic_vector(31 downto 0); + signal stb_data : std_logic_vector(31 downto 0); + signal rd_data : std_logic_vector(31 downto 0); + signal prescalar : std_logic_vector(7 downto 0); + signal len : std_logic_vector(4 downto 0); + signal ready : std_logic; + signal start : std_logic; + + signal bit_clk : std_logic; + signal bit_in : std_logic; + signal bit_out : std_logic; + signal bit_stb : std_logic; + + constant HALFCYCLE : time := 5 ns; + constant CYCLE : time := 2*HALFCYCLE; + +begin + + process + begin + wait for HALFCYCLE; + clk <= not clk; + end process; + + process + begin + rstn <= '0'; + start <= '0'; + len <= "11111"; + bit_in <= '0'; + prescalar <= X"02"; + wait for CYCLE; + rstn <= '1'; + wait for CYCLE; + wr_data <= X"ABCDEF01"; + stb_data <= X"FF7F7700"; + wait for CYCLE; + start <= '1'; + wait for CYCLE; + start <= '0'; + wait until ready = '1'; + wait for CYCLE; + start <= '1'; + wait for CYCLE; + start <= '0'; + bit_in <= '1'; + wait until ready = '1'; + wait for CYCLE; + bit_in <= '0'; + wait for CYCLE; + report "End of Test"; + end process; + + dut : entity work.bitq_fsm + port map ( + clk => clk, + rstn => rstn, + prescalar => prescalar, + + bit_clk => bit_clk, + bit_in => bit_in, + bit_out => bit_out, + bit_stb => bit_stb, + start => start, + len => len, + ready => ready, + wr_data => wr_data, + stb_data => stb_data, + rd_data => rd_data + ); + +end sim; + diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl new file mode 100644 index 000000000..0db18e9a9 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/2d_transfer.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/2d_transfer.v new file mode 100644 index 000000000..13f4e2dff --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/2d_transfer.v @@ -0,0 +1,142 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_2d_transfer ( + input req_aclk, + input req_aresetn, + + input req_valid, + output reg req_ready, + + input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_LENGTH_WIDTH-1:0] req_x_length, + input [DMA_LENGTH_WIDTH-1:0] req_y_length, + input [DMA_LENGTH_WIDTH-1:0] req_dest_stride, + input [DMA_LENGTH_WIDTH-1:0] req_src_stride, + input req_sync_transfer_start, + output reg req_eot, + + output reg out_req_valid, + input out_req_ready, + output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address, + output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address, + output [DMA_LENGTH_WIDTH-1:0] out_req_length, + output reg out_req_sync_transfer_start, + input out_eot +); + +parameter DMA_LENGTH_WIDTH = 24; +parameter BYTES_PER_BEAT_WIDTH_SRC = 3; +parameter BYTES_PER_BEAT_WIDTH_DEST = 3; + +reg [31:BYTES_PER_BEAT_WIDTH_DEST] dest_address; +reg [31:BYTES_PER_BEAT_WIDTH_SRC] src_address; +reg [DMA_LENGTH_WIDTH-1:0] x_length; +reg [DMA_LENGTH_WIDTH-1:0] y_length; +reg [DMA_LENGTH_WIDTH-1:0] dest_stride; +reg [DMA_LENGTH_WIDTH-1:0] src_stride; + +reg [1:0] req_id; +reg [1:0] eot_id; +reg [3:0] last_req; + +assign out_req_dest_address = dest_address; +assign out_req_src_address = src_address; +assign out_req_length = x_length; + +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + req_id <= 2'b0; + eot_id <= 2'b0; + req_eot <= 1'b0; + end else begin + if (out_req_valid && out_req_ready) begin + req_id <= req_id + 1'b1; + last_req[req_id] <= y_length == 0; + end + req_eot <= 1'b0; + if (out_eot) begin + eot_id <= eot_id + 1'b1; + req_eot <= last_req[eot_id]; + end + end +end + +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + dest_address <= 'h00; + src_address <= 'h00; + x_length <= 'h00; + y_length <= 'h00; + dest_stride <= 'h00; + src_stride <= 'h00; + req_ready <= 1'b1; + out_req_valid <= 1'b0; + out_req_sync_transfer_start <= 1'b0; + end else begin + if (req_ready) begin + if (req_valid) begin + dest_address <= req_dest_address; + src_address <= req_src_address; + x_length <= req_x_length; + y_length <= req_y_length; + dest_stride <= req_dest_stride; + src_stride <= req_src_stride; + out_req_sync_transfer_start <= req_sync_transfer_start; + req_ready <= 1'b0; + out_req_valid <= 1'b1; + end + end else begin + if (out_req_valid && out_req_ready) begin + dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST]; + src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]; + y_length <= y_length - 1'b1; + out_req_sync_transfer_start <= 1'b0; + if (y_length == 0) begin + out_req_valid <= 1'b0; + req_ready <= 1'b1; + end + end + end + end +end + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/address_generator.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/address_generator.v new file mode 100644 index 000000000..8e38486d5 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/address_generator.v @@ -0,0 +1,161 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_address_generator ( + input clk, + input resetn, + + input req_valid, + output reg req_ready, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + + output reg [ID_WIDTH-1:0] id, + input [ID_WIDTH-1:0] request_id, + input sync_id, + + input eot, + + input enable, + input pause, + output reg enabled, + + input addr_ready, + output reg addr_valid, + output [31:0] addr, + output [ 7:0] len, + output [ 2:0] size, + output [ 1:0] burst, + output [ 2:0] prot, + output [ 3:0] cache +); + + +parameter ID_WIDTH = 3; +parameter DMA_DATA_WIDTH = 64; +parameter BEATS_PER_BURST_WIDTH = 4; +parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8); +localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH); + +`include "inc_id.h" + +assign burst = 2'b01; +assign prot = 3'b000; +assign cache = 4'b0011; +assign len = length; +assign size = $clog2(DMA_DATA_WIDTH/8); + +reg [7:0] length = 'h0; +reg [31-BYTES_PER_BEAT_WIDTH:0] address = 'h00; +reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00; +assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}}; + +reg addr_valid_d1; +reg last = 1'b0; + +// If we already asserted addr_valid we have to wait until it is accepted before +// we can disable the address generator. +always @(posedge clk) begin + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (enable) + enabled <= 1'b1; + else if (~addr_valid) + enabled <= 1'b0; + end +end + +always @(posedge clk) begin + if (addr_valid == 1'b0) begin + if (eot == 1'b1) + length <= last_burst_len; + else + length <= MAX_BEATS_PER_BURST - 1; + end +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + last <= 1'b0; + end else if (addr_valid == 1'b0) begin + last <= eot; + end +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + address <= 'h00; + last_burst_len <= 'h00; + req_ready <= 1'b1; + addr_valid <= 1'b0; + end else begin + if (~enabled) begin + req_ready <= 1'b1; + end else if (req_ready) begin + if (req_valid && enable) begin + address <= req_address; + req_ready <= 1'b0; + last_burst_len <= req_last_burst_length; + end + end else begin + if (addr_valid && addr_ready) begin + address <= address + MAX_BEATS_PER_BURST; + addr_valid <= 1'b0; + if (last) + req_ready <= 1'b1; + end else if (id != request_id && enable) begin + addr_valid <= 1'b1; + end + end + end +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + id <='h0; + addr_valid_d1 <= 1'b0; + end else begin + addr_valid_d1 <= addr_valid; + if ((addr_valid && ~addr_valid_d1) || + (sync_id && id != request_id)) + id <= inc_id(id); + + end +end + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac.v new file mode 100644 index 000000000..ad8019792 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac.v @@ -0,0 +1,672 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// Source: git://github.com/analogdevicesinc/hdl.git +// Commit hash: 04843795d8d6a496c00ee91b437d57924bc1cbf1 + +module axi_dmac ( + // Slave AXI interface + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + // Interrupt + output reg irq, + + // Master AXI interface + input m_dest_axi_aclk, + input m_dest_axi_aresetn, + + // Write address + output [31:0] m_dest_axi_awaddr, + output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen, + output [ 2:0] m_dest_axi_awsize, + output [ 1:0] m_dest_axi_awburst, + output [ 2:0] m_dest_axi_awprot, + output [ 3:0] m_dest_axi_awcache, + output m_dest_axi_awvalid, + input m_dest_axi_awready, + + // Write data + output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb, + input m_dest_axi_wready, + output m_dest_axi_wvalid, + output m_dest_axi_wlast, + + // Write response + input m_dest_axi_bvalid, + input [ 1:0] m_dest_axi_bresp, + output m_dest_axi_bready, + + // Unused read interface + output m_dest_axi_arvalid, + output [31:0] m_dest_axi_araddr, + output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen, + output [ 2:0] m_dest_axi_arsize, + output [ 1:0] m_dest_axi_arburst, + output [ 3:0] m_dest_axi_arcache, + output [ 2:0] m_dest_axi_arprot, + input m_dest_axi_arready, + input m_dest_axi_rvalid, + input [ 1:0] m_dest_axi_rresp, + input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata, + output m_dest_axi_rready, + + // Master AXI interface + input m_src_axi_aclk, + input m_src_axi_aresetn, + + // Read address + input m_src_axi_arready, + output m_src_axi_arvalid, + output [31:0] m_src_axi_araddr, + output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen, + output [ 2:0] m_src_axi_arsize, + output [ 1:0] m_src_axi_arburst, + output [ 2:0] m_src_axi_arprot, + output [ 3:0] m_src_axi_arcache, + + // Read data and response + input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata, + output m_src_axi_rready, + input m_src_axi_rvalid, + input [ 1:0] m_src_axi_rresp, + + // Unused write interface + output m_src_axi_awvalid, + output [31:0] m_src_axi_awaddr, + output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen, + output [ 2:0] m_src_axi_awsize, + output [ 1:0] m_src_axi_awburst, + output [ 3:0] m_src_axi_awcache, + output [ 2:0] m_src_axi_awprot, + input m_src_axi_awready, + output m_src_axi_wvalid, + output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata, + output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb, + output m_src_axi_wlast, + input m_src_axi_wready, + input m_src_axi_bvalid, + input [ 1:0] m_src_axi_bresp, + output m_src_axi_bready, + + // Slave streaming AXI interface + input s_axis_aclk, + output s_axis_ready, + input s_axis_valid, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input [0:0] s_axis_user, + output s_axis_xfer_req, + + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_ready, + output m_axis_valid, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + output m_axis_last, + output m_axis_xfer_req, + + // Input FIFO interface + input fifo_wr_clk, + input fifo_wr_en, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + output fifo_wr_overflow, + input fifo_wr_sync, + output fifo_wr_xfer_req, + + // Input FIFO interface + input fifo_rd_clk, + input fifo_rd_en, + output fifo_rd_valid, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output fifo_rd_underflow, + output fifo_rd_xfer_req +); + +parameter ID = 0; + +parameter DMA_DATA_WIDTH_SRC = 64; +parameter DMA_DATA_WIDTH_DEST = 64; +parameter DMA_LENGTH_WIDTH = 24; +parameter DMA_2D_TRANSFER = 1; + +parameter ASYNC_CLK_REQ_SRC = 1; +parameter ASYNC_CLK_SRC_DEST = 1; +parameter ASYNC_CLK_DEST_REQ = 1; + +parameter AXI_SLICE_DEST = 0; +parameter AXI_SLICE_SRC = 0; +parameter SYNC_TRANSFER_START = 0; +parameter CYCLIC = 1; + +parameter DMA_AXI_PROTOCOL_DEST = 0; +parameter DMA_AXI_PROTOCOL_SRC = 0; +parameter DMA_TYPE_DEST = 0; +parameter DMA_TYPE_SRC = 2; + +parameter MAX_BYTES_PER_BURST = 128; +parameter FIFO_SIZE = 4; // In bursts + +localparam DMA_TYPE_AXI_MM = 0; +localparam DMA_TYPE_AXI_STREAM = 1; +localparam DMA_TYPE_FIFO = 2; + +localparam PCORE_VERSION = 'h00040062; + +localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM; +localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM; + +// Argh... "[Synth 8-2722] system function call clog2 is not allowed here" +localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 : + DMA_DATA_WIDTH_DEST > 512 ? 7 : + DMA_DATA_WIDTH_DEST > 256 ? 6 : + DMA_DATA_WIDTH_DEST > 128 ? 5 : + DMA_DATA_WIDTH_DEST > 64 ? 4 : + DMA_DATA_WIDTH_DEST > 32 ? 3 : + DMA_DATA_WIDTH_DEST > 16 ? 2 : + DMA_DATA_WIDTH_DEST > 8 ? 1 : 0; +localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 : + DMA_DATA_WIDTH_SRC > 512 ? 7 : + DMA_DATA_WIDTH_SRC > 256 ? 6 : + DMA_DATA_WIDTH_SRC > 128 ? 5 : + DMA_DATA_WIDTH_SRC > 64 ? 4 : + DMA_DATA_WIDTH_SRC > 32 ? 3 : + DMA_DATA_WIDTH_SRC > 16 ? 2 : + DMA_DATA_WIDTH_SRC > 8 ? 1 : 0; +localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 : + (FIFO_SIZE) > 32 ? 7 : + (FIFO_SIZE) > 16 ? 6 : + (FIFO_SIZE) > 8 ? 5 : + (FIFO_SIZE) > 4 ? 4 : + (FIFO_SIZE) > 2 ? 3 : + (FIFO_SIZE) > 1 ? 2 : 1; + +// Register interface signals +reg [31:0] up_rdata = 'd0; +reg up_wack = 1'b0; +reg up_rack = 1'b0; +wire up_wreq; +wire up_rreq; +wire [31:0] up_wdata; +wire [11:0] up_waddr; +wire [11:0] up_raddr; + +// Scratch register +reg [31:0] up_scratch = 'h00; + +// Control bits +reg up_enable = 'h00; +reg up_pause = 'h00; + +// Start and end of transfer +wire up_eot; // Asserted for one cycle when a transfer has been completed +wire up_sot; // Asserted for one cycle when a transfer has been queued + +// Interupt handling +reg [1:0] up_irq_mask = 'h3; +reg [1:0] up_irq_source = 'h0; +wire [1:0] up_irq_pending; +wire [1:0] up_irq_trigger; +wire [1:0] up_irq_source_clear; + +// DMA transfer signals +reg up_dma_req_valid = 1'b0; +wire up_dma_req_ready; + +reg [1:0] up_transfer_id = 2'b0; +reg [1:0] up_transfer_id_eot = 2'b0; +reg [3:0] up_transfer_done_bitmap = 4'b0; +reg up_axis_xlast = 1'b1; + +reg [31:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00; +reg [31:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00; +reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00; +reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00; +reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00; +reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00; +reg up_dma_cyclic = CYCLIC; +wire up_dma_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0; + +// ID signals from the DMAC, just for debugging +wire [ID_WIDTH-1:0] dest_request_id; +wire [ID_WIDTH-1:0] dest_data_id; +wire [ID_WIDTH-1:0] dest_address_id; +wire [ID_WIDTH-1:0] dest_response_id; +wire [ID_WIDTH-1:0] src_request_id; +wire [ID_WIDTH-1:0] src_data_id; +wire [ID_WIDTH-1:0] src_address_id; +wire [ID_WIDTH-1:0] src_response_id; +wire [7:0] dbg_status; + +assign m_dest_axi_araddr = 'd0; +assign m_dest_axi_arlen = 'd0; +assign m_dest_axi_arsize = 'd0; +assign m_dest_axi_arburst = 'd0; +assign m_dest_axi_arcache = 'd0; +assign m_dest_axi_arprot = 'd0; +assign m_src_axi_awaddr = 'd0; +assign m_src_axi_awlen = 'd0; +assign m_src_axi_awsize = 'd0; +assign m_src_axi_awburst = 'd0; +assign m_src_axi_awcache = 'd0; +assign m_src_axi_awprot = 'd0; +assign m_src_axi_wdata = 'd0; +assign m_src_axi_wstrb = 'd0; +assign m_src_axi_wlast = 'd0; + +up_axi #( + .ADDRESS_WIDTH (12) +) i_up_axi ( + .up_rstn(s_axi_aresetn), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack) +); + +// IRQ handling +assign up_irq_pending = ~up_irq_mask & up_irq_source; +assign up_irq_trigger = {up_eot, up_sot}; +assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 12'h021) ? up_wdata[1:0] : 0; + +always @(posedge s_axi_aclk) +begin + if (s_axi_aresetn == 1'b0) + irq <= 1'b0; + else + irq <= |up_irq_pending; +end + +always @(posedge s_axi_aclk) +begin + if (s_axi_aresetn == 1'b0) begin + up_irq_source <= 2'b00; + end else begin + up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear); + end +end + +// Register Interface + +always @(posedge s_axi_aclk) +begin + if (s_axi_aresetn == 1'b0) begin + up_enable <= 'h00; + up_pause <= 'h00; + up_dma_src_address <= 'h00; + up_dma_dest_address <= 'h00; + up_dma_y_length <= 'h00; + up_dma_x_length <= 'h00; + up_dma_dest_stride <= 'h00; + up_dma_src_stride <= 'h00; + up_irq_mask <= 3'b11; + up_dma_req_valid <= 1'b0; + up_scratch <= 'h00; + up_wack <= 1'b0; + end else begin + up_wack <= up_wreq; + if (up_enable == 1'b1) begin + if (up_wreq && up_waddr == 12'h102) begin + up_dma_req_valid <= up_dma_req_valid | up_wdata[0]; + end else if (up_sot) begin + up_dma_req_valid <= 1'b0; + end + end else begin + up_dma_req_valid <= 1'b0; + end + + if (up_wreq) begin + case (up_waddr) + 12'h002: up_scratch <= up_wdata; + 12'h020: up_irq_mask <= up_wdata; + 12'h100: {up_pause, up_enable} <= up_wdata[1:0]; + 12'h103: begin + if (CYCLIC) up_dma_cyclic <= up_wdata[0]; + up_axis_xlast <= up_wdata[1]; + end + 12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST]; + 12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC]; + 12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + endcase + end + end +end + +always @(posedge s_axi_aclk) +begin + if (s_axi_aresetn == 1'b0) begin + up_rack <= 'd0; + up_rdata <= 'h00; + end else begin + up_rack <= up_rreq; + case (up_raddr) + 12'h000: up_rdata <= PCORE_VERSION; + 12'h001: up_rdata <= ID; + 12'h002: up_rdata <= up_scratch; + 12'h003: up_rdata <= 32'h444d4143; // "DMAC" + 12'h020: up_rdata <= up_irq_mask; + 12'h021: up_rdata <= up_irq_pending; + 12'h022: up_rdata <= up_irq_source; + 12'h100: up_rdata <= {up_pause, up_enable}; + 12'h101: up_rdata <= up_transfer_id; + 12'h102: up_rdata <= up_dma_req_valid; + 12'h103: up_rdata <= {30'h00, up_axis_xlast, up_dma_cyclic}; // Flags + 12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00; + 12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00; + 12'h106: up_rdata <= up_dma_x_length; + 12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00; + 12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00; + 12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00; + 12'h10a: up_rdata <= up_transfer_done_bitmap; + 12'h10b: up_rdata <= up_transfer_id_eot; + 12'h10c: up_rdata <= 'h00; // Status + 12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address + 12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address + 12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id, + 1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id}; + 12'h110: up_rdata <= dbg_status; + default: up_rdata <= 'h00; + endcase + end +end + +// Request ID and Request done bitmap handling +always @(posedge s_axi_aclk) +begin + if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin + up_transfer_id <= 'h0; + up_transfer_id_eot <= 'h0; + up_transfer_done_bitmap <= 'h0; + end begin + if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin + up_transfer_id <= up_transfer_id + 1'b1; + up_transfer_done_bitmap[up_transfer_id] <= 1'b0; + end + if (up_eot == 1'b1) begin + up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1; + up_transfer_id_eot <= up_transfer_id_eot + 1'b1; + end + end +end + +wire dma_req_valid; +wire dma_req_ready; +wire [31:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address; +wire [31:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address; +wire [DMA_LENGTH_WIDTH-1:0] dma_req_length; +wire dma_req_eot; +wire dma_req_sync_transfer_start; +wire up_req_eot; + +assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready; +assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot; + + +generate if (DMA_2D_TRANSFER == 1) begin + +dmac_2d_transfer #( + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC) +) i_2d_transfer ( + .req_aclk(s_axi_aclk), + .req_aresetn(s_axi_aresetn), + + .req_eot(up_req_eot), + + .req_valid(up_dma_req_valid), + .req_ready(up_dma_req_ready), + .req_dest_address(up_dma_dest_address), + .req_src_address(up_dma_src_address), + .req_x_length(up_dma_x_length), + .req_y_length(up_dma_y_length), + .req_dest_stride(up_dma_dest_stride), + .req_src_stride(up_dma_src_stride), + .req_sync_transfer_start(up_dma_sync_transfer_start), + + .out_req_valid(dma_req_valid), + .out_req_ready(dma_req_ready), + .out_req_dest_address(dma_req_dest_address), + .out_req_src_address(dma_req_src_address), + .out_req_length(dma_req_length), + .out_req_sync_transfer_start(dma_req_sync_transfer_start), + .out_eot(dma_req_eot) +); + +end else begin + +assign dma_req_valid = up_dma_req_valid; +assign up_dma_req_ready = dma_req_ready; +assign dma_req_dest_address = up_dma_dest_address; +assign dma_req_src_address = up_dma_src_address; +assign dma_req_length = up_dma_x_length; +assign dma_req_sync_transfer_start = up_dma_sync_transfer_start; +assign up_req_eot = dma_req_eot; + +end endgenerate + +dmac_request_arb #( + .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC), + .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .DMA_TYPE_DEST(DMA_TYPE_DEST), + .DMA_TYPE_SRC(DMA_TYPE_SRC), + .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC), + .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST), + .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ), + .AXI_SLICE_DEST(AXI_SLICE_DEST), + .AXI_SLICE_SRC(AXI_SLICE_SRC), + .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST), + .FIFO_SIZE(FIFO_SIZE), + .ID_WIDTH(ID_WIDTH) +) i_request_arb ( + .req_aclk(s_axi_aclk), + .req_aresetn(s_axi_aresetn), + + .enable(up_enable), + .pause(up_pause), + + .req_valid(dma_req_valid), + .req_ready(dma_req_ready), + .req_dest_address(dma_req_dest_address), + .req_src_address(dma_req_src_address), + .req_length(dma_req_length), + .req_xlast(up_axis_xlast), + .req_sync_transfer_start(dma_req_sync_transfer_start), + + .eot(dma_req_eot), + + + .m_dest_axi_aclk(m_dest_axi_aclk), + .m_dest_axi_aresetn(m_dest_axi_aresetn), + .m_src_axi_aclk(m_src_axi_aclk), + .m_src_axi_aresetn(m_src_axi_aresetn), + + + .m_axi_awaddr(m_dest_axi_awaddr), + .m_axi_awlen(m_dest_axi_awlen), + .m_axi_awsize(m_dest_axi_awsize), + .m_axi_awburst(m_dest_axi_awburst), + .m_axi_awprot(m_dest_axi_awprot), + .m_axi_awcache(m_dest_axi_awcache), + .m_axi_awvalid(m_dest_axi_awvalid), + .m_axi_awready(m_dest_axi_awready), + + + .m_axi_wdata(m_dest_axi_wdata), + .m_axi_wstrb(m_dest_axi_wstrb), + .m_axi_wready(m_dest_axi_wready), + .m_axi_wvalid(m_dest_axi_wvalid), + .m_axi_wlast(m_dest_axi_wlast), + + + .m_axi_bvalid(m_dest_axi_bvalid), + .m_axi_bresp(m_dest_axi_bresp), + .m_axi_bready(m_dest_axi_bready), + + + .m_axi_arready(m_src_axi_arready), + .m_axi_arvalid(m_src_axi_arvalid), + .m_axi_araddr(m_src_axi_araddr), + .m_axi_arlen(m_src_axi_arlen), + .m_axi_arsize(m_src_axi_arsize), + .m_axi_arburst(m_src_axi_arburst), + .m_axi_arprot(m_src_axi_arprot), + .m_axi_arcache(m_src_axi_arcache), + + + .m_axi_rdata(m_src_axi_rdata), + .m_axi_rready(m_src_axi_rready), + .m_axi_rvalid(m_src_axi_rvalid), + .m_axi_rresp(m_src_axi_rresp), + + + .s_axis_aclk(s_axis_aclk), + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_data(s_axis_data), + .s_axis_user(s_axis_user), + .s_axis_xfer_req(s_axis_xfer_req), + + + .m_axis_aclk(m_axis_aclk), + .m_axis_ready(m_axis_ready), + .m_axis_valid(m_axis_valid), + .m_axis_data(m_axis_data), + .m_axis_last(m_axis_last), + .m_axis_xfer_req(m_axis_xfer_req), + + + .fifo_wr_clk(fifo_wr_clk), + .fifo_wr_en(fifo_wr_en), + .fifo_wr_din(fifo_wr_din), + .fifo_wr_overflow(fifo_wr_overflow), + .fifo_wr_sync(fifo_wr_sync), + .fifo_wr_xfer_req(fifo_wr_xfer_req), + + + .fifo_rd_clk(fifo_rd_clk), + .fifo_rd_en(fifo_rd_en), + .fifo_rd_valid(fifo_rd_valid), + .fifo_rd_dout(fifo_rd_dout), + .fifo_rd_underflow(fifo_rd_underflow), + .fifo_rd_xfer_req(fifo_rd_xfer_req), + + // DBG + .dbg_dest_request_id(dest_request_id), + .dbg_dest_address_id(dest_address_id), + .dbg_dest_data_id(dest_data_id), + .dbg_dest_response_id(dest_response_id), + .dbg_src_request_id(src_request_id), + .dbg_src_address_id(src_address_id), + .dbg_src_data_id(src_data_id), + .dbg_src_response_id(src_response_id), + .dbg_status(dbg_status) +); + +assign m_dest_axi_arvalid = 1'b0; +assign m_dest_axi_rready = 1'b0; +assign m_dest_axi_araddr = 'h0; +assign m_dest_axi_arlen = 'h0; +assign m_dest_axi_arsize = 'h0; +assign m_dest_axi_arburst = 'h0; +assign m_dest_axi_arcache = 'h0; +assign m_dest_axi_arprot = 'h0; + +assign m_src_axi_awvalid = 1'b0; +assign m_src_axi_wvalid = 1'b0; +assign m_src_axi_bready = 1'b0; +assign m_src_axi_awvalid = 'h0; +assign m_src_axi_awaddr = 'h0; +assign m_src_axi_awlen = 'h0; +assign m_src_axi_awsize = 'h0; +assign m_src_axi_awburst = 'h0; +assign m_src_axi_awcache = 'h0; +assign m_src_axi_awprot = 'h0; +assign m_src_axi_wvalid = 'h0; +assign m_src_axi_wdata = 'h0; +assign m_src_axi_wstrb = 'h0; +assign m_src_axi_wlast = 'h0; + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac_constr.ttcl b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac_constr.ttcl new file mode 100644 index 000000000..a2cabf55f --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_dmac_constr.ttcl @@ -0,0 +1,167 @@ +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set async_dest_req [getBooleanValue "ASYNC_CLK_DEST_REQ"] :> +<: set async_req_src [getBooleanValue "ASYNC_CLK_REQ_SRC"] :> +<: set async_src_dest [getBooleanValue "ASYNC_CLK_SRC_DEST"] :> + +set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]] +set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]] + +<: if {$async_req_src || $async_src_dest || $async_dest_req} { :> +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage1_reg*] \ + [get_cells -quiet -hier *cdc_sync_stage2_reg*] + +<: } :> +<: if {$async_req_src} { :> +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_false_path -quiet \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_status_src* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_control_src* && IS_SEQUENTIAL}] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_src_req_fifo* && IS_SEQUENTIAL}] \ + -to $src_clk \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *eot_mem_reg* \ + -filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \ + -to $src_clk \ + [get_property -min PERIOD $src_clk] + +<: } :> +<: if {$async_dest_req} { :> +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_req_response_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_false_path -quiet \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_status_dest* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_control_dest* && IS_SEQUENTIAL}] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_dest_req_fifo* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_dest_response_fifo* && IS_SEQUENTIAL}] \ + -to $req_clk \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *eot_mem_reg* \ + -filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +<: } :> +<: if {$async_src_dest} { :> +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +# In SDP mode REGCEB should not be connected. When inferring the BRAM the tools +# do it anyway. The signal is not used by the BRAM though. But since the clock +# associated with REGCEB is the write clock and not the read clock we get a +# timing problem. Mark the path as a false path so it is not timed. +set_false_path -quiet \ + -to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}] + +<: } :> +# Reset signals +set_false_path -quiet \ + -from $req_clk \ + -to [get_pins -quiet -hier *reset_shift_reg*/PRE] + +# Ignore timing for debug signals to register map +set_false_path -quiet \ + -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {name =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {name =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_register_slice.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_register_slice.v new file mode 100644 index 000000000..159f0d0fe --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/axi_register_slice.v @@ -0,0 +1,139 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module axi_register_slice ( + input clk, + input resetn, + + input s_axi_valid, + output s_axi_ready, + input [DATA_WIDTH-1:0] s_axi_data, + + output m_axi_valid, + input m_axi_ready, + output [DATA_WIDTH-1:0] m_axi_data +); + +parameter DATA_WIDTH = 32; + +parameter FORWARD_REGISTERED = 0; +parameter BACKWARD_REGISTERED = 0; + +/* + s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data + s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid + s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready + + (1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid + (2) BACKWARD_REGISTERED insters a FF before s_axi_ready +*/ + +wire [DATA_WIDTH-1:0] bwd_data_s; +wire bwd_valid_s; +wire bwd_ready_s; +wire [DATA_WIDTH-1:0] fwd_data_s; +wire fwd_valid_s; +wire fwd_ready_s; + +generate if (FORWARD_REGISTERED == 1) begin + +reg fwd_valid = 1'b0; +reg [DATA_WIDTH-1:0] fwd_data = 'h00; + +assign fwd_ready_s = ~fwd_valid | m_axi_ready; +assign fwd_valid_s = fwd_valid; +assign fwd_data_s = fwd_data; + +always @(posedge clk) begin + if (~fwd_valid | m_axi_ready) + fwd_data <= bwd_data_s; +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + fwd_valid <= 1'b0; + end else begin + if (bwd_valid_s) + fwd_valid <= 1'b1; + else if (m_axi_ready) + fwd_valid <= 1'b0; + end +end + +end else begin +assign fwd_data_s = bwd_data_s; +assign fwd_valid_s = bwd_valid_s; +assign fwd_ready_s = m_axi_ready; +end +endgenerate + +generate if (BACKWARD_REGISTERED == 1) begin + +reg bwd_ready = 1'b1; +reg [DATA_WIDTH-1:0] bwd_data = 'h00; + +assign bwd_valid_s = ~bwd_ready | s_axi_valid; +assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data; +assign bwd_ready_s = bwd_ready; + +always @(posedge clk) begin + if (bwd_ready) + bwd_data <= s_axi_data; +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + bwd_ready <= 1'b1; + end else begin + if (fwd_ready_s) + bwd_ready <= 1'b1; + else if (s_axi_valid) + bwd_ready <= 1'b0; + end +end + +end else begin +assign bwd_valid_s = s_axi_valid; +assign bwd_data_s = s_axi_data; +assign bwd_ready_s = fwd_ready_s; +end endgenerate + +assign m_axi_data = fwd_data_s; +assign m_axi_valid = fwd_valid_s; +assign s_axi_ready = bwd_ready_s; + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/bd/bd.tcl b/fpga/usrp3/lib/vivado_ipi/axi_dmac/bd/bd.tcl new file mode 100644 index 000000000..d67f5134c --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/bd/bd.tcl @@ -0,0 +1,115 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip \ + "ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ" + + # On ZYNQ the core is most likely connected to the AXI3 HP ports so use AXI3 + # as the default. + set family [string tolower [get_property FAMILY [get_property PART [current_project]]]] + if {$family == "zynq"} { + set axi_protocol 1 + } else { + set axi_protocol 0 + } + + foreach dir {SRC DEST} { + # This is a bit of a hack, but we can't change the protocol if the type + # is not AXI MM + set old [get_property "CONFIG.DMA_TYPE_${dir}" $ip] + set_property "CONFIG.DMA_TYPE_${dir}" "0" $ip + set_property "CONFIG.DMA_AXI_PROTOCOL_${dir}" $axi_protocol $ip + set_property "CONFIG.DMA_TYPE_${dir}" $old $ip + } +} + +proc post_config_ip {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + # Update AXI interface properties according to configuration + set max_bytes_per_burst [get_property "CONFIG.MAX_BYTES_PER_BURST" $ip] + set fifo_size [get_property "CONFIG.FIFO_SIZE" $ip] + + foreach dir {"SRC" "DEST"} { + set type [get_property "CONFIG.DMA_TYPE_$dir" $ip] + if {$type != 0} { + continue + } + + set data_width [get_property "CONFIG.DMA_DATA_WIDTH_$dir" $ip] + set max_beats_per_burst [expr {int(ceil($max_bytes_per_burst * 8.0 / $data_width))}] + + set intf [get_bd_intf_pins [format "%s/m_%s_axi" $cellpath [string tolower $dir]]] + set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf + + # The core issues as many requests as the amount of data the FIFO can hold + if {$dir == "SRC"} { + set_property CONFIG.NUM_WRITE_OUTSTANDING 0 $intf + set_property CONFIG.NUM_READ_OUTSTANDING $fifo_size $intf + } else { + set_property CONFIG.NUM_WRITE_OUTSTANDING $fifo_size $intf + set_property CONFIG.NUM_READ_OUTSTANDING 0 $intf + } + } +} + +proc axi_dmac_detect_async_clk { cellpath ip param_name clk_a clk_b } { + set param_src [get_property "CONFIG.$param_name.VALUE_SRC" $ip] + if {[string equal $param_src "USER"]} { + return; + } + + set clk_domain_a [get_property CONFIG.CLK_DOMAIN $clk_a] + set clk_domain_b [get_property CONFIG.CLK_DOMAIN $clk_b] + set clk_freq_a [get_property CONFIG.FREQ_HZ $clk_a] + set clk_freq_b [get_property CONFIG.FREQ_HZ $clk_b] + set clk_phase_a [get_property CONFIG.PHASE $clk_a] + set clk_phase_b [get_property CONFIG.PHASE $clk_b] + + # Only mark it as sync if we can make sure that it is sync, if the + # relationship of the clocks is unknown mark it as async + if {$clk_domain_a != {} && $clk_domain_b != {} && \ + $clk_domain_a == $clk_domain_b && $clk_freq_a == $clk_freq_b && \ + $clk_phase_a == $clk_phase_b} { + set clk_async 0 + } else { + set clk_async 1 + } + + set_property "CONFIG.$param_name" $clk_async $ip + +# if {$clk_async == 0} { +# bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are synchronous" +# } else { +# bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are asynchronous" +# } +} + +proc propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + set src_type [get_property CONFIG.DMA_TYPE_SRC $ip] + set dest_type [get_property CONFIG.DMA_TYPE_DEST $ip] + + set req_clk [get_bd_pins "$ip/s_axi_aclk"] + + if {$src_type == 2} { + set src_clk [get_bd_pins "$ip/fifo_wr_clk"] + } elseif {$src_type == 1} { + set src_clk [get_bd_pins "$ip/s_axis_aclk"] + } else { + set src_clk [get_bd_pins "$ip/m_src_axi_aclk"] + } + + if {$dest_type == 2} { + set dest_clk [get_bd_pins "$ip/fifo_rd_clk"] + } elseif {$dest_type == 1} { + set dest_clk [get_bd_pins "$ip/m_axis_aclk"] + } else { + set dest_clk [get_bd_pins "$ip/m_dest_axi_aclk"] + } + + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_REQ_SRC" $req_clk $src_clk + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_SRC_DEST" $src_clk $dest_clk + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_DEST_REQ" $dest_clk $req_clk +} diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/component.xml b/fpga/usrp3/lib/vivado_ipi/axi_dmac/component.xml new file mode 100644 index 000000000..a3626529e --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/component.xml @@ -0,0 +1,4107 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>analog.com</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>axi_dmac</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>s_axi</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/> + <spirit:slave> + <spirit:memoryMapRef spirit:memoryMapRef="s_axi"/> + </spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWADDR</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_awaddr</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWPROT</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_awprot</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_awvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_awready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_wdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WSTRB</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_wstrb</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_wvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_wready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>BRESP</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_bresp</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>BVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_bvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>BREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_bready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ARADDR</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_araddr</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ARPROT</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_arprot</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ARVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_arvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ARREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_arready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_rdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RRESP</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_rresp</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_rvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axi_rready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>s_axi_aclk</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" 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a/fpga/usrp3/lib/vivado_ipi/axi_dmac/data_mover.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/data_mover.v new file mode 100644 index 000000000..1f1b9dc04 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/data_mover.v @@ -0,0 +1,176 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_data_mover ( + input clk, + input resetn, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input sync_id, + input eot, + + input enable, + output reg enabled, + + output xfer_req, + + output s_axi_ready, + input s_axi_valid, + input [DATA_WIDTH-1:0] s_axi_data, + + input m_axi_ready, + output m_axi_valid, + output [DATA_WIDTH-1:0] m_axi_data, + output m_axi_last, + + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length +); + +parameter ID_WIDTH = 3; +parameter DATA_WIDTH = 64; +parameter DISABLE_WAIT_FOR_ID = 1; +parameter BEATS_PER_BURST_WIDTH = 4; +parameter LAST = 0; /* 0 = last asserted at the end of each burst, 1 = last only asserted at the end of the transfer */ + +localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH); + +`include "inc_id.h" + +reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00; +reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00; +reg [ID_WIDTH-1:0] id = 'h00; +reg [ID_WIDTH-1:0] id_next = 'h00; + +reg pending_burst = 1'b0; +reg active = 1'b0; +reg last_eot = 1'b0; +reg last_non_eot = 1'b0; + +wire last_load; +wire last; + +assign xfer_req = active; + +assign response_id = id; + +assign last = eot ? last_eot : last_non_eot; + +assign s_axi_ready = m_axi_ready & pending_burst & active; +assign m_axi_valid = s_axi_valid & pending_burst & active; +assign m_axi_data = s_axi_data; +assign m_axi_last = LAST ? (last_eot & eot) : last; + +// If we want to support zero delay between transfers we have to assert +// req_ready on the same cycle on which the last load happens. +assign last_load = s_axi_ready && s_axi_valid && last_eot && eot; +assign req_ready = last_load || ~active; + +always @(posedge clk) begin + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (enable) begin + enabled <= 1'b1; + end else begin + if (DISABLE_WAIT_FOR_ID == 0) begin + // We are not allowed to just deassert valid, so wait until the + // current beat has been accepted + if (~s_axi_valid || m_axi_ready) + enabled <= 1'b0; + end else begin + // For memory mapped AXI busses we have to complete all pending + // burst requests before we can disable the data mover. + if (response_id == request_id) + enabled <= 1'b0; + end + end + end +end + +always @(posedge clk) begin + if (req_ready) begin + last_eot <= req_last_burst_length == 'h0; + last_non_eot <= 1'b0; + beat_counter <= 'h1; + end else if (s_axi_ready && s_axi_valid) begin + last_eot <= beat_counter == last_burst_length; + last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1; + beat_counter <= beat_counter + 1; + end +end + +always @(posedge clk) begin + if (req_ready) + last_burst_length <= req_last_burst_length; +end + +always @(posedge clk) begin + if (enabled == 1'b0 || resetn == 1'b0) begin + active <= 1'b0; + end else if (req_valid) begin + active <= 1'b1; + end else if (last_load) begin + active <= 1'b0; + end +end + +always @(*) +begin + if ((s_axi_ready && s_axi_valid && last) || + (sync_id && pending_burst)) + id_next <= inc_id(id); + else + id_next <= id; +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + id <= 'h0; + end else begin + id <= id_next; + end +end + +always @(posedge clk) begin + pending_burst <= id_next != request_id; +end + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_mm.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_mm.v new file mode 100644 index 000000000..93f351e3f --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_mm.v @@ -0,0 +1,232 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_dest_mm_axi ( + input m_axi_aclk, + input m_axi_aresetn, + + input req_valid, + output req_ready, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes, + + input enable, + output enabled, + input pause, + input sync_id, + output sync_id_ret, + + output response_valid, + input response_ready, + output [1:0] response_resp, + output response_resp_eot, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + + output [ID_WIDTH-1:0] data_id, + output [ID_WIDTH-1:0] address_id, + input data_eot, + input address_eot, + input response_eot, + + input fifo_valid, + output fifo_ready, + input [DMA_DATA_WIDTH-1:0] fifo_data, + + // Write address + input m_axi_awready, + output m_axi_awvalid, + output [31:0] m_axi_awaddr, + output [ 7:0] m_axi_awlen, + output [ 2:0] m_axi_awsize, + output [ 1:0] m_axi_awburst, + output [ 2:0] m_axi_awprot, + output [ 3:0] m_axi_awcache, + + // Write data + output [DMA_DATA_WIDTH-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb, + input m_axi_wready, + output m_axi_wvalid, + output m_axi_wlast, + + // Write response + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready +); + +parameter ID_WIDTH = 3; +parameter DMA_DATA_WIDTH = 64; +parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8); +parameter BEATS_PER_BURST_WIDTH = 4; + +reg [(DMA_DATA_WIDTH/8)-1:0] wstrb; + +wire address_req_valid; +wire address_req_ready; +wire data_req_valid; +wire data_req_ready; + +wire address_enabled; +wire data_enabled; +assign sync_id_ret = sync_id; + +wire _fifo_ready; +assign fifo_ready = _fifo_ready | ~enabled; + +splitter #( + .NUM_M(2) +) i_req_splitter ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + .s_valid(req_valid), + .s_ready(req_ready), + .m_valid({ + address_req_valid, + data_req_valid + }), + .m_ready({ + address_req_ready, + data_req_ready + }) +); + +dmac_address_generator #( + .ID_WIDTH(ID_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH) +) i_addr_gen ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + + .enable(enable), + .enabled(address_enabled), + .pause(pause), + + .id(address_id), + .request_id(request_id), + .sync_id(sync_id), + + .req_valid(address_req_valid), + .req_ready(address_req_ready), + .req_address(req_address), + .req_last_burst_length(req_last_burst_length), + + .eot(address_eot), + + .addr_ready(m_axi_awready), + .addr_valid(m_axi_awvalid), + .addr(m_axi_awaddr), + .len(m_axi_awlen), + .size(m_axi_awsize), + .burst(m_axi_awburst), + .prot(m_axi_awprot), + .cache(m_axi_awcache) +); + +dmac_data_mover # ( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) +) i_data_mover ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + + .enable(address_enabled), + .enabled(data_enabled), + + .xfer_req(), + + .request_id(address_id), + .response_id(data_id), + .sync_id(sync_id), + .eot(data_eot), + + .req_valid(data_req_valid), + .req_ready(data_req_ready), + .req_last_burst_length(req_last_burst_length), + + .s_axi_valid(fifo_valid), + .s_axi_ready(_fifo_ready), + .s_axi_data(fifo_data), + .m_axi_valid(m_axi_wvalid), + .m_axi_ready(m_axi_wready), + .m_axi_data(m_axi_wdata), + .m_axi_last(m_axi_wlast) +); + +always @(*) +begin + if (data_eot & m_axi_wlast) begin + wstrb <= (1 << (req_last_beat_bytes + 1)) - 1; + end else begin + wstrb <= {(DMA_DATA_WIDTH/8){1'b1}}; + end +end + +assign m_axi_wstrb = wstrb; + +dmac_response_handler #( + .ID_WIDTH(ID_WIDTH) +) i_response_handler ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + .bvalid(m_axi_bvalid), + .bready(m_axi_bready), + .bresp(m_axi_bresp), + + .enable(data_enabled), + .enabled(enabled), + + .id(response_id), + .request_id(data_id), + .sync_id(sync_id), + + .eot(response_eot), + + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_resp(response_resp), + .resp_eot(response_resp_eot) +); + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_stream.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_stream.v new file mode 100644 index 000000000..3b3da3397 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_axi_stream.v @@ -0,0 +1,154 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_dest_axi_stream ( + input s_axis_aclk, + input s_axis_aresetn, + + input enable, + output enabled, + input sync_id, + output sync_id_ret, + output xfer_req, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] data_id, + input data_eot, + input response_eot, + + input m_axis_ready, + output m_axis_valid, + output [S_AXIS_DATA_WIDTH-1:0] m_axis_data, + output m_axis_last, + + output fifo_ready, + input fifo_valid, + input [S_AXIS_DATA_WIDTH-1:0] fifo_data, + + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_xlast, + + output response_valid, + input response_ready, + output response_resp_eot, + output [1:0] response_resp +); + +parameter ID_WIDTH = 3; +parameter S_AXIS_DATA_WIDTH = 64; +parameter BEATS_PER_BURST_WIDTH = 4; + +reg req_xlast_d = 1'b0; + +assign sync_id_ret = sync_id; +wire data_enabled; +wire _fifo_ready; +wire m_axis_last_s; + +// We are not allowed to just de-assert valid, but if the streaming target does +// not accept any samples anymore we'd lock up the DMA core. So retain the last +// beat when disabled until it is accepted. But if in the meantime the DMA core +// is re-enabled and new data becomes available overwrite the old. + +always @(posedge s_axis_aclk) begin + if(req_ready == 1'b1) begin + req_xlast_d <= req_xlast; + end +end + +assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0; + +dmac_data_mover # ( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(S_AXIS_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .DISABLE_WAIT_FOR_ID(0), + .LAST(1) +) i_data_mover ( + .clk(s_axis_aclk), + .resetn(s_axis_aresetn), + + .enable(enable), + .enabled(data_enabled), + .sync_id(sync_id), + .xfer_req(xfer_req), + + .request_id(request_id), + .response_id(data_id), + .eot(data_eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), + + .m_axi_ready(m_axis_ready), + .m_axi_valid(m_axis_valid), + .m_axi_data(m_axis_data), + .m_axi_last(m_axis_last_s), + .s_axi_ready(_fifo_ready), + .s_axi_valid(fifo_valid), + .s_axi_data(fifo_data) +); + +dmac_response_generator # ( + .ID_WIDTH(ID_WIDTH) +) i_response_generator ( + .clk(s_axis_aclk), + .resetn(s_axis_aresetn), + + .enable(data_enabled), + .enabled(enabled), + .sync_id(sync_id), + + .request_id(data_id), + .response_id(response_id), + + .eot(response_eot), + + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_eot(response_resp_eot), + .resp_resp(response_resp) +); + +assign fifo_ready = _fifo_ready | ~enabled; + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_fifo_inf.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_fifo_inf.v new file mode 100644 index 000000000..fccac5d7a --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/dest_fifo_inf.v @@ -0,0 +1,154 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_dest_fifo_inf ( + input clk, + input resetn, + + input enable, + output enabled, + input sync_id, + output sync_id_ret, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] data_id, + input data_eot, + input response_eot, + + input en, + output [DATA_WIDTH-1:0] dout, + output valid, + output underflow, + + output xfer_req, + + output fifo_ready, + input fifo_valid, + input [DATA_WIDTH-1:0] fifo_data, + + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + + output response_valid, + input response_ready, + output response_resp_eot, + output [1:0] response_resp +); + +parameter ID_WIDTH = 3; +parameter DATA_WIDTH = 64; +parameter BEATS_PER_BURST_WIDTH = 4; + +assign sync_id_ret = sync_id; +wire data_enabled; + +wire _fifo_ready; +assign fifo_ready = _fifo_ready | ~enabled; + +reg en_d1; +wire data_ready; +wire data_valid; + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + en_d1 <= 1'b0; + end else begin + en_d1 <= en; + end +end + +assign underflow = en_d1 & (~data_valid | ~enable); +assign data_ready = en_d1 & (data_valid | ~enable); +assign valid = en_d1 & data_valid & enable; + +dmac_data_mover # ( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .DISABLE_WAIT_FOR_ID(0) +) i_data_mover ( + .clk(clk), + .resetn(resetn), + + .enable(enable), + .enabled(data_enabled), + .sync_id(sync_id), + .xfer_req(xfer_req), + + .request_id(request_id), + .response_id(data_id), + .eot(data_eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), + + .s_axi_ready(_fifo_ready), + .s_axi_valid(fifo_valid), + .s_axi_data(fifo_data), + .m_axi_ready(data_ready), + .m_axi_valid(data_valid), + .m_axi_data(dout), + .m_axi_last() +); + +dmac_response_generator # ( + .ID_WIDTH(ID_WIDTH) +) i_response_generator ( + .clk(clk), + .resetn(resetn), + + .enable(data_enabled), + .enabled(enabled), + .sync_id(sync_id), + + .request_id(data_id), + .response_id(response_id), + + .eot(response_eot), + + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_eot(response_resp_eot), + .resp_resp(response_resp) +); + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/gui/axi_dmac_v1_0.gtcl b/fpga/usrp3/lib/vivado_ipi/axi_dmac/gui/axi_dmac_v1_0.gtcl new file mode 100644 index 000000000..f932a6695 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/gui/axi_dmac_v1_0.gtcl @@ -0,0 +1,4 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_SYNC_TRANSFER_START_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA_TYPE_SRC != 0} +proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_SRC_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA_TYPE_SRC == 0} +proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_DEST_ENABLEMENT {DMA_TYPE_DEST } {expr $DMA_TYPE_DEST == 0} diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/inc_id.h b/fpga/usrp3/lib/vivado_ipi/axi_dmac/inc_id.h new file mode 100644 index 000000000..0aaebde0d --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/inc_id.h @@ -0,0 +1,67 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +function [ID_WIDTH-1:0] g2b; + input [ID_WIDTH-1:0] g; + reg [ID_WIDTH-1:0] b; + integer i; + begin + b[ID_WIDTH-1] = g[ID_WIDTH-1]; + for (i = ID_WIDTH - 2; i >= 0; i = i - 1) + b[i] = b[i + 1] ^ g[i]; + g2b = b; + end +endfunction + +function [ID_WIDTH-1:0] b2g; + input [ID_WIDTH-1:0] b; + reg [ID_WIDTH-1:0] g; + integer i; + begin + g[ID_WIDTH-1] = b[ID_WIDTH-1]; + for (i = ID_WIDTH - 2; i >= 0; i = i -1) + g[i] = b[i + 1] ^ b[i]; + b2g = g; + end +endfunction + +function [ID_WIDTH:0] inc_id; +input [ID_WIDTH:0] id; +begin + inc_id = b2g(g2b(id) + 1); +end +endfunction diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_arb.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_arb.v new file mode 100644 index 000000000..706d2cedc --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_arb.v @@ -0,0 +1,1115 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_request_arb ( + input req_aclk, + input req_aresetn, + + input req_valid, + output req_ready, + input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_LENGTH_WIDTH-1:0] req_length, + input req_xlast, + input req_sync_transfer_start, + + output reg eot, + + input enable, + input pause, + + // Master AXI interface + input m_dest_axi_aclk, + input m_dest_axi_aresetn, + input m_src_axi_aclk, + input m_src_axi_aresetn, + + // Write address + output [31:0] m_axi_awaddr, + output [ 7:0] m_axi_awlen, + output [ 2:0] m_axi_awsize, + output [ 1:0] m_axi_awburst, + output [ 2:0] m_axi_awprot, + output [ 3:0] m_axi_awcache, + output m_axi_awvalid, + input m_axi_awready, + + // Write data + output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb, + input m_axi_wready, + output m_axi_wvalid, + output m_axi_wlast, + + // Write response + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready, + + // Read address + input m_axi_arready, + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [ 7:0] m_axi_arlen, + output [ 2:0] m_axi_arsize, + output [ 1:0] m_axi_arburst, + output [ 2:0] m_axi_arprot, + output [ 3:0] m_axi_arcache, + + // Read data and response + input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata, + output m_axi_rready, + input m_axi_rvalid, + input [ 1:0] m_axi_rresp, + + // Slave streaming AXI interface + input s_axis_aclk, + output s_axis_ready, + input s_axis_valid, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input [0:0] s_axis_user, + output s_axis_xfer_req, + + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_ready, + output m_axis_valid, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + output m_axis_last, + output m_axis_xfer_req, + + // Input FIFO interface + input fifo_wr_clk, + input fifo_wr_en, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + output fifo_wr_overflow, + input fifo_wr_sync, + output fifo_wr_xfer_req, + + // Input FIFO interface + input fifo_rd_clk, + input fifo_rd_en, + output fifo_rd_valid, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output fifo_rd_underflow, + output fifo_rd_xfer_req, + + output [ID_WIDTH-1:0] dbg_dest_request_id, + output [ID_WIDTH-1:0] dbg_dest_address_id, + output [ID_WIDTH-1:0] dbg_dest_data_id, + output [ID_WIDTH-1:0] dbg_dest_response_id, + output [ID_WIDTH-1:0] dbg_src_request_id, + output [ID_WIDTH-1:0] dbg_src_address_id, + output [ID_WIDTH-1:0] dbg_src_data_id, + output [ID_WIDTH-1:0] dbg_src_response_id, + output [7:0] dbg_status +); + +parameter DMA_DATA_WIDTH_SRC = 64; +parameter DMA_DATA_WIDTH_DEST = 64; +parameter DMA_LENGTH_WIDTH = 24; + +parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8); +parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8); + +parameter DMA_TYPE_DEST = DMA_TYPE_MM_AXI; +parameter DMA_TYPE_SRC = DMA_TYPE_FIFO; + +parameter ASYNC_CLK_REQ_SRC = 1; +parameter ASYNC_CLK_SRC_DEST = 1; +parameter ASYNC_CLK_DEST_REQ = 1; + +parameter AXI_SLICE_DEST = 0; +parameter AXI_SLICE_SRC = 0; + +parameter MAX_BYTES_PER_BURST = 128; +parameter FIFO_SIZE = 4; + +parameter ID_WIDTH = $clog2(FIFO_SIZE*2); + +localparam DMA_TYPE_MM_AXI = 0; +localparam DMA_TYPE_STREAM_AXI = 1; +localparam DMA_TYPE_FIFO = 2; + +localparam DMA_ADDRESS_WIDTH_DEST = 32 - BYTES_PER_BEAT_WIDTH_DEST; +localparam DMA_ADDRESS_WIDTH_SRC = 32 - BYTES_PER_BEAT_WIDTH_SRC; + +localparam DMA_DATA_WIDTH = DMA_DATA_WIDTH_SRC < DMA_DATA_WIDTH_DEST ? + DMA_DATA_WIDTH_DEST : DMA_DATA_WIDTH_SRC; + + + +// Bytes per burst is the same for both dest and src, but bytes per beat may +// differ, so beats per burst may also differ + +parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST); +localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC; +localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST; + +localparam BURSTS_PER_TRANSFER_WIDTH = DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH; + +reg [0:2**ID_WIDTH-1] eot_mem; +wire request_eot; + +wire [ID_WIDTH-1:0] request_id; +wire [ID_WIDTH-1:0] response_id; + +wire enabled_src; +wire enabled_dest; +wire sync_id; +wire sync_id_ret_dest; +wire sync_id_ret_src; + +wire dest_enable; +wire dest_enabled; +wire dest_pause; +wire dest_sync_id; +wire dest_sync_id_ret; +wire src_enable; +wire src_enabled; +wire src_pause; +wire src_sync_id; +wire src_sync_id_ret; + +wire req_dest_valid; +wire req_dest_ready; +wire req_dest_empty; +wire req_src_valid; +wire req_src_ready; +wire req_src_empty; + +wire dest_clk; +wire dest_resetn; +wire dest_req_valid; +wire dest_req_ready; +wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_address; +wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_req_last_burst_length; +wire [BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes; +wire dest_req_xlast; + +wire dest_response_valid; +wire dest_response_ready; +wire dest_response_empty; +wire [1:0] dest_response_resp; +wire dest_response_resp_eot; + +wire [ID_WIDTH-1:0] dest_request_id; +wire [ID_WIDTH-1:0] dest_response_id; + +wire dest_valid; +wire dest_ready; +wire [DMA_DATA_WIDTH_DEST-1:0] dest_data; +wire dest_fifo_repacked_valid; +wire dest_fifo_repacked_ready; +wire [DMA_DATA_WIDTH_DEST-1:0] dest_fifo_repacked_data; +wire dest_fifo_valid; +wire dest_fifo_ready; +wire [DMA_DATA_WIDTH-1:0] dest_fifo_data; + +wire src_clk; +wire src_resetn; +wire src_req_valid; +wire src_req_ready; +wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_address; +wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length; +wire src_req_sync_transfer_start; + +wire src_response_valid; +wire src_response_ready; +wire src_response_empty; +wire [1:0] src_response_resp; + +wire [ID_WIDTH-1:0] src_request_id; +wire [ID_WIDTH-1:0] src_response_id; + +wire src_valid; +wire src_ready; +wire [DMA_DATA_WIDTH_SRC-1:0] src_data; +wire src_fifo_valid; +wire src_fifo_ready; +wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data; +wire src_fifo_repacked_valid; +wire src_fifo_repacked_ready; +wire [DMA_DATA_WIDTH-1:0] src_fifo_repacked_data; +wire src_fifo_empty; + +wire fifo_empty; + +wire response_dest_valid; +wire response_dest_ready = 1'b1; +wire [1:0] response_dest_resp; +wire response_dest_resp_eot; + +/* Unused for now +wire response_src_valid; +wire response_src_ready = 1'b1; +wire [1:0] response_src_resp; +*/ + +assign dbg_dest_request_id = dest_request_id; +assign dbg_dest_response_id = dest_response_id; +assign dbg_src_request_id = src_request_id; +assign dbg_src_response_id = src_response_id; + +assign sync_id = ~enabled_dest && ~enabled_src && request_id != response_id; + +reg enabled; +reg do_enable; + +// Enable src and dest if we are in sync +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + do_enable <= 1'b0; + end else begin + if (enable) begin + // First make sure we are fully disabled + if (~sync_id_ret_dest && ~sync_id_ret_src && + response_id == request_id && ~enabled_dest && ~enabled_src && + req_dest_empty && req_src_empty && fifo_empty) + do_enable <= 1'b1; + end else begin + do_enable <= 1'b0; + end + end +end + +// Flag enabled once both src and dest are enabled +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (do_enable == 1'b0) + enabled <= 1'b0; + else if (enabled_dest && enabled_src) + enabled <= 1'b1; + end +end + +assign dbg_status = {do_enable, enabled, enabled_dest, enabled_src, fifo_empty, + sync_id, sync_id_ret_dest, sync_id_ret_src}; + +always @(posedge req_aclk) +begin + eot_mem[request_id] <= request_eot; +end + +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + eot <= 1'b0; + end else begin + eot <= response_dest_valid & response_dest_ready & response_dest_resp_eot; + end +end + +generate if (ASYNC_CLK_REQ_SRC) begin + +wire src_async_resetn_source; + +if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin +assign src_async_resetn_source = m_src_axi_aresetn; +end else begin +assign src_async_resetn_source = req_aresetn; +end + +reg [2:0] src_reset_shift = 3'b111; +assign src_resetn = ~src_reset_shift[2]; + +always @(negedge src_async_resetn_source or posedge src_clk) begin + if (src_async_resetn_source == 1'b0) + src_reset_shift <= 3'b111; + else + src_reset_shift <= {src_reset_shift[1:0], 1'b0}; +end + +end else begin +assign src_resetn = req_aresetn; +end endgenerate + +generate if (ASYNC_CLK_DEST_REQ) begin +wire dest_async_resetn_source; + +if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin +assign dest_async_resetn_source = m_dest_axi_aresetn; +end else begin +assign dest_async_resetn_source = req_aresetn; +end + +reg [2:0] dest_reset_shift = 3'b111; +assign dest_resetn = ~dest_reset_shift[2]; + +always @(negedge dest_async_resetn_source or posedge dest_clk) begin + if (dest_async_resetn_source == 1'b0) + dest_reset_shift <= 3'b111; + else + dest_reset_shift <= {dest_reset_shift[1:0], 1'b0}; +end + +end else begin +assign dest_resetn = req_aresetn; +end endgenerate + +generate if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin + +assign dest_clk = m_dest_axi_aclk; + +wire [ID_WIDTH-1:0] dest_data_id; +wire [ID_WIDTH-1:0] dest_address_id; +wire dest_address_eot = eot_mem[dest_address_id]; +wire dest_data_eot = eot_mem[dest_data_id]; +wire dest_response_eot = eot_mem[dest_response_id]; + +assign dbg_dest_address_id = dest_address_id; +assign dbg_dest_data_id = dest_data_id; + +dmac_dest_mm_axi #( + .ID_WIDTH(ID_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST) +) i_dest_dma_mm ( + .m_axi_aclk(m_dest_axi_aclk), + .m_axi_aresetn(dest_resetn), + + .enable(dest_enable), + .enabled(dest_enabled), + .pause(dest_pause), + + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + .req_address(dest_req_address), + .req_last_burst_length(dest_req_last_burst_length), + .req_last_beat_bytes(dest_req_last_beat_bytes), + + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), + + .request_id(dest_request_id), + .response_id(dest_response_id), + .sync_id(dest_sync_id), + .sync_id_ret(dest_sync_id_ret), + + .data_id(dest_data_id), + .address_id(dest_address_id), + + .address_eot(dest_address_eot), + .data_eot(dest_data_eot), + .response_eot(dest_response_eot), + + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), + + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awprot(m_axi_awprot), + .m_axi_awcache(m_axi_awcache), + .m_axi_wready(m_axi_wready), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), + + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bresp(m_axi_bresp), + .m_axi_bready(m_axi_bready) +); + +end else begin + +assign m_axi_awvalid = 1'b0; +assign m_axi_awaddr = 'h00; +assign m_axi_awlen = 'h00; +assign m_axi_awsize = 'h00; +assign m_axi_awburst = 'h00; +assign m_axi_awprot = 'h00; +assign m_axi_awcache = 'h00; + +assign m_axi_wvalid = 1'b0; +assign m_axi_wdata = 'h00; +assign m_axi_wstrb = 'h00; +assign m_axi_wlast = 1'b0; + +assign m_axi_bready = 1'b0; + +end + +if (DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin + +assign dest_clk = m_axis_aclk; + +wire [ID_WIDTH-1:0] data_id; + +wire data_eot = eot_mem[data_id]; +wire response_eot = eot_mem[dest_response_id]; + +assign dbg_dest_address_id = 'h00; +assign dbg_dest_data_id = data_id; + +dmac_dest_axi_stream #( + .ID_WIDTH(ID_WIDTH), + .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) +) i_dest_dma_stream ( + .s_axis_aclk(m_axis_aclk), + .s_axis_aresetn(dest_resetn), + + .enable(dest_enable), + .enabled(dest_enabled), + + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + .req_last_burst_length(dest_req_last_burst_length), + .req_xlast(dest_req_xlast), + + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), + + .request_id(dest_request_id), + .response_id(dest_response_id), + .data_id(data_id), + .sync_id(dest_sync_id), + .sync_id_ret(dest_sync_id_ret), + .xfer_req(m_axis_xfer_req), + + .data_eot(data_eot), + .response_eot(response_eot), + + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), + + .m_axis_valid(m_axis_valid), + .m_axis_ready(m_axis_ready), + .m_axis_data(m_axis_data), + .m_axis_last(m_axis_last) +); + +end else begin + +assign m_axis_valid = 1'b0; +assign m_axis_last = 1'b0; +assign m_axis_xfer_req = 1'b0; +assign m_axis_data = 'h00; + +end + +if (DMA_TYPE_DEST == DMA_TYPE_FIFO) begin + +assign dest_clk = fifo_rd_clk; + +wire [ID_WIDTH-1:0] data_id; + +wire data_eot = eot_mem[data_id]; +wire response_eot = eot_mem[dest_response_id]; + +assign dbg_dest_address_id = 'h00; +assign dbg_dest_data_id = data_id; + +dmac_dest_fifo_inf #( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) +) i_dest_dma_fifo ( + .clk(fifo_rd_clk), + .resetn(dest_resetn), + + .enable(dest_enable), + .enabled(dest_enabled), + + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + .req_last_burst_length(dest_req_last_burst_length), + + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), + + .request_id(dest_request_id), + .response_id(dest_response_id), + .data_id(data_id), + .sync_id(dest_sync_id), + .sync_id_ret(dest_sync_id_ret), + + .data_eot(data_eot), + .response_eot(response_eot), + + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), + + .en(fifo_rd_en), + .valid(fifo_rd_valid), + .dout(fifo_rd_dout), + .underflow(fifo_rd_underflow), + .xfer_req(fifo_rd_xfer_req) +); + +end else begin + +assign fifo_rd_valid = 1'b0; +assign fifo_rd_dout = 'h0; +assign fifo_rd_underflow = 1'b0; +assign fifo_rd_xfer_req = 1'b0; + +end endgenerate + +generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin + +assign src_clk = m_src_axi_aclk; + +wire [ID_WIDTH-1:0] src_data_id; +wire [ID_WIDTH-1:0] src_address_id; +wire src_address_eot = eot_mem[src_address_id]; +wire src_data_eot = eot_mem[src_data_id]; + +assign dbg_src_address_id = src_address_id; +assign dbg_src_data_id = src_data_id; + +dmac_src_mm_axi #( + .ID_WIDTH(ID_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC) +) i_src_dma_mm ( + .m_axi_aclk(m_src_axi_aclk), + .m_axi_aresetn(src_resetn), + + .pause(src_pause), + .enable(src_enable), + .enabled(src_enabled), + .sync_id(src_sync_id), + .sync_id_ret(src_sync_id_ret), + + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_address(src_req_address), + .req_last_burst_length(src_req_last_burst_length), + + .response_valid(src_response_valid), + .response_ready(src_response_ready), + .response_resp(src_response_resp), + + .request_id(src_request_id), + .response_id(src_response_id), + .address_id(src_address_id), + .data_id(src_data_id), + + .address_eot(src_address_eot), + .data_eot(src_data_eot), + + .fifo_valid(src_valid), + .fifo_ready(src_ready), + .fifo_data(src_data), + + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(m_axi_arlen), + .m_axi_arsize(m_axi_arsize), + .m_axi_arburst(m_axi_arburst), + .m_axi_arprot(m_axi_arprot), + .m_axi_arcache(m_axi_arcache), + + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp) +); + +end else begin + +assign m_axi_arvalid = 1'b0; +assign m_axi_araddr = 'h00; +assign m_axi_arlen = 'h00; +assign m_axi_arsize = 'h00; +assign m_axi_arburst = 'h00; +assign m_axi_arcache = 'h00; +assign m_axi_arprot = 'h00; +assign m_axi_rready = 1'b0; + +end + +if (DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin + +assign src_clk = s_axis_aclk; + +wire src_eot = eot_mem[src_response_id]; + +assign dbg_src_address_id = 'h00; +assign dbg_src_data_id = 'h00; + +/* TODO */ +assign src_response_valid = 1'b0; +assign src_response_resp = 2'b0; + +dmac_src_axi_stream #( + .ID_WIDTH(ID_WIDTH), + .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) +) i_src_dma_stream ( + .s_axis_aclk(s_axis_aclk), + .s_axis_aresetn(src_resetn), + + .enable(src_enable), + .enabled(src_enabled), + .sync_id(src_sync_id), + .sync_id_ret(src_sync_id_ret), + + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_last_burst_length(src_req_last_burst_length), + .req_sync_transfer_start(src_req_sync_transfer_start), + + .request_id(src_request_id), + .response_id(src_response_id), + + .eot(src_eot), + + .fifo_valid(src_valid), + .fifo_ready(src_ready), + .fifo_data(src_data), + + .s_axis_valid(s_axis_valid), + .s_axis_ready(s_axis_ready), + .s_axis_data(s_axis_data), + .s_axis_user(s_axis_user), + .s_axis_xfer_req(s_axis_xfer_req) +); + +end else begin + +assign s_axis_ready = 1'b0; +assign s_axis_xfer_req = 1'b0; + +end + +if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin + +assign src_clk = fifo_wr_clk; + +wire src_eot = eot_mem[src_response_id]; + +assign dbg_src_address_id = 'h00; +assign dbg_src_data_id = 'h00; + +/* TODO */ +assign src_response_valid = 1'b0; +assign src_response_resp = 2'b0; + +dmac_src_fifo_inf #( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) +) i_src_dma_fifo ( + .clk(fifo_wr_clk), + .resetn(src_resetn), + + .enable(src_enable), + .enabled(src_enabled), + .sync_id(src_sync_id), + .sync_id_ret(src_sync_id_ret), + + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_last_burst_length(src_req_last_burst_length), + .req_sync_transfer_start(src_req_sync_transfer_start), + + .request_id(src_request_id), + .response_id(src_response_id), + + .eot(src_eot), + + .fifo_valid(src_valid), + .fifo_ready(src_ready), + .fifo_data(src_data), + + .en(fifo_wr_en), + .din(fifo_wr_din), + .overflow(fifo_wr_overflow), + .sync(fifo_wr_sync), + .xfer_req(fifo_wr_xfer_req) +); + +end else begin + +assign fifo_wr_overflow = 1'b0; +assign fifo_wr_xfer_req = 1'b0; + +end endgenerate + +sync_bits #( + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) +) i_sync_src_request_id ( + .out_clk(src_clk), + .out_resetn(src_resetn), + .in(request_id), + .out(src_request_id) +); + +sync_bits #( + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST) +) i_sync_dest_request_id ( + .out_clk(dest_clk), + .out_resetn(dest_resetn), + .in(src_response_id), + .out(dest_request_id) +); + +sync_bits #( + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) +) i_sync_req_response_id ( + .out_clk(req_aclk), + .out_resetn(req_aresetn), + .in(dest_response_id), + .out(response_id) +); + +axi_register_slice #( + .DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .FORWARD_REGISTERED(AXI_SLICE_SRC), + .BACKWARD_REGISTERED(AXI_SLICE_SRC) +) i_src_slice ( + .clk(src_clk), + .resetn(src_resetn), + .s_axi_valid(src_valid), + .s_axi_ready(src_ready), + .s_axi_data(src_data), + .m_axi_valid(src_fifo_valid), + .m_axi_ready(src_fifo_ready), + .m_axi_data(src_fifo_data) +); + +util_axis_resize #( + .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .MASTER_DATA_WIDTH(DMA_DATA_WIDTH) +) i_src_repack ( + .clk(src_clk), + .resetn(src_resetn & src_enable), + .s_valid(src_fifo_valid), + .s_ready(src_fifo_ready), + .s_data(src_fifo_data), + .m_valid(src_fifo_repacked_valid), + .m_ready(src_fifo_repacked_ready), + .m_data(src_fifo_repacked_data) +); + +util_axis_fifo #( + .DATA_WIDTH(DMA_DATA_WIDTH), + .ADDRESS_WIDTH($clog2(MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * FIFO_SIZE)), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST) +) i_fifo ( + .s_axis_aclk(src_clk), + .s_axis_aresetn(src_resetn), + .s_axis_valid(src_fifo_repacked_valid), + .s_axis_ready(src_fifo_repacked_ready), + .s_axis_data(src_fifo_repacked_data), + .s_axis_empty(src_fifo_empty), + .s_axis_room(), + + .m_axis_aclk(dest_clk), + .m_axis_aresetn(dest_resetn), + .m_axis_valid(dest_fifo_valid), + .m_axis_ready(dest_fifo_ready), + .m_axis_data(dest_fifo_data), + .m_axis_level() +); + +util_axis_resize #( + .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH), + .MASTER_DATA_WIDTH(DMA_DATA_WIDTH_DEST) +) i_dest_repack ( + .clk(dest_clk), + .resetn(dest_resetn & dest_enable), + .s_valid(dest_fifo_valid), + .s_ready(dest_fifo_ready), + .s_data(dest_fifo_data), + .m_valid(dest_fifo_repacked_valid), + .m_ready(dest_fifo_repacked_ready), + .m_data(dest_fifo_repacked_data) +); + +wire _dest_valid; +wire _dest_ready; +wire [DMA_DATA_WIDTH_DEST-1:0] _dest_data; + +axi_register_slice #( + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .FORWARD_REGISTERED(AXI_SLICE_DEST) +) i_dest_slice2 ( + .clk(dest_clk), + .resetn(dest_resetn), + .s_axi_valid(dest_fifo_repacked_valid), + .s_axi_ready(dest_fifo_repacked_ready), + .s_axi_data(dest_fifo_repacked_data), + .m_axi_valid(_dest_valid), + .m_axi_ready(_dest_ready), + .m_axi_data(_dest_data) +); + +axi_register_slice #( + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .FORWARD_REGISTERED(AXI_SLICE_DEST), + .BACKWARD_REGISTERED(AXI_SLICE_DEST) +) i_dest_slice ( + .clk(dest_clk), + .resetn(dest_resetn), + .s_axi_valid(_dest_valid), + .s_axi_ready(_dest_ready), + .s_axi_data(_dest_data), + .m_axi_valid(dest_valid), + .m_axi_ready(dest_ready), + .m_axi_data(dest_data) +); + + +// We do not accept any requests until all components are enabled +reg _req_valid = 1'b0; +wire _req_ready; + +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + _req_valid <= 1'b0; + end else begin + if (_req_valid == 1'b1 && _req_ready == 1'b1) begin + _req_valid <= 1'b0; + end else if (req_valid == 1'b1 && enabled == 1'b1) begin + _req_valid <= 1'b1; + end + end +end + +assign req_ready = _req_ready & _req_valid & enable; + +splitter #( + .NUM_M(3) +) i_req_splitter ( + .clk(req_aclk), + .resetn(req_aresetn), + .s_valid(_req_valid), + .s_ready(_req_ready), + .m_valid({ + req_gen_valid, + req_dest_valid, + req_src_valid + }), + .m_ready({ + req_gen_ready, + req_dest_ready, + req_src_ready + }) +); + +util_axis_fifo #( + .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) +) i_dest_req_fifo ( + .s_axis_aclk(req_aclk), + .s_axis_aresetn(req_aresetn), + .s_axis_valid(req_dest_valid), + .s_axis_ready(req_dest_ready), + .s_axis_empty(req_dest_empty), + .s_axis_data({ + req_dest_address, + req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST], + req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0], + req_xlast + }), + .s_axis_room(), + + .m_axis_aclk(dest_clk), + .m_axis_aresetn(dest_resetn), + .m_axis_valid(dest_req_valid), + .m_axis_ready(dest_req_ready), + .m_axis_data({ + dest_req_address, + dest_req_last_burst_length, + dest_req_last_beat_bytes, + dest_req_xlast + }), + .m_axis_level() +); + +util_axis_fifo #( + .DATA_WIDTH(DMA_ADDRESS_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) +) i_src_req_fifo ( + .s_axis_aclk(req_aclk), + .s_axis_aresetn(req_aresetn), + .s_axis_valid(req_src_valid), + .s_axis_ready(req_src_ready), + .s_axis_empty(req_src_empty), + .s_axis_data({ + req_src_address, + req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC], + req_sync_transfer_start + }), + .s_axis_room(), + + .m_axis_aclk(src_clk), + .m_axis_aresetn(src_resetn), + .m_axis_valid(src_req_valid), + .m_axis_ready(src_req_ready), + .m_axis_data({ + src_req_address, + src_req_last_burst_length, + src_req_sync_transfer_start + }), + .m_axis_level() +); + +util_axis_fifo #( + .DATA_WIDTH(1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) +) i_dest_response_fifo ( + .s_axis_aclk(dest_clk), + .s_axis_aresetn(dest_resetn), + .s_axis_valid(dest_response_valid), + .s_axis_ready(dest_response_ready), + .s_axis_empty(dest_response_empty), + .s_axis_data(dest_response_resp_eot), + .s_axis_room(), + + .m_axis_aclk(req_aclk), + .m_axis_aresetn(req_aresetn), + .m_axis_valid(response_dest_valid), + .m_axis_ready(response_dest_ready), + .m_axis_data(response_dest_resp_eot), + .m_axis_level() +); + +/* Unused for now +util_axis_fifo #( + .DATA_WIDTH(2), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) +) i_src_response_fifo ( + .s_axis_aclk(src_clk), + .s_axis_aresetn(src_resetn), + .s_axis_valid(src_response_valid), + .s_axis_ready(src_response_ready), + .s_axis_empty(src_response_empty), + .s_axis_data(src_response_resp), + .m_axis_aclk(req_aclk), + .m_axis_aresetn(req_aresetn), + .m_axis_valid(response_src_valid), + .m_axis_ready(response_src_ready), + .m_axis_data(response_src_resp) +);*/ +assign src_response_empty = 1'b1; +assign src_response_ready = 1'b1; + +dmac_request_generator #( + .ID_WIDTH(ID_WIDTH), + .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH) +) i_req_gen ( + .req_aclk(req_aclk), + .req_aresetn(req_aresetn), + + .request_id(request_id), + .response_id(response_id), + + .req_valid(req_gen_valid), + .req_ready(req_gen_ready), + .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]), + + .enable(do_enable), + .pause(pause), + + .eot(request_eot) +); + +sync_bits #( + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) +) i_sync_control_dest ( + .out_clk(dest_clk), + .out_resetn(dest_resetn), + .in({do_enable, pause, sync_id}), + .out({dest_enable, dest_pause, dest_sync_id}) +); + +sync_bits #( + .NUM_OF_BITS(2), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) +) i_sync_status_dest ( + .out_clk(req_aclk), + .out_resetn(req_aresetn), + .in({dest_enabled | ~dest_response_empty, dest_sync_id_ret}), + .out({enabled_dest, sync_id_ret_dest}) +); + +sync_bits #( + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) +) i_sync_control_src ( + .out_clk(src_clk), + .out_resetn(src_resetn), + .in({do_enable, pause, sync_id}), + .out({src_enable, src_pause, src_sync_id}) +); + +sync_bits #( + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) +) i_sync_status_src ( + .out_clk(req_aclk), + .out_resetn(req_aresetn), + .in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}), + .out({enabled_src, sync_id_ret_src, fifo_empty}) +); + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_generator.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_generator.v new file mode 100644 index 000000000..d56a5e8c5 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/request_generator.v @@ -0,0 +1,98 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_request_generator ( + input req_aclk, + input req_aresetn, + + output [ID_WIDTH-1:0] request_id, + input [ID_WIDTH-1:0] response_id, + + input req_valid, + output reg req_ready, + input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count, + + input enable, + input pause, + + output eot +); + +parameter ID_WIDTH = 3; +parameter BURSTS_PER_TRANSFER_WIDTH = 17; + +`include "inc_id.h" + +/* + * Here we only need to count the number of bursts, which means we can ignore + * the lower bits of the byte count. The last last burst may not contain the + * maximum number of bytes, but the address_generator and data_mover will take + * care that only the requested ammount of bytes is transfered. + */ + +reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00; +reg [ID_WIDTH-1:0] id; +wire [ID_WIDTH-1:0] id_next = inc_id(id); + +assign eot = burst_count == 'h00; +assign request_id = id; + +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + burst_count <= 'h00; + id <= 'h0; + req_ready <= 1'b1; + end else if (enable == 1'b0) begin + req_ready <= 1'b1; + end else begin + if (req_ready) begin + if (req_valid && enable) begin + burst_count <= req_burst_count; + req_ready <= 1'b0; + end + end else if (response_id != id_next && ~pause) begin + if (eot) + req_ready <= 1'b1; + burst_count <= burst_count - 1'b1; + id <= id_next; + end + end +end + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/resp.h b/fpga/usrp3/lib/vivado_ipi/axi_dmac/resp.h new file mode 100644 index 000000000..a3a738357 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/resp.h @@ -0,0 +1,4 @@ +localparam RESP_OKAY = 2'b00; +localparam RESP_EXOKAY = 2'b01; +localparam RESP_SLVERR = 2'b10; +localparam RESP_DECERR = 2'b11; diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_generator.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_generator.v new file mode 100644 index 000000000..61104d36f --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_generator.v @@ -0,0 +1,90 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_response_generator ( + input clk, + input resetn, + + input enable, + output reg enabled, + + input [ID_WIDTH-1:0] request_id, + output reg [ID_WIDTH-1:0] response_id, + input sync_id, + + input eot, + + output resp_valid, + input resp_ready, + output resp_eot, + output [1:0] resp_resp +); + +parameter ID_WIDTH = 3; + +`include "inc_id.h" +`include "resp.h" + +assign resp_resp = RESP_OKAY; +assign resp_eot = eot; + +assign resp_valid = request_id != response_id && enabled; + +// We have to wait for all responses before we can disable the response handler +always @(posedge clk) begin + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (enable) + enabled <= 1'b1; + else if (request_id == response_id) + enabled <= 1'b0; + end +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + response_id <= 'h0; + end else begin + if ((resp_valid && resp_ready) || + (sync_id && response_id != request_id)) + response_id <= inc_id(response_id); + end +end + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_handler.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_handler.v new file mode 100644 index 000000000..cd64ba7e7 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/response_handler.v @@ -0,0 +1,97 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_response_handler ( + input clk, + input resetn, + + input bvalid, + output bready, + input [1:0] bresp, + + output reg [ID_WIDTH-1:0] id, + input [ID_WIDTH-1:0] request_id, + input sync_id, + + input enable, + output reg enabled, + + input eot, + + output resp_valid, + input resp_ready, + output resp_eot, + output [1:0] resp_resp +); + +parameter ID_WIDTH = 3; + +`include "resp.h" +`include "inc_id.h" + +assign resp_resp = bresp; +assign resp_eot = eot; + +wire active = id != request_id && enabled; + +assign bready = active && resp_ready; +assign resp_valid = active && bvalid; + +// We have to wait for all responses before we can disable the response handler +always @(posedge clk) begin + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (enable) + enabled <= 1'b1; + else if (request_id == id) + enabled <= 1'b0; + end +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + id <= 'h0; + end else begin + if ((bready && bvalid) || + (sync_id && id != request_id)) + id <= inc_id(id); + end +end + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/splitter.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/splitter.v new file mode 100644 index 000000000..4fee19f95 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/splitter.v @@ -0,0 +1,69 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + + +module splitter ( + input clk, + input resetn, + + input s_valid, + output s_ready, + + output [NUM_M-1:0] m_valid, + input [NUM_M-1:0] m_ready +); + +parameter NUM_M = 2; + +reg [NUM_M-1:0] acked; + +assign s_ready = &(m_ready | acked); +assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}}; + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + acked <= {NUM_M{1'b0}}; + end else begin + if (s_valid & s_ready) + acked <= {NUM_M{1'b0}}; + else + acked <= acked | (m_ready & m_valid); + end +end + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_mm.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_mm.v new file mode 100644 index 000000000..c1a06b0d8 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_mm.v @@ -0,0 +1,199 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_src_mm_axi ( + input m_axi_aclk, + input m_axi_aresetn, + + input req_valid, + output req_ready, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + + input enable, + output enabled, + input pause, + input sync_id, + output sync_id_ret, + + output response_valid, + input response_ready, + output [1:0] response_resp, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + + output [ID_WIDTH-1:0] data_id, + output [ID_WIDTH-1:0] address_id, + input data_eot, + input address_eot, + + output fifo_valid, + input fifo_ready, + output [DMA_DATA_WIDTH-1:0] fifo_data, + + // Read address + input m_axi_arready, + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [ 7:0] m_axi_arlen, + output [ 2:0] m_axi_arsize, + output [ 1:0] m_axi_arburst, + output [ 2:0] m_axi_arprot, + output [ 3:0] m_axi_arcache, + + // Read data and response + input [DMA_DATA_WIDTH-1:0] m_axi_rdata, + output m_axi_rready, + input m_axi_rvalid, + input [ 1:0] m_axi_rresp +); + +parameter ID_WIDTH = 3; +parameter DMA_DATA_WIDTH = 64; +parameter BYTES_PER_BEAT_WIDTH = 3; +parameter BEATS_PER_BURST_WIDTH = 4; + +`include "resp.h" + +wire address_enabled; + +wire address_req_valid; +wire address_req_ready; +wire data_req_valid; +wire data_req_ready; + +assign sync_id_ret = sync_id; +assign response_id = data_id; + +assign response_valid = 1'b0; +assign response_resp = RESP_OKAY; + +splitter #( + .NUM_M(2) +) i_req_splitter ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + .s_valid(req_valid), + .s_ready(req_ready), + .m_valid({ + address_req_valid, + data_req_valid + }), + .m_ready({ + address_req_ready, + data_req_ready + }) +); + +dmac_address_generator #( + .ID_WIDTH(ID_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH) +) i_addr_gen ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + + .enable(enable), + .enabled(address_enabled), + .pause(pause), + .sync_id(sync_id), + + .request_id(request_id), + .id(address_id), + + .req_valid(address_req_valid), + .req_ready(address_req_ready), + .req_address(req_address), + .req_last_burst_length(req_last_burst_length), + + .eot(address_eot), + + .addr_ready(m_axi_arready), + .addr_valid(m_axi_arvalid), + .addr(m_axi_araddr), + .len(m_axi_arlen), + .size(m_axi_arsize), + .burst(m_axi_arburst), + .prot(m_axi_arprot), + .cache(m_axi_arcache) +); + +dmac_data_mover # ( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) +) i_data_mover ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + + .enable(address_enabled), + .enabled(enabled), + .sync_id(sync_id), + + .xfer_req(), + + .request_id(address_id), + .response_id(data_id), + .eot(data_eot), + + .req_valid(data_req_valid), + .req_ready(data_req_ready), + .req_last_burst_length(req_last_burst_length), + + .s_axi_valid(m_axi_rvalid), + .s_axi_ready(m_axi_rready), + .s_axi_data(m_axi_rdata), + .m_axi_valid(fifo_valid), + .m_axi_ready(fifo_ready), + .m_axi_data(fifo_data), + .m_axi_last() +); + +reg [1:0] rresp; + +always @(posedge m_axi_aclk) +begin + if (m_axi_rvalid && m_axi_rready) begin + if (m_axi_rresp != 2'b0) + rresp <= m_axi_rresp; + end +end + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_stream.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_stream.v new file mode 100644 index 000000000..a2c41a928 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_axi_stream.v @@ -0,0 +1,123 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_src_axi_stream ( + input s_axis_aclk, + input s_axis_aresetn, + + input enable, + output enabled, + input sync_id, + output sync_id_ret, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input eot, + + output s_axis_ready, + input s_axis_valid, + input [S_AXIS_DATA_WIDTH-1:0] s_axis_data, + input [0:0] s_axis_user, + output s_axis_xfer_req, + + input fifo_ready, + output fifo_valid, + output [S_AXIS_DATA_WIDTH-1:0] fifo_data, + + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_sync_transfer_start +); + +parameter ID_WIDTH = 3; +parameter S_AXIS_DATA_WIDTH = 64; +parameter LENGTH_WIDTH = 24; +parameter BEATS_PER_BURST_WIDTH = 4; + +reg needs_sync = 1'b0; +wire sync = s_axis_user[0]; +wire has_sync = ~needs_sync | sync; +wire sync_valid = s_axis_valid & has_sync; +assign sync_id_ret = sync_id; + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + needs_sync <= 1'b0; + end else begin + if (s_axis_valid && s_axis_ready && sync) begin + needs_sync <= 1'b0; + end else if (req_valid && req_ready) begin + needs_sync <= req_sync_transfer_start; + end + end +end + +dmac_data_mover # ( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(S_AXIS_DATA_WIDTH), + .DISABLE_WAIT_FOR_ID(0), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) +) i_data_mover ( + .clk(s_axis_aclk), + .resetn(s_axis_aresetn), + + .enable(enable), + .enabled(enabled), + .sync_id(sync_id), + + .xfer_req(s_axis_xfer_req), + + .request_id(request_id), + .response_id(response_id), + .eot(eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), + + .s_axi_ready(s_axis_ready), + .s_axi_valid(sync_valid), + .s_axi_data(s_axis_data), + .m_axi_ready(fifo_ready), + .m_axi_valid(fifo_valid), + .m_axi_data(fifo_data) +); + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_fifo_inf.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_fifo_inf.v new file mode 100644 index 000000000..633cc1ab4 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/src_fifo_inf.v @@ -0,0 +1,138 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module dmac_src_fifo_inf ( + input clk, + input resetn, + + input enable, + output enabled, + input sync_id, + output sync_id_ret, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input eot, + + input en, + input [DATA_WIDTH-1:0] din, + output reg overflow, + input sync, + output xfer_req, + + input fifo_ready, + output fifo_valid, + output [DATA_WIDTH-1:0] fifo_data, + + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_sync_transfer_start +); + +parameter ID_WIDTH = 3; +parameter DATA_WIDTH = 64; +parameter BEATS_PER_BURST_WIDTH = 4; + +wire ready; + +reg needs_sync = 1'b0; +wire has_sync = ~needs_sync | sync; +wire sync_valid = en & ready & has_sync; + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + needs_sync <= 1'b0; + end else begin + if (ready && en && sync) begin + needs_sync <= 1'b0; + end else if (req_valid && req_ready) begin + needs_sync <= req_sync_transfer_start; + end + end +end + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + overflow <= 1'b0; + end else begin + if (enable) begin + overflow <= en & ~ready; + end else begin + overflow <= en; + end + end +end + +assign sync_id_ret = sync_id; + +dmac_data_mover # ( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .DISABLE_WAIT_FOR_ID(0), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) +) i_data_mover ( + .clk(clk), + .resetn(resetn), + + .enable(enable), + .enabled(enabled), + .sync_id(sync_id), + + .xfer_req(xfer_req), + + .request_id(request_id), + .response_id(response_id), + .eot(eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), + + .s_axi_ready(ready), + .s_axi_valid(sync_valid), + .s_axi_data(din), + .m_axi_ready(fifo_ready), + .m_axi_valid(fifo_valid), + .m_axi_data(fifo_data), + .m_axi_last() +); + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/sync_bits.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/sync_bits.v new file mode 100644 index 000000000..2530f047b --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/sync_bits.v @@ -0,0 +1,76 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing bit signals from one clock domain to another. + * It uses the standard approach of 2 FF in series. + * Note, that while the module allows to synchronize multiple bits at once it is + * only able to synchronize multi-bit signals where at max one bit changes per + * clock cycle (e.g. a gray counter). + */ +module sync_bits +( + input [NUM_OF_BITS-1:0] in, + input out_resetn, + input out_clk, + output [NUM_OF_BITS-1:0] out +); + +// Number of bits to synchronize +parameter NUM_OF_BITS = 1; +// Whether input and output clocks are asynchronous, if 0 the synchronizer will +// be bypassed and the output signal equals the input signal. +parameter ASYNC_CLK = 1; + +reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0; +reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0; + +always @(posedge out_clk) +begin + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'b0; + cdc_sync_stage2 <= 'b0; + end else begin + cdc_sync_stage1 <= in; + cdc_sync_stage2 <= cdc_sync_stage1; + end +end + +assign out = ASYNC_CLK ? cdc_sync_stage2 : in; + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v new file mode 100644 index 000000000..db62e659a --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_axi ( + + // reset and clocks + + up_rstn, + up_clk, + + // axi4 interface + + up_axi_awvalid, + up_axi_awaddr, + up_axi_awready, + up_axi_wvalid, + up_axi_wdata, + up_axi_wstrb, + up_axi_wready, + up_axi_bvalid, + up_axi_bresp, + up_axi_bready, + up_axi_arvalid, + up_axi_araddr, + up_axi_arready, + up_axi_rvalid, + up_axi_rresp, + up_axi_rdata, + up_axi_rready, + + // pcore interface + + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter ADDRESS_WIDTH = 14; + localparam AW = ADDRESS_WIDTH - 1; + + // reset and clocks + + input up_rstn; + input up_clk; + + // axi4 interface + + input up_axi_awvalid; + input [31:0] up_axi_awaddr; + output up_axi_awready; + input up_axi_wvalid; + input [31:0] up_axi_wdata; + input [ 3:0] up_axi_wstrb; + output up_axi_wready; + output up_axi_bvalid; + output [ 1:0] up_axi_bresp; + input up_axi_bready; + input up_axi_arvalid; + input [31:0] up_axi_araddr; + output up_axi_arready; + output up_axi_rvalid; + output [ 1:0] up_axi_rresp; + output [31:0] up_axi_rdata; + input up_axi_rready; + + // pcore interface + + output up_wreq; + output [AW:0] up_waddr; + output [31:0] up_wdata; + input up_wack; + output up_rreq; + output [AW:0] up_raddr; + input [31:0] up_rdata; + input up_rack; + + // internal registers + + reg up_axi_awready = 'd0; + reg up_axi_wready = 'd0; + reg up_axi_bvalid = 'd0; + reg up_wack_d = 'd0; + reg up_wsel = 'd0; + reg up_wreq = 'd0; + reg [AW:0] up_waddr = 'd0; + reg [31:0] up_wdata = 'd0; + reg [ 4:0] up_wcount = 'd0; + reg up_axi_arready = 'd0; + reg up_axi_rvalid = 'd0; + reg [31:0] up_axi_rdata = 'd0; + reg up_rack_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + reg up_rsel = 'd0; + reg up_rreq = 'd0; + reg [AW:0] up_raddr = 'd0; + reg [ 4:0] up_rcount = 'd0; + + // internal signals + + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; + + // write channel interface + + assign up_axi_bresp = 2'd0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_awready <= 'd0; + up_axi_wready <= 'd0; + up_axi_bvalid <= 'd0; + end else begin + if (up_axi_awready == 1'b1) begin + up_axi_awready <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_awready <= 1'b1; + end + if (up_axi_wready == 1'b1) begin + up_axi_wready <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_wready <= 1'b1; + end + if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin + up_axi_bvalid <= 1'b0; + end else if (up_wack_d == 1'b1) begin + up_axi_bvalid <= 1'b1; + end + end + end + + assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack); + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_wack_d <= 'd0; + up_wsel <= 'd0; + up_wreq <= 'd0; + up_waddr <= 'd0; + up_wdata <= 'd0; + up_wcount <= 'd0; + end else begin + up_wack_d <= up_wack_s; + if (up_wsel == 1'b1) begin + if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin + up_wsel <= 1'b0; + end + up_wreq <= 1'b0; + up_waddr <= up_waddr; + up_wdata <= up_wdata; + end else begin + up_wsel <= up_axi_awvalid & up_axi_wvalid; + up_wreq <= up_axi_awvalid & up_axi_wvalid; + up_waddr <= up_axi_awaddr[AW+2:2]; + up_wdata <= up_axi_wdata; + end + if (up_wack_s == 1'b1) begin + up_wcount <= 5'h00; + end else if (up_wcount[4] == 1'b1) begin + up_wcount <= up_wcount + 1'b1; + end else if (up_wreq == 1'b1) begin + up_wcount <= 5'h10; + end + end + end + + // read channel interface + + assign up_axi_rresp = 2'd0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_arready <= 'd0; + up_axi_rvalid <= 'd0; + up_axi_rdata <= 'd0; + end else begin + if (up_axi_arready == 1'b1) begin + up_axi_arready <= 1'b0; + end else if (up_rack_s == 1'b1) begin + up_axi_arready <= 1'b1; + end + if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin + up_axi_rvalid <= 1'b0; + up_axi_rdata <= 32'd0; + end else if (up_rack_d == 1'b1) begin + up_axi_rvalid <= 1'b1; + up_axi_rdata <= up_rdata_d; + end + end + end + + assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack); + assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rack_d <= 'd0; + up_rdata_d <= 'd0; + up_rsel <= 'd0; + up_rreq <= 'd0; + up_raddr <= 'd0; + up_rcount <= 'd0; + end else begin + up_rack_d <= up_rack_s; + up_rdata_d <= up_rdata_s; + if (up_rsel == 1'b1) begin + if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin + up_rsel <= 1'b0; + end + up_rreq <= 1'b0; + up_raddr <= up_raddr; + end else begin + up_rsel <= up_axi_arvalid; + up_rreq <= up_axi_arvalid; + up_raddr <= up_axi_araddr[AW+2:2]; + end + if (up_rack_s == 1'b1) begin + up_rcount <= 5'h00; + end else if (up_rcount[4] == 1'b1) begin + up_rcount <= up_rcount + 1'b1; + end else if (up_rreq == 1'b1) begin + up_rcount <= 5'h10; + end + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/xgui/axi_dmac_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/axi_dmac/xgui/axi_dmac_v1_0.tcl new file mode 100644 index 000000000..f750a2f9c --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/xgui/axi_dmac_v1_0.tcl @@ -0,0 +1,329 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/axi_dmac_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set DMA_Endpoint_Configuration [ipgui::add_group $IPINST -name "DMA Endpoint Configuration" -parent ${Page_0} -layout horizontal] + #Adding Group + set Source [ipgui::add_group $IPINST -name "Source" -parent ${DMA_Endpoint_Configuration}] + ipgui::add_param $IPINST -name "DMA_TYPE_SRC" -parent ${Source} -widget comboBox + ipgui::add_param $IPINST -name "DMA_AXI_PROTOCOL_SRC" -parent ${Source} -widget comboBox + ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_SRC" -parent ${Source} + ipgui::add_param $IPINST -name "AXI_SLICE_SRC" -parent ${Source} + ipgui::add_param $IPINST -name "SYNC_TRANSFER_START" -parent ${Source} + + #Adding Group + set Destination [ipgui::add_group $IPINST -name "Destination" -parent ${DMA_Endpoint_Configuration}] + ipgui::add_param $IPINST -name "DMA_TYPE_DEST" -parent ${Destination} -widget comboBox + ipgui::add_param $IPINST -name "DMA_AXI_PROTOCOL_DEST" -parent ${Destination} -widget comboBox + ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_DEST" -parent ${Destination} + ipgui::add_param $IPINST -name "AXI_SLICE_DEST" -parent ${Destination} + + + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration} + ipgui::add_param $IPINST -name "DMA_LENGTH_WIDTH" -parent ${General_Configuration} + ipgui::add_param $IPINST -name "FIFO_SIZE" -parent ${General_Configuration} + ipgui::add_param $IPINST -name "MAX_BYTES_PER_BURST" -parent ${General_Configuration} + + #Adding Group + set Features [ipgui::add_group $IPINST -name "Features" -parent ${Page_0}] + ipgui::add_param $IPINST -name "CYCLIC" -parent ${Features} + ipgui::add_param $IPINST -name "DMA_2D_TRANSFER" -parent ${Features} + + #Adding Group + set Clock_Domain_Configuration [ipgui::add_group $IPINST -name "Clock Domain Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "ASYNC_CLK_REQ_SRC" -parent ${Clock_Domain_Configuration} + ipgui::add_param $IPINST -name "ASYNC_CLK_SRC_DEST" -parent ${Clock_Domain_Configuration} + ipgui::add_param $IPINST -name "ASYNC_CLK_DEST_REQ" -parent ${Clock_Domain_Configuration} + + + +} + +proc update_PARAM_VALUE.DMA_AXI_PROTOCOL_DEST { PARAM_VALUE.DMA_AXI_PROTOCOL_DEST PARAM_VALUE.DMA_TYPE_DEST } { + # Procedure called to update DMA_AXI_PROTOCOL_DEST when any of the dependent parameters in the arguments change + + set DMA_AXI_PROTOCOL_DEST ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST} + set DMA_TYPE_DEST ${PARAM_VALUE.DMA_TYPE_DEST} + set values(DMA_TYPE_DEST) [get_property value $DMA_TYPE_DEST] + if { [gen_USERPARAMETER_DMA_AXI_PROTOCOL_DEST_ENABLEMENT $values(DMA_TYPE_DEST)] } { + set_property enabled true $DMA_AXI_PROTOCOL_DEST + } else { + set_property enabled false $DMA_AXI_PROTOCOL_DEST + } +} + +proc validate_PARAM_VALUE.DMA_AXI_PROTOCOL_DEST { PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } { + # Procedure called to validate DMA_AXI_PROTOCOL_DEST + return true +} + +proc update_PARAM_VALUE.DMA_AXI_PROTOCOL_SRC { PARAM_VALUE.DMA_AXI_PROTOCOL_SRC PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to update DMA_AXI_PROTOCOL_SRC when any of the dependent parameters in the arguments change + + set DMA_AXI_PROTOCOL_SRC ${PARAM_VALUE.DMA_AXI_PROTOCOL_SRC} + set DMA_TYPE_SRC ${PARAM_VALUE.DMA_TYPE_SRC} + set values(DMA_TYPE_SRC) [get_property value $DMA_TYPE_SRC] + if { [gen_USERPARAMETER_DMA_AXI_PROTOCOL_SRC_ENABLEMENT $values(DMA_TYPE_SRC)] } { + set_property enabled true $DMA_AXI_PROTOCOL_SRC + } else { + set_property enabled false $DMA_AXI_PROTOCOL_SRC + } +} + +proc validate_PARAM_VALUE.DMA_AXI_PROTOCOL_SRC { PARAM_VALUE.DMA_AXI_PROTOCOL_SRC } { + # Procedure called to validate DMA_AXI_PROTOCOL_SRC + return true +} + +proc update_PARAM_VALUE.SYNC_TRANSFER_START { PARAM_VALUE.SYNC_TRANSFER_START PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to update SYNC_TRANSFER_START when any of the dependent parameters in the arguments change + + set SYNC_TRANSFER_START ${PARAM_VALUE.SYNC_TRANSFER_START} + set DMA_TYPE_SRC ${PARAM_VALUE.DMA_TYPE_SRC} + set values(DMA_TYPE_SRC) [get_property value $DMA_TYPE_SRC] + if { [gen_USERPARAMETER_SYNC_TRANSFER_START_ENABLEMENT $values(DMA_TYPE_SRC)] } { + set_property enabled true $SYNC_TRANSFER_START + } else { + set_property enabled false $SYNC_TRANSFER_START + } +} + +proc validate_PARAM_VALUE.SYNC_TRANSFER_START { PARAM_VALUE.SYNC_TRANSFER_START } { + # Procedure called to validate SYNC_TRANSFER_START + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_DEST_REQ { PARAM_VALUE.ASYNC_CLK_DEST_REQ } { + # Procedure called to update ASYNC_CLK_DEST_REQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_DEST_REQ { PARAM_VALUE.ASYNC_CLK_DEST_REQ } { + # Procedure called to validate ASYNC_CLK_DEST_REQ + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_REQ_SRC { PARAM_VALUE.ASYNC_CLK_REQ_SRC } { + # Procedure called to update ASYNC_CLK_REQ_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_REQ_SRC { PARAM_VALUE.ASYNC_CLK_REQ_SRC } { + # Procedure called to validate ASYNC_CLK_REQ_SRC + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_SRC_DEST { PARAM_VALUE.ASYNC_CLK_SRC_DEST } { + # Procedure called to update ASYNC_CLK_SRC_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_SRC_DEST { PARAM_VALUE.ASYNC_CLK_SRC_DEST } { + # Procedure called to validate ASYNC_CLK_SRC_DEST + return true +} + +proc update_PARAM_VALUE.AXI_SLICE_DEST { PARAM_VALUE.AXI_SLICE_DEST } { + # Procedure called to update AXI_SLICE_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_SLICE_DEST { PARAM_VALUE.AXI_SLICE_DEST } { + # Procedure called to validate AXI_SLICE_DEST + return true +} + +proc update_PARAM_VALUE.AXI_SLICE_SRC { PARAM_VALUE.AXI_SLICE_SRC } { + # Procedure called to update AXI_SLICE_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_SLICE_SRC { PARAM_VALUE.AXI_SLICE_SRC } { + # Procedure called to validate AXI_SLICE_SRC + return true +} + +proc update_PARAM_VALUE.CYCLIC { PARAM_VALUE.CYCLIC } { + # Procedure called to update CYCLIC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CYCLIC { PARAM_VALUE.CYCLIC } { + # Procedure called to validate CYCLIC + return true +} + +proc update_PARAM_VALUE.DMA_2D_TRANSFER { PARAM_VALUE.DMA_2D_TRANSFER } { + # Procedure called to update DMA_2D_TRANSFER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_2D_TRANSFER { PARAM_VALUE.DMA_2D_TRANSFER } { + # Procedure called to validate DMA_2D_TRANSFER + return true +} + +proc update_PARAM_VALUE.DMA_DATA_WIDTH_DEST { PARAM_VALUE.DMA_DATA_WIDTH_DEST } { + # Procedure called to update DMA_DATA_WIDTH_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_DATA_WIDTH_DEST { PARAM_VALUE.DMA_DATA_WIDTH_DEST } { + # Procedure called to validate DMA_DATA_WIDTH_DEST + return true +} + +proc update_PARAM_VALUE.DMA_DATA_WIDTH_SRC { PARAM_VALUE.DMA_DATA_WIDTH_SRC } { + # Procedure called to update DMA_DATA_WIDTH_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_DATA_WIDTH_SRC { PARAM_VALUE.DMA_DATA_WIDTH_SRC } { + # Procedure called to validate DMA_DATA_WIDTH_SRC + return true +} + +proc update_PARAM_VALUE.DMA_LENGTH_WIDTH { PARAM_VALUE.DMA_LENGTH_WIDTH } { + # Procedure called to update DMA_LENGTH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_LENGTH_WIDTH { PARAM_VALUE.DMA_LENGTH_WIDTH } { + # Procedure called to validate DMA_LENGTH_WIDTH + return true +} + +proc update_PARAM_VALUE.DMA_TYPE_DEST { PARAM_VALUE.DMA_TYPE_DEST } { + # Procedure called to update DMA_TYPE_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_TYPE_DEST { PARAM_VALUE.DMA_TYPE_DEST } { + # Procedure called to validate DMA_TYPE_DEST + return true +} + +proc update_PARAM_VALUE.DMA_TYPE_SRC { PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to update DMA_TYPE_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_TYPE_SRC { PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to validate DMA_TYPE_SRC + return true +} + +proc update_PARAM_VALUE.FIFO_SIZE { PARAM_VALUE.FIFO_SIZE } { + # Procedure called to update FIFO_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FIFO_SIZE { PARAM_VALUE.FIFO_SIZE } { + # Procedure called to validate FIFO_SIZE + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.MAX_BYTES_PER_BURST { PARAM_VALUE.MAX_BYTES_PER_BURST } { + # Procedure called to update MAX_BYTES_PER_BURST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MAX_BYTES_PER_BURST { PARAM_VALUE.MAX_BYTES_PER_BURST } { + # Procedure called to validate MAX_BYTES_PER_BURST + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC { MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC PARAM_VALUE.DMA_DATA_WIDTH_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH_SRC}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC} +} + +proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST { MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST PARAM_VALUE.DMA_DATA_WIDTH_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH_DEST}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST} +} + +proc update_MODELPARAM_VALUE.DMA_LENGTH_WIDTH { MODELPARAM_VALUE.DMA_LENGTH_WIDTH PARAM_VALUE.DMA_LENGTH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_LENGTH_WIDTH}] ${MODELPARAM_VALUE.DMA_LENGTH_WIDTH} +} + +proc update_MODELPARAM_VALUE.DMA_2D_TRANSFER { MODELPARAM_VALUE.DMA_2D_TRANSFER PARAM_VALUE.DMA_2D_TRANSFER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_2D_TRANSFER}] ${MODELPARAM_VALUE.DMA_2D_TRANSFER} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC { MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC PARAM_VALUE.ASYNC_CLK_REQ_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_REQ_SRC}] ${MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST { MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST PARAM_VALUE.ASYNC_CLK_SRC_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_SRC_DEST}] ${MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ { MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ PARAM_VALUE.ASYNC_CLK_DEST_REQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_DEST_REQ}] ${MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ} +} + +proc update_MODELPARAM_VALUE.AXI_SLICE_DEST { MODELPARAM_VALUE.AXI_SLICE_DEST PARAM_VALUE.AXI_SLICE_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_SLICE_DEST}] ${MODELPARAM_VALUE.AXI_SLICE_DEST} +} + +proc update_MODELPARAM_VALUE.AXI_SLICE_SRC { MODELPARAM_VALUE.AXI_SLICE_SRC PARAM_VALUE.AXI_SLICE_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_SLICE_SRC}] ${MODELPARAM_VALUE.AXI_SLICE_SRC} +} + +proc update_MODELPARAM_VALUE.SYNC_TRANSFER_START { MODELPARAM_VALUE.SYNC_TRANSFER_START PARAM_VALUE.SYNC_TRANSFER_START } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC_TRANSFER_START}] ${MODELPARAM_VALUE.SYNC_TRANSFER_START} +} + +proc update_MODELPARAM_VALUE.CYCLIC { MODELPARAM_VALUE.CYCLIC PARAM_VALUE.CYCLIC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CYCLIC}] ${MODELPARAM_VALUE.CYCLIC} +} + +proc update_MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST { MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST}] ${MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST} +} + +proc update_MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC { MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC PARAM_VALUE.DMA_AXI_PROTOCOL_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_AXI_PROTOCOL_SRC}] ${MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC} +} + +proc update_MODELPARAM_VALUE.DMA_TYPE_DEST { MODELPARAM_VALUE.DMA_TYPE_DEST PARAM_VALUE.DMA_TYPE_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_TYPE_DEST}] ${MODELPARAM_VALUE.DMA_TYPE_DEST} +} + +proc update_MODELPARAM_VALUE.DMA_TYPE_SRC { MODELPARAM_VALUE.DMA_TYPE_SRC PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_TYPE_SRC}] ${MODELPARAM_VALUE.DMA_TYPE_SRC} +} + +proc update_MODELPARAM_VALUE.MAX_BYTES_PER_BURST { MODELPARAM_VALUE.MAX_BYTES_PER_BURST PARAM_VALUE.MAX_BYTES_PER_BURST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MAX_BYTES_PER_BURST}] ${MODELPARAM_VALUE.MAX_BYTES_PER_BURST} +} + +proc update_MODELPARAM_VALUE.FIFO_SIZE { MODELPARAM_VALUE.FIFO_SIZE PARAM_VALUE.FIFO_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FIFO_SIZE}] ${MODELPARAM_VALUE.FIFO_SIZE} +} + diff --git a/fpga/usrp3/lib/vivado_ipi/axi_regfile/axi_regfile.vhd b/fpga/usrp3/lib/vivado_ipi/axi_regfile/axi_regfile.vhd new file mode 100644 index 000000000..3ec84543f --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_regfile/axi_regfile.vhd @@ -0,0 +1,144 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_regfile is +generic ( + NUM_REGS : integer := 16 +); +port ( + regs : out std_logic_vector(NUM_REGS*32-1 downto 0); + + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(11 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(11 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic +); +end axi_regfile; + +architecture arch of axi_regfile is + type regfile_t is array (integer range <>) of std_logic_vector(31 downto 0); + signal read_token : std_logic; + signal write_addr : std_logic_vector(S_AXI_AWADDR'left downto S_AXI_AWADDR'right); + signal write_strb : std_logic_vector(3 downto 0); + signal write_addr_token : std_logic; + signal write_data : std_logic_vector(31 downto 0); + signal write_data_token : std_logic; + signal soft_reset : std_logic; + signal regs_r : regfile_t(NUM_REGS-1 downto 0); +begin + + S_AXI_ARREADY <= not read_token; + S_AXI_RVALID <= read_token; + S_AXI_RRESP <= "00"; + + S_AXI_AWREADY <= not write_addr_token; + S_AXI_WREADY <= not write_data_token; + S_AXI_BVALID <= write_addr_token and write_data_token; + S_AXI_BRESP <= "00"; + + --Port assignment from registers + reg_distribution : process (regs_r) + begin + for i in 0 to NUM_REGS-1 loop + regs(32*(i+1)-1 downto 32*i) <= regs_r(i); + end loop; + end process reg_distribution; + + --Register reads + read_proc : process (S_AXI_ACLK) + variable read_addr : integer; + begin + if rising_edge(S_AXI_ACLK) then + read_addr := to_integer(unsigned(S_AXI_ARADDR(S_AXI_ARADDR'left downto S_AXI_ARADDR'right+2))); + + if (S_AXI_ARESETN = '0') then + read_token <= '0'; + elsif (S_AXI_ARVALID = '1') and (read_token = '0') then + read_token <= '1'; + elsif (S_AXI_RREADY = '1') and (read_token = '1') then + read_token <= '0'; + end if; + + if (S_AXI_ARVALID = '1') and (read_token = '0') then + S_AXI_RDATA <= (others => '0'); + for i in 0 to NUM_REGS-1 loop + if (read_addr = i) then + S_AXI_RDATA <= regs_r(i); + end if; + end loop; + end if; + end if; + end process read_proc; + + write_proc : process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if (S_AXI_ARESETN = '0') then + write_addr_token <= '0'; + write_data_token <= '0'; + write_strb <= (others => '0'); + else + if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then + write_addr_token <= '1'; + elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then + write_addr_token <= '0'; + end if; + + if (S_AXI_WVALID = '1') and (write_data_token = '0') then + write_data_token <= '1'; + elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then + write_data_token <= '0'; + end if; + end if; + + if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then + write_addr <= S_AXI_AWADDR; + end if; + + if (S_AXI_WVALID = '1') and (write_data_token = '0') then + write_data <= S_AXI_WDATA; + write_strb <= S_AXI_WSTRB; + end if; + end if; + end process write_proc; + + -- Update registers on write + write_reg : process (S_AXI_ACLK) + variable write_addr_int : integer; + begin + if rising_edge(S_AXI_ACLK) then + write_addr_int := to_integer(unsigned(write_addr(write_addr'left downto 2))); + + if (S_AXI_ARESETN = '0') or (soft_reset = '1') then + --Initial states for each signal + soft_reset <= '0'; + elsif (write_addr_token = '1') and (write_data_token = '1') then + for i in 0 to NUM_REGS-1 loop + if (write_addr_int = i) then + for j in write_strb'left downto write_strb'right loop + regs_r(i)(j*8+7 downto j*8) <= write_data(j*8+7 downto j*8); + end loop; + end if; + end loop; + end if; + end if; + end process write_reg; + +end arch; + diff --git a/fpga/usrp3/lib/vivado_ipi/axi_regfile/component.xml b/fpga/usrp3/lib/vivado_ipi/axi_regfile/component.xml new file mode 100644 index 000000000..fc0e6382d --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_regfile/component.xml @@ -0,0 +1,661 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ettus.com</spirit:vendor> + <spirit:library>ip</spirit:library> + <spirit:name>axi_regfile</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>S_AXI</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/> + <spirit:slave> + <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/> + </spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWADDR</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_AWADDR</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_AWVALID</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>AWREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_AWREADY</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_WDATA</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>WSTRB</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S_AXI_WSTRB</spirit:name> + </spirit:physicalPort> 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spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_REGS" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">16</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>Component_Name</spirit:name> + <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_regfile_v1_0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <xilinx:coreExtensions> + <xilinx:supportedFamilies> + <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family> + </xilinx:supportedFamilies> + <xilinx:taxonomies> + <xilinx:taxonomy>/EttusResearch</xilinx:taxonomy> + </xilinx:taxonomies> + <xilinx:displayName>axi_regfile_v1_0</xilinx:displayName> + <xilinx:coreRevision>2</xilinx:coreRevision> + <xilinx:coreCreationDateTime>2017-06-02T21:40:33Z</xilinx:coreCreationDateTime> + <xilinx:tags> + <xilinx:tag xilinx:name="nopcore"/> + <xilinx:tag xilinx:name="ettus.com:ip:axi_regfile:1.0_ARCHIVE_LOCATION">usrp3/lib/vivado_ipi/axi_regfile</xilinx:tag> + </xilinx:tags> + </xilinx:coreExtensions> + <xilinx:packagingInfo> + <xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion> + <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="93ec0ca8"/> + <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="3fb862bd"/> + <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3c1bd853"/> + <xilinx:checksum xilinx:scope="ports" xilinx:value="172f3ad0"/> + <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d473f965"/> + <xilinx:checksum xilinx:scope="parameters" xilinx:value="cbb0b4a6"/> + </xilinx:packagingInfo> + </spirit:vendorExtensions> +</spirit:component> diff --git a/fpga/usrp3/lib/vivado_ipi/axi_regfile/xgui/axi_regfile_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/axi_regfile/xgui/axi_regfile_v1_0.tcl new file mode 100644 index 000000000..0ab7d0eca --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/axi_regfile/xgui/axi_regfile_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "NUM_REGS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.NUM_REGS { PARAM_VALUE.NUM_REGS } { + # Procedure called to update NUM_REGS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_REGS { PARAM_VALUE.NUM_REGS } { + # Procedure called to validate NUM_REGS + return true +} + + +proc update_MODELPARAM_VALUE.NUM_REGS { MODELPARAM_VALUE.NUM_REGS PARAM_VALUE.NUM_REGS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_REGS}] ${MODELPARAM_VALUE.NUM_REGS} +} + diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd.xml new file mode 100644 index 000000000..66d44bdbd --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd.xml @@ -0,0 +1,13 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>analog.com</spirit:vendor> + <spirit:library>interface</spirit:library> + <spirit:name>fifo_rd</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:extends spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> + <spirit:description>FIFO Read Interface</spirit:description> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd_rtl.xml new file mode 100644 index 000000000..3c15f7203 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_rd_rtl.xml @@ -0,0 +1,69 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>analog.com</spirit:vendor> + <spirit:library>interface</spirit:library> + <spirit:name>fifo_rd_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="fifo_rd" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>DATA</spirit:logicalName> + <spirit:description>FIFO Read Data</spirit:description> + <spirit:wire> + <spirit:qualifier> + <spirit:isData>true</spirit:isData> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + <spirit:defaultValue>0</spirit:defaultValue> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>EN</spirit:logicalName> + <spirit:description>FIFO Read Enable</spirit:description> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + <spirit:defaultValue>0</spirit:defaultValue> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>UNDERFLOW</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:width>1</spirit:width> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>VALID</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr.xml new file mode 100644 index 000000000..8e1f4d781 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr.xml @@ -0,0 +1,13 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>analog.com</spirit:vendor> + <spirit:library>interface</spirit:library> + <spirit:name>fifo_wr</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:extends spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> + <spirit:description>FIFO Write Interface</spirit:description> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr_rtl.xml new file mode 100644 index 000000000..49509dbfa --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/fifo_wr_rtl.xml @@ -0,0 +1,88 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>analog.com</spirit:vendor> + <spirit:library>interface</spirit:library> + <spirit:name>fifo_wr_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="fifo_wr" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>DATA</spirit:logicalName> + <spirit:description/> + <spirit:wire> + <spirit:qualifier> + <spirit:isData>true</spirit:isData> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + <spirit:defaultValue>0</spirit:defaultValue> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>EN</spirit:logicalName> + <spirit:description/> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + <spirit:defaultValue>0</spirit:defaultValue> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>OVERFLOW</spirit:logicalName> + <spirit:description/> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>optional</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>optional</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + <spirit:defaultValue>0</spirit:defaultValue> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>SYNC</spirit:logicalName> + <spirit:description/> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>optional</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>optional</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + <spirit:defaultValue>0</spirit:defaultValue> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>XFER_REQ</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll.xml new file mode 100644 index 000000000..583c1f242 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll.xml @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_pll</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll_rtl.xml new file mode 100644 index 000000000..58d14d2f7 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_pll_rtl.xml @@ -0,0 +1,46 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_pll_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_pll" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>cpll_rst_m</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isReset>true</spirit:isReset> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>cpll_ref_clk_in</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isClock>true</spirit:isClock> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll.xml new file mode 100644 index 000000000..12e43a4c0 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll.xml @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_qpll</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll_rtl.xml new file mode 100644 index 000000000..486cb8b61 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_qpll_rtl.xml @@ -0,0 +1,46 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_qpll_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_qpll" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>qpll_rst</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isReset>true</spirit:isReset> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>qpll_ref_clk</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isClock>true</spirit:isClock> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx.xml new file mode 100644 index 000000000..24e435073 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx.xml @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_rx</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig.xml new file mode 100644 index 000000000..a8cae5ade --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig.xml @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_rx_ksig</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig_rtl.xml new file mode 100644 index 000000000..4e09e7982 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_ksig_rtl.xml @@ -0,0 +1,85 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_rx_ksig_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_rx_ksig" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>rx_gt_ilas_f</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_gt_ilas_q</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_gt_ilas_a</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_gt_ilas_r</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_gt_cgs_k</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>4</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_rtl.xml new file mode 100644 index 000000000..e2e49d1c3 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_rx_rtl.xml @@ -0,0 +1,409 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_rx_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_rx" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>rx_p</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_n</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_rst</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isReset>true</spirit:isReset> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_rst_m</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isReset>true</spirit:isReset> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + 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<spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_ip_sync</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rx_ip_rst_done</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx.xml new file mode 100644 index 000000000..50eca29d0 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx.xml @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_tx</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx_rtl.xml new file mode 100644 index 000000000..faaa387f2 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_gt_tx_rtl.xml @@ -0,0 +1,379 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_gt_tx_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_gt_tx" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>tx_p</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_n</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_rst</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isReset>true</spirit:isReset> + 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<spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_out_clk</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isClock>true</spirit:isClock> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_clk</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isClock>true</spirit:isClock> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_sysref</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_sync</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_data</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>32</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>32</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_ip_rst</spirit:logicalName> + <spirit:wire> + <spirit:qualifier> + <spirit:isReset>true</spirit:isReset> + </spirit:qualifier> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_ip_data</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>32</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>32</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_ip_sysref</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_ip_sync</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>tx_ip_rst_done</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch.xml new file mode 100644 index 000000000..32a225486 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch.xml @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_xcvr_ch</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch_rtl.xml new file mode 100644 index 000000000..ba01aef9c --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_ch_rtl.xml @@ -0,0 +1,235 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_xcvr_ch_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_xcvr_ch" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>pll_locked</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rst</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>user_ready</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rst_done</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>lpm_dfe_n</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rate</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>3</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>3</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>sys_clk_sel</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>2</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>2</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>out_clk_sel</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>3</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>3</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>sel</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>8</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>8</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>enb</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>addr</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>12</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>12</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>wr</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>wdata</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>16</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>16</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rdata</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>16</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>16</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>ready</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm.xml new file mode 100644 index 000000000..218fd3686 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm.xml @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_xcvr_cm</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:directConnection>false</spirit:directConnection> + <spirit:isAddressable>false</spirit:isAddressable> + <spirit:maxMasters>1</spirit:maxMasters> + <spirit:maxSlaves>1</spirit:maxSlaves> +</spirit:busDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm_rtl.xml b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm_rtl.xml new file mode 100644 index 000000000..beb223077 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/interfaces/if_xcvr_cm_rtl.xml @@ -0,0 +1,115 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>ADI</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>if_xcvr_cm_rtl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busType spirit:vendor="ADI" spirit:library="user" spirit:name="if_xcvr_cm" spirit:version="1.0"/> + <spirit:ports> + <spirit:port> + <spirit:logicalName>sel</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>8</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>8</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>enb</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>addr</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>12</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>12</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>wr</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>wdata</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>16</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>16</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>rdata</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>16</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>16</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:logicalName>ready</spirit:logicalName> + <spirit:wire> + <spirit:onMaster> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>in</spirit:direction> + </spirit:onMaster> + <spirit:onSlave> + <spirit:presence>required</spirit:presence> + <spirit:width>1</spirit:width> + <spirit:direction>out</spirit:direction> + </spirit:onSlave> + </spirit:wire> + </spirit:port> + </spirit:ports> +</spirit:abstractionDefinition> diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile new file mode 100644 index 000000000..d1e77a7b1 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile @@ -0,0 +1,51 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/sync_bits.v +M_DEPS += ../common/sync_gray.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += address_gray.v +M_DEPS += address_gray_pipelined.v +M_DEPS += address_sync.v +M_DEPS += util_axis_fifo.v +M_DEPS += util_axis_fifo_ip.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: util_axis_fifo.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +util_axis_fifo.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_axis_fifo_ip.tcl >> util_axis_fifo_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v new file mode 100644 index 000000000..5c912179d --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v @@ -0,0 +1,156 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module fifo_address_gray ( + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output reg m_axis_valid, + output reg [ADDRESS_WIDTH:0] m_axis_level, + + input s_axis_aclk, + input s_axis_aresetn, + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output reg [ADDRESS_WIDTH:0] s_axis_room +); + +parameter ADDRESS_WIDTH = 4; + +reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; +reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; + +reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; +reg [ADDRESS_WIDTH:0] _m_axis_raddr_next; + +reg [ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00; +wire [ADDRESS_WIDTH:0] s_axis_waddr_gray_next; +wire [ADDRESS_WIDTH:0] s_axis_raddr_gray; + +reg [ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00; +wire [ADDRESS_WIDTH:0] m_axis_raddr_gray_next; +wire [ADDRESS_WIDTH:0] m_axis_waddr_gray; + +assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0]; + +always @(*) +begin + if (s_axis_ready && s_axis_valid) + _s_axis_waddr_next <= _s_axis_waddr + 1; + else + _s_axis_waddr_next <= _s_axis_waddr; +end + +assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1]; + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + _s_axis_waddr <= 'h00; + s_axis_waddr_gray <= 'h00; + end else begin + _s_axis_waddr <= _s_axis_waddr_next; + s_axis_waddr_gray <= s_axis_waddr_gray_next; + end +end + +always @(*) +begin + if (m_axis_ready && m_axis_valid) + _m_axis_raddr_next <= _m_axis_raddr + 1; + else + _m_axis_raddr_next <= _m_axis_raddr; +end + +assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1]; + +always @(posedge m_axis_aclk) +begin + if (m_axis_aresetn == 1'b0) begin + _m_axis_raddr <= 'h00; + m_axis_raddr_gray <= 'h00; + end else begin + _m_axis_raddr <= _m_axis_raddr_next; + m_axis_raddr_gray <= m_axis_raddr_gray_next; + end +end + +sync_bits #( + .NUM_OF_BITS(ADDRESS_WIDTH + 1) +) i_waddr_sync ( + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in(s_axis_waddr_gray), + .out(m_axis_waddr_gray) +); + +sync_bits #( + .NUM_OF_BITS(ADDRESS_WIDTH + 1) +) i_raddr_sync ( + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in(m_axis_raddr_gray), + .out(s_axis_raddr_gray) +); + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + s_axis_ready <= 1'b1; + s_axis_empty <= 1'b1; + end else begin + s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] || + s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] || + s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]); + s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next; + end +end + +always @(posedge m_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) + m_axis_valid <= 1'b0; + else begin + m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next; + end +end + +endmodule + diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v new file mode 100644 index 000000000..ed7055b39 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v @@ -0,0 +1,151 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module fifo_address_gray_pipelined ( + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output reg m_axis_valid, + output [ADDRESS_WIDTH-1:0] m_axis_raddr, + output reg [ADDRESS_WIDTH:0] m_axis_level, + + input s_axis_aclk, + input s_axis_aresetn, + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output reg [ADDRESS_WIDTH:0] s_axis_room +); + +parameter ADDRESS_WIDTH = 4; + +reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; +reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; +wire [ADDRESS_WIDTH:0] _s_axis_raddr; + +reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; +reg [ADDRESS_WIDTH:0] _m_axis_raddr_next; +wire [ADDRESS_WIDTH:0] _m_axis_waddr; + +assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0]; +assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0]; + +always @(*) +begin + if (s_axis_ready && s_axis_valid) + _s_axis_waddr_next <= _s_axis_waddr + 1; + else + _s_axis_waddr_next <= _s_axis_waddr; +end + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + _s_axis_waddr <= 'h00; + end else begin + _s_axis_waddr <= _s_axis_waddr_next; + end +end + +always @(*) +begin + if (m_axis_ready && m_axis_valid) + _m_axis_raddr_next <= _m_axis_raddr + 1; + else + _m_axis_raddr_next <= _m_axis_raddr; +end + +always @(posedge m_axis_aclk) +begin + if (m_axis_aresetn == 1'b0) begin + _m_axis_raddr <= 'h00; + end else begin + _m_axis_raddr <= _m_axis_raddr_next; + end +end + +sync_gray #( + .DATA_WIDTH(ADDRESS_WIDTH + 1) +) i_waddr_sync ( + .in_clk(s_axis_aclk), + .in_resetn(s_axis_aresetn), + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in_count(_s_axis_waddr), + .out_count(_m_axis_waddr) +); + +sync_gray #( + .DATA_WIDTH(ADDRESS_WIDTH + 1) +) i_raddr_sync ( + .in_clk(m_axis_aclk), + .in_resetn(m_axis_aresetn), + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in_count(_m_axis_raddr), + .out_count(_s_axis_raddr) +); + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + s_axis_ready <= 1'b1; + s_axis_empty <= 1'b1; + s_axis_room <= 2**ADDRESS_WIDTH; + end else begin + s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] || + _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]); + s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next; + s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH; + end +end + +always @(posedge m_axis_aclk) +begin + if (m_axis_aresetn == 1'b0) begin + m_axis_valid <= 1'b0; + m_axis_level <= 'h00; + end else begin + m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next; + m_axis_level <= _m_axis_waddr - _m_axis_raddr_next; + end +end + +endmodule + diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v new file mode 100644 index 000000000..6c94dba9c --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v @@ -0,0 +1,108 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module fifo_address_sync ( + input clk, + input resetn, + + input m_axis_ready, + output reg m_axis_valid, + output reg [ADDRESS_WIDTH-1:0] m_axis_raddr, + output [ADDRESS_WIDTH:0] m_axis_level, + + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output reg [ADDRESS_WIDTH-1:0] s_axis_waddr, + output [ADDRESS_WIDTH:0] s_axis_room +); + +parameter ADDRESS_WIDTH = 4; + +reg [ADDRESS_WIDTH:0] room = 2**ADDRESS_WIDTH; +reg [ADDRESS_WIDTH:0] level = 'h00; +reg [ADDRESS_WIDTH:0] level_next; + +assign s_axis_room = room; +assign m_axis_level = level; + +wire read = m_axis_ready & m_axis_valid; +wire write = s_axis_ready & s_axis_valid; + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + s_axis_waddr <= 'h00; + m_axis_raddr <= 'h00; + end else begin + if (write) + s_axis_waddr <= s_axis_waddr + 1'b1; + if (read) + m_axis_raddr <= m_axis_raddr + 1'b1; + end +end + +always @(*) +begin + if (read & ~write) + level_next <= level - 1'b1; + else if (~read & write) + level_next <= level + 1'b1; + else + level_next <= level; +end + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + m_axis_valid <= 1'b0; + s_axis_ready <= 1'b0; + level <= 'h00; + room <= 2**ADDRESS_WIDTH; + s_axis_empty <= 'h00; + end else begin + level <= level_next; + room <= 2**ADDRESS_WIDTH - level_next; + m_axis_valid <= level_next != 0; + s_axis_ready <= level_next != 2**ADDRESS_WIDTH; + s_axis_empty <= level_next == 0; + end +end + +endmodule + diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml new file mode 100644 index 000000000..44d9a2af4 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml @@ -0,0 +1,542 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>analog.com</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>util_axis_fifo</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>S_AXIS</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axis_valid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axis_ready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axis_data</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>M_AXIS</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:master/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>m_axis_valid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + 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a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v new file mode 100644 index 000000000..2530f047b --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v @@ -0,0 +1,76 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing bit signals from one clock domain to another. + * It uses the standard approach of 2 FF in series. + * Note, that while the module allows to synchronize multiple bits at once it is + * only able to synchronize multi-bit signals where at max one bit changes per + * clock cycle (e.g. a gray counter). + */ +module sync_bits +( + input [NUM_OF_BITS-1:0] in, + input out_resetn, + input out_clk, + output [NUM_OF_BITS-1:0] out +); + +// Number of bits to synchronize +parameter NUM_OF_BITS = 1; +// Whether input and output clocks are asynchronous, if 0 the synchronizer will +// be bypassed and the output signal equals the input signal. +parameter ASYNC_CLK = 1; + +reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0; +reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0; + +always @(posedge out_clk) +begin + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'b0; + cdc_sync_stage2 <= 'b0; + end else begin + cdc_sync_stage1 <= in; + cdc_sync_stage2 <= cdc_sync_stage1; + end +end + +assign out = ASYNC_CLK ? cdc_sync_stage2 : in; + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v new file mode 100644 index 000000000..2b67e1266 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v @@ -0,0 +1,111 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing a counter from one clock domain to another + * using gray code. To work correctly the counter must not change its value by + * more than one in one clock cycle in the source domain. I.e. the value may + * change by either -1, 0 or +1. + */ +module sync_gray ( + input in_clk, + input in_resetn, + input [DATA_WIDTH-1:0] in_count, + input out_resetn, + input out_clk, + output [DATA_WIDTH-1:0] out_count +); + +// Bit-width of the counter +parameter DATA_WIDTH = 1; +// Whether the input and output clock are asynchronous, if set to 0 the +// synchronizer will be bypassed and out_count will be in_count. +parameter ASYNC_CLK = 1; + +reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0; +reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0; +reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0; +reg [DATA_WIDTH-1:0] out_count_m = 'h0; + +function [DATA_WIDTH-1:0] g2b; + input [DATA_WIDTH-1:0] g; + reg [DATA_WIDTH-1:0] b; + integer i; + begin + b[DATA_WIDTH-1] = g[DATA_WIDTH-1]; + for (i = DATA_WIDTH - 2; i >= 0; i = i - 1) + b[i] = b[i + 1] ^ g[i]; + g2b = b; + end +endfunction + +function [DATA_WIDTH-1:0] b2g; + input [DATA_WIDTH-1:0] b; + reg [DATA_WIDTH-1:0] g; + integer i; + begin + g[DATA_WIDTH-1] = b[DATA_WIDTH-1]; + for (i = DATA_WIDTH - 2; i >= 0; i = i -1) + g[i] = b[i + 1] ^ b[i]; + b2g = g; + end +endfunction + +always @(posedge in_clk) begin + if (in_resetn == 1'b0) begin + cdc_sync_stage0 <= 'h00; + end else begin + cdc_sync_stage0 <= b2g(in_count); + end +end + +always @(posedge out_clk) begin + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'h00; + cdc_sync_stage2 <= 'h00; + out_count_m <= 'h00; + end else begin + cdc_sync_stage1 <= cdc_sync_stage0; + cdc_sync_stage2 <= cdc_sync_stage1; + out_count_m <= g2b(cdc_sync_stage2); + end +end + +assign out_count = ASYNC_CLK ? out_count_m : in_count; + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v new file mode 100644 index 000000000..f2661daa1 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v @@ -0,0 +1,215 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// Source: git://github.com/analogdevicesinc/hdl.git +// Commit hash: 04843795d8d6a496c00ee91b437d57924bc1cbf1 + +module util_axis_fifo ( + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output m_axis_valid, + output [DATA_WIDTH-1:0] m_axis_data, + output [ADDRESS_WIDTH:0] m_axis_level, + + input s_axis_aclk, + input s_axis_aresetn, + output s_axis_ready, + input s_axis_valid, + input [DATA_WIDTH-1:0] s_axis_data, + output s_axis_empty, + output [ADDRESS_WIDTH:0] s_axis_room +); + +parameter DATA_WIDTH = 64; +parameter ASYNC_CLK = 1; +parameter ADDRESS_WIDTH = 4; +parameter S_AXIS_REGISTERED = 1; + +generate if (ADDRESS_WIDTH == 0) begin + +reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; +reg s_axis_waddr = 1'b0; +reg m_axis_raddr = 1'b0; + +wire m_axis_waddr; +wire s_axis_raddr; + +sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) +) i_waddr_sync ( + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in(s_axis_waddr), + .out(m_axis_waddr) +); + +sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) +) i_raddr_sync ( + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in(m_axis_raddr), + .out(s_axis_raddr) +); + +assign m_axis_valid = m_axis_raddr != m_axis_waddr; +assign m_axis_level = m_axis_valid; +assign s_axis_ready = s_axis_raddr == s_axis_waddr; +assign s_axis_empty = s_axis_ready; +assign s_axis_room = s_axis_ready; + +always @(posedge s_axis_aclk) begin + if (s_axis_ready) + cdc_sync_fifo_ram <= s_axis_data; +end + +always @(posedge s_axis_aclk) begin + if (s_axis_aresetn == 1'b0) begin + s_axis_waddr <= 1'b0; + end else begin + if (s_axis_ready & s_axis_valid) begin + s_axis_waddr <= s_axis_waddr + 1'b1; + end + end +end + +always @(posedge m_axis_aclk) begin + if (m_axis_aresetn == 1'b0) begin + m_axis_raddr <= 1'b0; + end else begin + if (m_axis_valid & m_axis_ready) + m_axis_raddr <= m_axis_raddr + 1'b1; + end +end + +assign m_axis_data = cdc_sync_fifo_ram; + +end else begin + +reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1]; + +wire [ADDRESS_WIDTH-1:0] s_axis_waddr; +wire [ADDRESS_WIDTH-1:0] m_axis_raddr; +wire _m_axis_ready; +wire _m_axis_valid; + +if (ASYNC_CLK == 1) begin + +fifo_address_gray_pipelined #( + .ADDRESS_WIDTH(ADDRESS_WIDTH) +) i_address_gray ( + .m_axis_aclk(m_axis_aclk), + .m_axis_aresetn(m_axis_aresetn), + .m_axis_ready(_m_axis_ready), + .m_axis_valid(_m_axis_valid), + .m_axis_raddr(m_axis_raddr), + .m_axis_level(m_axis_level), + + .s_axis_aclk(s_axis_aclk), + .s_axis_aresetn(s_axis_aresetn), + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_empty(s_axis_empty), + .s_axis_waddr(s_axis_waddr), + .s_axis_room(s_axis_room) +); + +end else begin + +fifo_address_sync #( + .ADDRESS_WIDTH(ADDRESS_WIDTH) +) i_address_sync ( + .clk(m_axis_aclk), + .resetn(m_axis_aresetn), + .m_axis_ready(_m_axis_ready), + .m_axis_valid(_m_axis_valid), + .m_axis_raddr(m_axis_raddr), + .m_axis_level(m_axis_level), + + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_empty(s_axis_empty), + .s_axis_waddr(s_axis_waddr), + .s_axis_room(s_axis_room) +); + +end + +always @(posedge s_axis_aclk) begin + if (s_axis_ready) + ram[s_axis_waddr] <= s_axis_data; +end + +if (S_AXIS_REGISTERED == 1) begin + +reg [DATA_WIDTH-1:0] data; +reg valid; + +always @(posedge m_axis_aclk) begin + if (m_axis_aresetn == 1'b0) begin + valid <= 1'b0; + end else begin + if (_m_axis_valid) + valid <= 1'b1; + else if (m_axis_ready) + valid <= 1'b0; + end +end + +always @(posedge m_axis_aclk) begin + if (~valid || m_axis_ready) + data <= ram[m_axis_raddr]; +end + +assign _m_axis_ready = ~valid || m_axis_ready; +assign m_axis_data = data; +assign m_axis_valid = valid; + +end else begin + +assign _m_axis_ready = m_axis_ready; +assign m_axis_valid = _m_axis_valid; +assign m_axis_data = ram[m_axis_raddr]; + +end + +end endgenerate + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl new file mode 100644 index 000000000..014409288 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl @@ -0,0 +1,38 @@ + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_axis_fifo +adi_ip_files util_axis_fifo [list \ + "$ad_hdl_dir/library/common/sync_bits.v" \ + "$ad_hdl_dir/library/common/sync_gray.v" \ + "address_gray.v" \ + "address_gray_pipelined.v" \ + "address_sync.v" \ + "util_axis_fifo.v" \ +] + +adi_ip_properties_lite util_axis_fifo + +adi_add_bus "S_AXIS" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_valid" "TVALID"} \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_data" "TDATA"} \ + } + +adi_add_bus "M_AXIS" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_valid" "TVALID"} \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_data" "TDATA"} \ + } + +adi_add_bus_clock "m_axis_aclk" "M_AXIS" "m_axis_aresetn" +adi_add_bus_clock "s_axis_aclk" "S_AXIS" "m_axis_aresetn" + +ipx::save_core [ipx::current_core] diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl new file mode 100644 index 000000000..0f2092e6a --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0} + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "S_AXIS_REGISTERED" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to validate ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to validate ASYNC_CLK + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } { + # Procedure called to update S_AXIS_REGISTERED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } { + # Procedure called to validate S_AXIS_REGISTERED + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK} +} + +proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.S_AXIS_REGISTERED { MODELPARAM_VALUE.S_AXIS_REGISTERED PARAM_VALUE.S_AXIS_REGISTERED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.S_AXIS_REGISTERED}] ${MODELPARAM_VALUE.S_AXIS_REGISTERED} +} + diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_resize/component.xml b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/component.xml new file mode 100644 index 000000000..1b502fdf5 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/component.xml @@ -0,0 +1,373 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component 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<xilinx:coreCreationDateTime>2017-04-20T23:54:03Z</xilinx:coreCreationDateTime> + </xilinx:coreExtensions> + <xilinx:packagingInfo> + <xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion> + </xilinx:packagingInfo> + </spirit:vendorExtensions> +</spirit:component> diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_resize/util_axis_resize.v b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/util_axis_resize.v new file mode 100644 index 000000000..5dcd9518a --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/util_axis_resize.v @@ -0,0 +1,156 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// Source: git://github.com/analogdevicesinc/hdl.git +// Commit hash: 04843795d8d6a496c00ee91b437d57924bc1cbf1 + +module util_axis_resize ( + input clk, + input resetn, + + input s_valid, + output s_ready, + input [SLAVE_DATA_WIDTH-1:0] s_data, + + output m_valid, + input m_ready, + output [MASTER_DATA_WIDTH-1:0] m_data +); + +parameter MASTER_DATA_WIDTH = 64; +parameter SLAVE_DATA_WIDTH = 64; +parameter BIG_ENDIAN = 0; + +generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin + +assign m_valid = s_valid; +assign s_ready = m_ready; +assign m_data = s_data; + +end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin + +localparam RATIO = MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH; + +reg [MASTER_DATA_WIDTH-1:0] data; +reg [$clog2(RATIO)-1:0] count; +reg valid; + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + count <= RATIO - 1; + valid <= 1'b0; + end else begin + if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1) + valid <= 1'b1; + else if (m_ready == 1'b1) + valid <= 1'b0; + + if (s_ready == 1'b1 && s_valid == 1'b1) begin + if (count == 'h00) + count <= RATIO - 1; + else + count <= count - 1'b1; + end + end +end + +always @(posedge clk) +begin + if (s_ready == 1'b1 && s_valid == 1'b1) + if (BIG_ENDIAN == 1) begin + data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data}; + end else begin + data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]}; + end +end + +assign s_ready = ~valid || m_ready; +assign m_valid = valid; +assign m_data = data; + +end else begin + +localparam RATIO = SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH; + +reg [SLAVE_DATA_WIDTH-1:0] data; +reg [$clog2(RATIO)-1:0] count; +reg valid; + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + count <= RATIO - 1; + valid <= 1'b0; + end else begin + if (s_valid == 1'b1 && s_ready == 1'b1) + valid <= 1'b1; + else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1) + valid <= 1'b0; + + if (m_ready == 1'b1 && m_valid == 1'b1) begin + if (count == 'h00) + count <= RATIO - 1; + else + count <= count - 1'b1; + end + end +end + +always @(posedge clk) +begin + if (s_ready == 1'b1 && s_valid == 1'b1) begin + data <= s_data; + end else if (m_ready == 1'b1 && m_valid == 1'b1) begin + if (BIG_ENDIAN == 1) begin + data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0]; + end else begin + data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH]; + end + end +end + +assign s_ready = ~valid || (m_ready && count == 'h0); +assign m_valid = valid; +assign m_data = BIG_ENDIAN == 1 ? + data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] : + data[MASTER_DATA_WIDTH-1:0]; + +end +endgenerate + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_resize/xgui/util_axis_resize_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/xgui/util_axis_resize_v1_0.tcl new file mode 100644 index 000000000..5d2fe72d8 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_resize/xgui/util_axis_resize_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "BIG_ENDIAN" -parent ${Page_0} + ipgui::add_param $IPINST -name "MASTER_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "SLAVE_DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.BIG_ENDIAN { PARAM_VALUE.BIG_ENDIAN } { + # Procedure called to update BIG_ENDIAN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BIG_ENDIAN { PARAM_VALUE.BIG_ENDIAN } { + # Procedure called to validate BIG_ENDIAN + return true +} + +proc update_PARAM_VALUE.MASTER_DATA_WIDTH { PARAM_VALUE.MASTER_DATA_WIDTH } { + # Procedure called to update MASTER_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MASTER_DATA_WIDTH { PARAM_VALUE.MASTER_DATA_WIDTH } { + # Procedure called to validate MASTER_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.SLAVE_DATA_WIDTH { PARAM_VALUE.SLAVE_DATA_WIDTH } { + # Procedure called to update SLAVE_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SLAVE_DATA_WIDTH { PARAM_VALUE.SLAVE_DATA_WIDTH } { + # Procedure called to validate SLAVE_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.MASTER_DATA_WIDTH { MODELPARAM_VALUE.MASTER_DATA_WIDTH PARAM_VALUE.MASTER_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MASTER_DATA_WIDTH}] ${MODELPARAM_VALUE.MASTER_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.SLAVE_DATA_WIDTH { MODELPARAM_VALUE.SLAVE_DATA_WIDTH PARAM_VALUE.SLAVE_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SLAVE_DATA_WIDTH}] ${MODELPARAM_VALUE.SLAVE_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.BIG_ENDIAN { MODELPARAM_VALUE.BIG_ENDIAN PARAM_VALUE.BIG_ENDIAN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BIG_ENDIAN}] ${MODELPARAM_VALUE.BIG_ENDIAN} +} + |