Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

5 files changed, 1175 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd
new file mode 100644
index 000000000..322f706a4
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd
@@ -0,0 +1,223 @@
+--
+-- Copyright 2018 Ettus Research, A National Instruments Company
+--
+-- SPDX-License-Identifier: LGPL-3.0
+--
+-- Module: axi_bitq
+-- Description: Simple IP to shift bits in/out (primarily for JTAG)
+-- axi_bitq is the processor interface to the bitq_fsm module
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.bitq_fsm;
+
+entity axi_bitq is
+port (
+  bit_clk  : inout std_logic;
+  bit_in   : in    std_logic;
+  bit_out  : inout std_logic;
+  bit_stb  : inout std_logic;
+
+  S_AXI_ACLK     : in  std_logic;
+  S_AXI_ARESETN  : in  std_logic;
+  S_AXI_AWADDR   : in  std_logic_vector(3 downto 0);
+  S_AXI_AWVALID  : in  std_logic;
+  S_AXI_AWREADY  : out std_logic;
+  S_AXI_WDATA    : in  std_logic_vector(31 downto 0);
+  S_AXI_WSTRB    : in  std_logic_vector(3 downto 0);
+  S_AXI_WVALID   : in  std_logic;
+  S_AXI_WREADY   : out std_logic;
+  S_AXI_BRESP    : out std_logic_vector(1 downto 0);
+  S_AXI_BVALID   : out std_logic;
+  S_AXI_BREADY   : in  std_logic;
+  S_AXI_ARADDR   : in  std_logic_vector(3 downto 0);
+  S_AXI_ARVALID  : in  std_logic;
+  S_AXI_ARREADY  : out std_logic;
+  S_AXI_RDATA    : out std_logic_vector(31 downto 0);
+  S_AXI_RRESP    : out std_logic_vector(1 downto 0);
+  S_AXI_RVALID   : out std_logic;
+  S_AXI_RREADY   : in  std_logic
+);
+end axi_bitq;
+
+architecture arch of axi_bitq is
+  signal read_token       : std_logic;
+  signal write_addr       : std_logic_vector(3 downto 0);
+  signal write_strb       : std_logic_vector(3 downto 0);
+  signal write_addr_token : std_logic;
+  signal write_data       : std_logic_vector(31 downto 0);
+  signal write_data_token : std_logic;
+
+  signal wr_data          : std_logic_vector(31 downto 0);
+  signal stb_data         : std_logic_vector(31 downto 0);
+  signal rd_data          : std_logic_vector(31 downto 0);
+  signal prescalar        : std_logic_vector(7 downto 0);
+  signal len              : std_logic_vector(4 downto 0);
+  signal ready            : std_logic;
+  signal start            : std_logic;
+  signal bitq_rstn        : std_logic;
+  signal bitq_soft_rst    : std_logic;
+
+begin
+
+  S_AXI_ARREADY <= not read_token;
+  S_AXI_RVALID <= read_token;
+  S_AXI_RRESP <= "00";
+
+  S_AXI_AWREADY <= not write_addr_token;
+  S_AXI_WREADY <= not write_data_token;
+  S_AXI_BVALID <= write_addr_token and write_data_token;
+  S_AXI_BRESP <= "00";
+
+  --Register reads
+  read_proc : process (S_AXI_ACLK)
+    variable read_addr : std_logic_vector(S_AXI_ARADDR'left downto S_AXI_ARADDR'right+2);
+  begin
+  if rising_edge(S_AXI_ACLK) then
+    read_addr := S_AXI_ARADDR(S_AXI_ARADDR'left downto S_AXI_ARADDR'right+2);
+
+    if (S_AXI_ARESETN = '0') then
+      read_token <= '0';
+    elsif (S_AXI_ARVALID = '1') and (read_token = '0') then
+      read_token <= '1';
+    elsif (S_AXI_RREADY = '1') and (read_token = '1') then
+      read_token <= '0';
+    end if;
+
+    if (S_AXI_ARVALID = '1') and (read_token = '0') then
+      S_AXI_RDATA <= (others => '0');
+
+      case read_addr is
+      when "00" => 
+        S_AXI_RDATA(31 downto 0) <= wr_data;
+      when "01" =>
+        S_AXI_RDATA(31 downto 0) <= stb_data;
+      when "10" =>
+        S_AXI_RDATA(7 downto 0) <= prescalar;
+        S_AXI_RDATA(12 downto 8) <= len;
+        S_AXI_RDATA(31) <= ready;
+      when "11" =>
+        S_AXI_RDATA(31 downto 0) <= rd_data;
+      when others =>
+        null;
+      end case;
+
+    end if;
+  end if;
+  end process read_proc;
+
+  write_proc : process (S_AXI_ACLK)
+  begin
+  if rising_edge(S_AXI_ACLK) then
+    if (S_AXI_ARESETN = '0') then
+      write_addr_token <= '0';
+      write_data_token <= '0';
+      write_strb <= (others => '0');
+    else
+      if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then
+        write_addr_token <= '1';
+      elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then
+        write_addr_token <= '0';
+      end if;
+
+      if (S_AXI_WVALID = '1') and (write_data_token = '0') then
+        write_data_token <= '1';
+      elsif (S_AXI_BREADY = '1') and (write_addr_token = '1') and (write_data_token = '1') then
+        write_data_token <= '0';
+      end if;
+    end if;
+
+    if (S_AXI_AWVALID = '1') and (write_addr_token = '0') then
+      write_addr <= S_AXI_AWADDR;
+    end if;
+
+    if (S_AXI_WVALID = '1') and (write_data_token = '0') then
+      write_data <= S_AXI_WDATA;
+      write_strb <= S_AXI_WSTRB;
+    end if;
+  end if;
+  end process write_proc;
+
+  write_reg : process (S_AXI_ACLK)
+  begin
+  if rising_edge(S_AXI_ACLK) then
+    bitq_soft_rst <= '0';
+    start <= '0';
+
+    if (S_AXI_ARESETN = '0') or (bitq_soft_rst = '1') then
+      bitq_soft_rst <= '0';
+      start <= '0';
+    elsif (write_addr_token = '1') and (write_data_token = '1') then
+      case write_addr(write_addr'left downto 2) is
+      when "00" => 
+        if (write_strb(0) = '1') and (ready = '1') then
+          wr_data(7 downto 0) <= write_data(7 downto 0);
+        end if;
+        if (write_strb(1) = '1') and (ready = '1') then
+          wr_data(15 downto 8) <= write_data(15 downto 8);
+        end if;
+        if (write_strb(2) = '1') and (ready = '1') then
+          wr_data(23 downto 16) <= write_data(23 downto 16);
+        end if;
+        if (write_strb(3) = '1') and (ready = '1') then
+          wr_data(31 downto 24) <= write_data(31 downto 24);
+        end if;
+      when "01" => 
+        if (write_strb(0) = '1') and (ready = '1') then
+          stb_data(7 downto 0) <= write_data(7 downto 0);
+        end if;
+        if (write_strb(1) = '1') and (ready = '1') then
+          stb_data(15 downto 8) <= write_data(15 downto 8);
+        end if;
+        if (write_strb(2) = '1') and (ready = '1') then
+          stb_data(23 downto 16) <= write_data(23 downto 16);
+        end if;
+        if (write_strb(3) = '1') and (ready = '1') then
+          stb_data(31 downto 24) <= write_data(31 downto 24);
+        end if;
+      when "10" =>
+        if (write_strb(0) = '1') and (ready = '1') then
+          prescalar <= write_data(7 downto 0);
+        end if;
+        if (write_strb(1) = '1') and (ready = '1') then
+          len <= write_data(12 downto 8);
+          if (write_strb(3) = '0') or (write_data(31) = '0') then
+            start <= '1';
+          end if;
+        end if;
+        if (write_strb(3) = '1') then
+          bitq_soft_rst <= write_data(31);
+        end if;
+      when "11" => --Read only register
+        null;
+      when others =>
+        null;
+      end case;
+    end if;
+  end if;
+  end process write_reg;
+
+  bitq_rstn <= '0' when (S_AXI_ARESETN = '0') or (bitq_soft_rst = '1') else '1';
+
+  bitq_ctrl : entity bitq_fsm
+  port map (
+    clk  => S_AXI_ACLK,
+    rstn => S_AXI_ARESETN,
+    prescalar => prescalar,
+  
+    bit_clk  => bit_clk,
+    bit_in   => bit_in,
+    bit_out  => bit_out,
+    bit_stb  => bit_stb,
+    start    => start,
+    len      => len,
+    ready    => ready,
+    wr_data  => wr_data,
+    stb_data => stb_data,
+    rd_data  => rd_data
+  );
+
+end arch;
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
new file mode 100644
index 000000000..ed7ab4a50
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
@@ -0,0 +1,128 @@
+--
+-- Copyright 2018 Ettus Research, A National Instruments Company
+--
+-- SPDX-License-Identifier: LGPL-3.0
+--
+-- Module: bitq_fsm
+-- Description: Simple IP to shift bits in/out (primarily for JTAG)
+-- bitq_fsm implements the state machine underlying the IP
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bitq_fsm is
+port (
+  clk  : in std_logic;
+  rstn : in std_logic;
+  prescalar : in std_logic_vector(7 downto 0);
+
+  bit_clk  : inout std_logic;
+  bit_in   : in    std_logic;
+  bit_out  : inout std_logic;
+  bit_stb  : inout std_logic;
+  start    : in std_logic;
+  ready    : out std_logic;
+  len      : in std_logic_vector(4 downto 0);
+  wr_data  : in std_logic_vector(31 downto 0);
+  stb_data : in std_logic_vector(31 downto 0);
+  rd_data  : out std_logic_vector(31 downto 0)
+
+);
+
+end bitq_fsm;
+
+architecture arch of bitq_fsm is
+  type bitq_state_t is (IDLE, LOW, HIGH);
+  signal bitq_state : bitq_state_t;
+
+  signal bit_clk_count  : unsigned(7 downto 0);
+  signal bit_count  : unsigned(5 downto 0);
+
+  signal bit_out_r  : std_logic;
+  signal bit_stb_r  : std_logic;
+
+  signal rd_data_r  : std_logic_vector(31 downto 0);
+
+begin
+  rd_data <= rd_data_r;
+
+  gen_io : process (bitq_state, bit_count, bit_out_r, bit_stb_r)
+  begin
+    case (bitq_state) is
+    when IDLE =>
+      bit_clk <= 'Z';
+      bit_out <= 'Z';
+      bit_stb <= 'Z';
+      ready   <= '1';
+    when LOW =>
+      bit_clk <= '0';
+      bit_out <= bit_out_r;
+      bit_stb <= bit_stb_r;
+      ready <= '0';
+    when HIGH =>
+      bit_clk <= '1';
+      bit_out <= bit_out_r;
+      bit_stb <= bit_stb_r;
+      ready <= '0';
+    when others =>
+      bit_clk <= 'Z';
+      bit_out <= 'Z';
+      bit_stb <= 'Z';
+      ready   <= '1';
+    end case;
+  end process;
+
+  bit_clk_gen : process (clk)
+  begin
+  if rising_edge(clk) then
+    if (rstn = '0') or (bitq_state = IDLE) or
+       (bit_clk_count = 0) then
+      bit_clk_count <= unsigned(prescalar);
+    elsif (bit_clk_count /= 0) then
+      bit_clk_count <= bit_clk_count - 1;
+    end if;
+  end if;
+  end process bit_clk_gen;
+
+  fsm : process (clk)
+  begin
+  if rising_edge(clk) then
+    if (rstn = '0') then
+      bitq_state <= IDLE;
+      bit_count <= to_unsigned(0, bit_count'length);
+      rd_data_r <= (others => '0');
+    else
+      case bitq_state is
+      when IDLE =>
+        bit_count <= to_unsigned(0, bit_count'length);
+
+        if (start = '1') then
+          bitq_state <= LOW;
+          rd_data_r <= (others => '0');
+          bit_out_r <= wr_data(0);
+          bit_stb_r <= stb_data(0);
+        end if;
+      when LOW =>
+        if (bit_clk_count = 0) then
+          rd_data_r(to_integer(bit_count)) <= bit_in;
+          bit_count <= bit_count + 1;
+          bitq_state <= HIGH; --Rising edge
+        end if;
+      when HIGH =>
+        if (bit_clk_count = 0) then
+          if (bit_count > unsigned('0' & len)) then
+            bitq_state <= IDLE;
+          else
+            bit_out_r <= wr_data(to_integer(bit_count));
+            bit_stb_r <= stb_data(to_integer(bit_count));
+            bitq_state <= LOW; --Falling edge
+          end if;
+        end if;
+      end case;
+    end if;
+  end if;
+  end process fsm;
+
+end arch;
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml b/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml
new file mode 100644
index 000000000..2f22a5911
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/component.xml
@@ -0,0 +1,719 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>ettus.com</spirit:vendor>
+  <spirit:library>ip</spirit:library>
+  <spirit:name>axi_bitq</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_bitq_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/EttusResearch</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>axi_bitq_v1_0</xilinx:displayName>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:upgrades>
+        <xilinx:canUpgradeFrom>user.org:user:axi_bitq:1.0</xilinx:canUpgradeFrom>
+      </xilinx:upgrades>
+      <xilinx:coreCreationDateTime>2018-01-17T16:36:23Z</xilinx:coreCreationDateTime>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="nopcore"/>
+        <xilinx:tag xilinx:name="user.org:user:axi_bitq:1.0_ARCHIVE_LOCATION">usrp3/lib/vivado_ipi/axi_bitq</xilinx:tag>
+        <xilinx:tag xilinx:name="ettus.com:user:axi_bitq:1.0_ARCHIVE_LOCATION">usrp3/lib/vivado_ipi/axi_bitq</xilinx:tag>
+        <xilinx:tag xilinx:name="ettus.com:ip:axi_bitq:1.0_ARCHIVE_LOCATION">usrp3/lib/vivado_ipi/axi_bitq</xilinx:tag>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2663de75"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="da330753"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3da6ad7f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="15d3ec9b"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="0252408f"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd
new file mode 100644
index 000000000..a7bc95fe6
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/test/bitq_fsm_test.vhd
@@ -0,0 +1,95 @@
+--
+-- Copyright 2018 Ettus Research, A National Instruments Company
+--
+-- SPDX-License-Identifier: LGPL-3.0
+--
+-- Module: bitq_fsm_test
+-- Description: Manually-checked tester for bitq_fsm
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.bitq_fsm;
+
+entity bitq_fsm_test is
+end bitq_fsm_test;
+
+architecture sim of bitq_fsm_test is
+  signal clk  : std_logic := '0';
+  signal rstn : std_logic;
+
+  signal wr_data   : std_logic_vector(31 downto 0);
+  signal stb_data  : std_logic_vector(31 downto 0);
+  signal rd_data   : std_logic_vector(31 downto 0);
+  signal prescalar : std_logic_vector(7 downto 0);
+  signal len       : std_logic_vector(4 downto 0);
+  signal ready     : std_logic;
+  signal start     : std_logic;
+
+  signal bit_clk : std_logic;
+  signal bit_in : std_logic;
+  signal bit_out : std_logic;
+  signal bit_stb : std_logic;
+
+  constant HALFCYCLE : time := 5 ns;
+  constant CYCLE : time := 2*HALFCYCLE;
+
+begin
+
+  process
+  begin
+    wait for HALFCYCLE;
+    clk <= not clk;
+  end process;
+
+  process
+  begin
+    rstn <= '0';
+    start <= '0';
+    len <= "11111";
+    bit_in <= '0';
+    prescalar <= X"02";
+    wait for CYCLE;
+    rstn <= '1';
+    wait for CYCLE;
+    wr_data <= X"ABCDEF01";
+    stb_data <= X"FF7F7700";
+    wait for CYCLE;
+    start <= '1';
+    wait for CYCLE;
+    start <= '0';
+    wait until ready = '1';
+    wait for CYCLE;
+    start <= '1';
+    wait for CYCLE;
+    start <= '0';
+    bit_in <= '1';
+    wait until ready = '1';
+    wait for CYCLE;
+    bit_in <= '0';
+    wait for CYCLE;
+    report "End of Test";
+  end process;
+
+  dut : entity work.bitq_fsm
+  port map (
+    clk  => clk,
+    rstn => rstn,
+    prescalar => prescalar,
+  
+    bit_clk  => bit_clk,
+    bit_in   => bit_in,
+    bit_out  => bit_out,
+    bit_stb  => bit_stb,
+    start    => start,
+    len      => len,
+    ready    => ready,
+    wr_data  => wr_data,
+    stb_data => stb_data,
+    rd_data  => rd_data
+  );
+
+end sim;
+
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl
new file mode 100644
index 000000000..0db18e9a9
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/xgui/axi_bitq_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+