Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

17 files changed, 2286 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_pipe/axi_pipe_tb.v b/fpga/usrp3/lib/sim/rfnoc/axi_pipe/axi_pipe_tb.v
new file mode 100644
index 000000000..b84657b07
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_pipe/axi_pipe_tb.v
@@ -0,0 +1,74 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_pipe_tb;
+
+   initial $dumpfile("axi_pipe_tb.vcd");
+   initial $dumpvars(0,axi_pipe_tb);
+
+   reg clk = 0;
+   always #100 clk <= ~clk;
+   reg reset = 1;
+   initial #1000 @(posedge clk) reset <= 1'b0;
+   initial #30000 $finish;
+   
+   localparam LEN=10;
+   wire [LEN-1:0] enables, valids;
+
+   wire 	  o_tlast, i_tready, o_tvalid;
+   reg 		  i_tvalid = 0;
+   reg 		  o_tready = 0;
+   reg 		  i_tlast = 0;
+   
+   axi_pipe #(.STAGES(LEN)) axi_pipe
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .enables(enables), .valids(valids));
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (3)
+	  @(posedge clk);
+	i_tvalid <= 1;
+	@(posedge clk);
+	i_tvalid <= 0;
+	repeat (15) @(posedge clk);
+	@(posedge clk);
+	o_tready <= 1;
+	repeat (15) @(posedge clk);
+	o_tready <= 0;
+	i_tvalid <= 1;
+	repeat (15) @(posedge clk);
+	o_tready <= 1;
+	i_tvalid <= 0;
+	repeat (15) @(posedge clk);
+	o_tready <= 0;
+	i_tvalid <= 1;
+	@(posedge clk);
+	i_tvalid <= 0;
+	@(posedge clk);
+	i_tvalid <= 1;
+	@(posedge clk);
+	@(posedge clk);
+	i_tlast <= 1;
+	@(posedge clk);
+	i_tvalid <= 0;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	o_tready <= 1;
+
+     end
+   
+endmodule // axi_pipe
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/Makefile b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/Makefile
new file mode 100644
index 000000000..fcf21b755
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/Makefile
@@ -0,0 +1,37 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = axi_rate_change_tb
+
+# Add test bench, user design under test, and
+# additional user created files
+SIM_SRCS = $(abspath \
+axi_rate_change_tb.sv \
+$(LIB_DIR)/control/ram_2port.v \
+$(LIB_DIR)/fifo/axi_packet_gate.v \
+$(LIB_DIR)/rfnoc/axi_rate_change.v \
+$(LIB_DIR)/rfnoc/axi_drop_partial_packet.v \
+)
+
+MODELSIM_USER_DO = $(abspath wave.do)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/axi_rate_change_tb.sv b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/axi_rate_change_tb.sv
new file mode 100644
index 000000000..b16c2d26d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/axi_rate_change_tb.sv
@@ -0,0 +1,323 @@
+`timescale 1ns/1ps
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 4
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+`include "sim_cvita_lib.svh"
+`include "sim_axis_lib.svh"
+`include "sim_set_rb_lib.svh"
+
+module axi_rate_change_tb();
+  `TEST_BENCH_INIT("axi_rate_change_tb",`NUM_TEST_CASES,`NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(reset, 0, 100);
+
+  localparam SR_N_ADDR      = 0;
+  localparam SR_M_ADDR      = 1;
+  localparam SR_CONFIG_ADDR = 2;
+  localparam MAX_N = 16;
+  localparam MAX_M = 16;
+
+  logic [15:0] src_sid = 16'h0000;
+  logic [15:0] dst_sid = 16'h0010;
+  settings_bus_master sb (.clk(clk));
+  axis_master #(.DWIDTH(32+128)) m_axis (.clk(clk));
+  axis_slave #(.DWIDTH(32+128)) s_axis (.clk(clk));
+  logic clear, clear_user;
+  logic [31:0] m_axis_data_tdata, s_axis_data_tdata;
+  logic m_axis_data_tlast, m_axis_data_tvalid, m_axis_data_tready;
+  logic s_axis_data_tlast, s_axis_data_tvalid, s_axis_data_tready;
+  logic warning_long_throttle, error_extra_outputs, error_drop_pkt_lockup;
+  axi_rate_change #(
+    .WIDTH(32),
+    .MAX_N(MAX_N),
+    .MAX_M(MAX_M),
+    .SR_N_ADDR(SR_N_ADDR),
+    .SR_M_ADDR(SR_M_ADDR),
+    .SR_CONFIG_ADDR(SR_CONFIG_ADDR))
+  axi_rate_change (
+    .clk(clk), .reset(reset), .clear(clear), .clear_user(clear_user),
+    .src_sid(src_sid), .dst_sid(dst_sid),
+    .set_stb(sb.settings_bus.set_stb), .set_addr(sb.settings_bus.set_addr), .set_data(sb.settings_bus.set_data),
+    .i_tdata(m_axis.axis.tdata[31:0]), .i_tlast(m_axis.axis.tlast), .i_tvalid(m_axis.axis.tvalid), .i_tready(m_axis.axis.tready), .i_tuser(m_axis.axis.tdata[159:32]),
+    .o_tdata(s_axis.axis.tdata[31:0]), .o_tlast(s_axis.axis.tlast), .o_tvalid(s_axis.axis.tvalid), .o_tready(s_axis.axis.tready), .o_tuser(s_axis.axis.tdata[159:32]),
+    .m_axis_data_tdata(m_axis_data_tdata), .m_axis_data_tlast(m_axis_data_tlast),
+    .m_axis_data_tvalid(m_axis_data_tvalid), .m_axis_data_tready(m_axis_data_tready),
+    .s_axis_data_tdata(s_axis_data_tdata), .s_axis_data_tlast(s_axis_data_tlast),
+    .s_axis_data_tvalid(s_axis_data_tvalid), .s_axis_data_tready(s_axis_data_tready),
+    .warning_long_throttle(warning_long_throttle),
+    .error_extra_outputs(error_extra_outputs),
+    .error_drop_pkt_lockup(error_drop_pkt_lockup));
+
+  // Simulate user logic that can handle various decimation / interpolation rates
+  // - Generates a word count sequence that is checked in the test_rate() task.
+  // - Introduces a single clock cycle delay which is useful for testing that
+  //   the DUT is not reliant on user logic having a large built in delay.
+  integer rate_n, rate_m, count_n, count_m, count_in, count_out;
+  always @(posedge clk) begin
+    if (reset | clear_user | clear) begin
+      s_axis_data_tlast  <= 1'b0;
+      count_n            <= 1;
+      count_m            <= 1;
+      count_in           <= 0;
+      count_out          <= 0;
+    end else begin
+      // Rate change = N/M
+      if (m_axis_data_tvalid & m_axis_data_tready) begin
+        if (count_n == rate_n) begin
+          count_n        <= 1;
+          count_in       <= count_in + 1;
+        end else begin
+          count_n        <= count_n + 1;
+        end
+      end
+      if (count_in != count_out) begin
+        if (s_axis_data_tvalid & s_axis_data_tready) begin
+          if (count_m == rate_m) begin
+            count_m          <= 1;
+            count_out        <= count_out + 1;
+          end else begin
+            count_m          <= count_m + 1;
+          end
+        end
+      end
+    end
+  end
+
+  assign s_axis_data_tdata  = {count_out[15:0], count_m[15:0]};
+  assign s_axis_data_tvalid = (count_in != count_out);
+  assign m_axis_data_tready = s_axis_data_tready;
+
+  // Used with test 3 to count output clock cycles
+  int clock_cnt;
+  logic clock_cnt_en = 1'b0;
+  logic clock_cnt_start = 1'b0;
+  always @(posedge clk) begin
+    if (clock_cnt_en == 1'b1) begin
+      // Wait until output data starts
+      if (s_axis.axis.tvalid & ~clock_cnt_start) begin
+        clock_cnt_start <= 1'b1;
+        clock_cnt       <= clock_cnt + 1;
+      end else if (clock_cnt_start) begin
+        clock_cnt       <= clock_cnt + 1;
+      end
+    end else begin
+      clock_cnt_start <= 1'b0;
+      clock_cnt       <= 0;
+    end
+  end
+
+  /********************************************************
+  ** Verification
+  ********************************************************/
+  task random_wait(int unsigned min_cycles, int unsigned max_cycles);
+    begin
+      int unsigned num_cycles;
+      do begin
+        num_cycles = $random() & (2**($clog2(max_cycles))-1);
+      end while ((num_cycles < min_cycles) || (num_cycles > max_cycles));
+
+      if (num_cycles != 0) begin
+        for (int unsigned i = 0; i < num_cycles; i++) begin
+          @(posedge clk);
+        end
+        @(negedge clk); // Realign with negedge
+      end
+    end
+  endtask
+
+  task test_rate(int n, int m, int num_words, int spp = 16, bit rand_delay_in = 0, bit rand_delay_out = 0);
+    begin
+      clear = 1'b1;
+      @(posedge clk);
+      @(posedge clk);
+      clear = 1'b0;
+      @(posedge clk);
+      @(posedge clk);
+      rate_n = n;
+      rate_m = m;
+      sb.write(SR_N_ADDR, n);
+      sb.write(SR_M_ADDR, m);
+      @(posedge clk);
+      fork
+      begin
+        cvita_hdr_t send_header;
+        int words_left_to_send, words_to_send;
+        logic [31:0] words_sent;
+        real timestamp;
+        timestamp = 0.0;
+        words_sent = 0;
+        words_left_to_send = num_words;
+
+        while (words_left_to_send > 0) begin
+          // Setup header
+          send_header = '{default:0};
+          send_header.has_time = 1;
+          send_header.timestamp = longint'(timestamp);
+          send_header.eob = (words_left_to_send <= spp);
+          if (words_left_to_send >= spp) begin
+            send_header.length = 16+4*spp;
+            words_to_send = spp;
+            words_left_to_send -= spp;
+          end else begin
+            send_header.length = 16+4*words_left_to_send;
+            words_to_send = words_left_to_send;
+            words_left_to_send = 0;
+          end
+          // Send packet
+          for (int i = 0; i < words_to_send; i++) begin
+            if (rand_delay_in) random_wait(0,2*spp);
+            m_axis.push_word({send_header,words_sent + i},i == words_to_send-1);
+          end
+          words_sent += words_to_send;
+          // Update seq num, timestamp
+          send_header.seqnum++;
+          timestamp += (1.0*m/n)*words_to_send;
+        end
+      end
+      begin
+        string s;
+        cvita_hdr_t recv_header;
+        logic last, expected_eob;
+        real timestamp;
+        logic [63:0] expected_timestamp;
+        logic [31:0] word;
+        logic [15:0] word_cnt_div_m, word_cnt_div_m_frac;
+        logic [15:0] word_cnt_div_spp_frac;
+        int words_left_to_recv, words_recvd;
+        timestamp = 0.0;
+        expected_timestamp = 0; // Timestamp starts at 0
+        word_cnt_div_spp_frac = 0;
+        word_cnt_div_m = 0;
+        word_cnt_div_m_frac = 0;
+        words_recvd = 0;
+        words_left_to_recv = $floor(num_words/n)*m; // Order matters!
+
+        while (words_left_to_recv > 0) begin
+          s_axis.pull_word({recv_header,word},last);
+          word_cnt_div_spp_frac++;
+          word_cnt_div_m_frac++;
+          words_recvd++;
+          words_left_to_recv--;
+          timestamp += 1.0*n;
+          // Check packet length
+          if ((word_cnt_div_spp_frac == spp) || (words_left_to_recv == 0)) begin
+            `ASSERT_FATAL(last == 1, "Incorrect packet length! Last not asserted!");
+            word_cnt_div_spp_frac = 0;
+          end else begin
+            $sformat(s, "Incorrect packet length! Expected: %0d, Actual %0d", spp, words_recvd);
+            `ASSERT_FATAL(last == 0, s);
+          end
+          // Check for EOB
+          if (last) begin
+            words_recvd = 0;
+            expected_eob = (words_left_to_recv == 0);
+            $sformat(s, "Incorrect EOB state! Expected: %0d, Actual %0d", expected_eob, recv_header.eob);
+            `ASSERT_FATAL(recv_header.eob == expected_eob, s);
+          end
+          // Check timestamp
+          if (last) begin
+            $sformat(s, "Incorrect timestamp! Expected: %0d, Actual %0d", expected_timestamp, recv_header.timestamp);
+            `ASSERT_FATAL(recv_header.timestamp == expected_timestamp, s);
+            expected_timestamp = longint'(timestamp);
+          end
+          // Check word
+          $sformat(s, "Incorrect packet data! Expected: 0x%08h, Actual: 0x%08h", {word_cnt_div_m, word_cnt_div_m_frac}, word);
+          `ASSERT_FATAL(((word[31:16] == word_cnt_div_m) && (word[15:0] == word_cnt_div_m_frac)), s);
+          // Track number of received words, do at end of loop
+          if (word_cnt_div_m_frac == m) begin
+            word_cnt_div_m_frac = 0;
+            word_cnt_div_m++;
+          end
+        end
+      end
+      join
+    end
+  endtask
+
+  initial begin : tb_main
+    string s;
+    cvita_hdr_t tmp_header;
+    logic [63:0] word;
+    logic last;
+    integer spp, number_words;
+    spp = 16;
+
+    /********************************************************
+    ** Test 1 -- Reset
+    ********************************************************/
+    `TEST_CASE_START("Wait for Reset");
+    sb.reset();
+    m_axis.reset();
+    s_axis.reset();
+    while (reset) @(posedge clk);
+    `TEST_CASE_DONE(~reset);
+
+    /********************************************************
+    ** Test 2 -- Test various rates
+    ** - Try many decimation / interpolation rates (including 
+    **   fractional rates) and use randomized delays.
+    ********************************************************/
+    `TEST_CASE_START("Check various rates");
+    for (int _n = 1; _n <= MAX_N; _n++) begin
+      for (int _m = 1; _m <= MAX_M; _m++) begin
+        $display("Testing rate %0d:%0d", _n, _m);
+        test_rate(_n, _m, _n*spp*3, spp, 1, 1);
+      end
+    end
+    `TEST_CASE_DONE(1);
+
+    #2000; // Delay to make the tests visually distinct in waveform viewer
+
+    /********************************************************
+    ** Test 3 -- Test partial packets
+    ** - Send packets with extra data that is less than SPP.
+    **   Module should output the maximum number of samples
+    **   possible while dropping the "partial" sample.
+    ********************************************************/
+    `TEST_CASE_START("Test partial packets");
+    for (int _n = 1; _n <= MAX_N; _n++) begin
+      for (int _m = 1; _m <= MAX_M; _m++) begin
+        $display("Testing rate %0d:%0d", _n, _m);
+        test_rate(_n, _m, _n*spp + spp-1, spp, 1, 1);
+      end
+    end
+    `TEST_CASE_DONE(1);
+
+    #2000;
+
+    /********************************************************
+    ** Test 3 -- Test for bubble states
+    ** - Send many packets at full rate and make sure number
+    **   of input clock cycles == output clock cycles. If
+    **   they do not match, then the module likely has
+    **   bubble states that would prevent it from running
+    **   continuously at full rate.
+    ********************************************************/
+    `TEST_CASE_START("Test for bubble states");
+    clock_cnt_en = 1'b1;
+    number_words = 100000;
+    test_rate(1, 1, number_words, spp, 0, 0);
+    $sformat(s, "Incorrect number of clock cycles -- Possible bubble states detected! Expected: %0d, Actual: %0d", number_words, clock_cnt);
+    `ASSERT_FATAL(clock_cnt == number_words, s);
+    clock_cnt_en = 1'b0;
+    `TEST_CASE_DONE(1);
+
+    `TEST_BENCH_DONE;
+
+  end
+
+  // The warning, error signals should never assert.
+  initial begin
+    while (reset) @(posedge clk);
+    forever begin
+      @(posedge clk);
+      `ASSERT_FATAL(~warning_long_throttle,    "Throttle state deadlock!");
+      `ASSERT_FATAL(~error_extra_outputs,      "Extra outputs detected!");
+      `ASSERT_FATAL(~error_drop_pkt_lockup,    "Drop packet deadlock!");
+    end
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/wave.do b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/wave.do
new file mode 100644
index 000000000..f16b9d5a7
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/wave.do
@@ -0,0 +1,115 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/clk
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/reset
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/clear
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/clear_user
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/active
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tuser
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_frac
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/in_pkt_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tuser
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/out_payload_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/payload_length_out
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_m
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/first_pkt_out
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_out
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_accum
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_reg
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/header_fifo_out_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/header_fifo_out_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tuser
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tuser
+add wave -noupdate -divider {AXI Drop Partial Packet}
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_terror
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tlast_int
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/in_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/large_pkt
+add wave -noupdate {/axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tdata[32]}
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/small_pkt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/flush
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/hold_last_sample
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/in_pkt_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/out_pkt_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/release_due_to_error
+add wave -noupdate -divider {AXI Drop Packet}
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/hold
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_terror
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/empty
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/full
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/rd_addr
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/wr_addr
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/in_pkt_cnt
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tlast
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/mem
+add wave -noupdate -radix hexadecimal /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tdata
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tvalid
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tready
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tlast
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/out_pkt_cnt
+add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/prev_wr_addr
+add wave -noupdate /axi_rate_change_tb/axi_rate_change/n
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1112517 ps} 0} {{Cursor 2} {1974349848 ps} 0}
+quietly wave cursor active 2
+configure wave -namecolwidth 633
+configure wave -valuecolwidth 184
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1974303474 ps} {1974374671 ps}
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/axi_wrapper_tb.v b/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/axi_wrapper_tb.v
new file mode 100644
index 000000000..7a15d1d86
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/axi_wrapper_tb.v
@@ -0,0 +1,144 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module axi_wrapper_tb();
+   
+   xlnx_glbl glbl (.GSR(),.GTS());
+   
+   localparam STR_SINK_FIFOSIZE = 9;
+      
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("axi_wrapper_tb.vcd");
+   initial $dumpvars(0,axi_wrapper_tb);
+
+   initial #1000000 $finish;
+
+   wire [31:0] set_data;
+   wire [7:0]  set_addr;
+   wire        set_stb;
+
+   wire [63:0] noci_tdata[PORTS-1:0];
+   wire        noci_tlast[PORTS-1:0];
+   wire        noci_tvalid[PORTS-1:0];
+   wire        noci_tready[PORTS-1:0];
+
+   wire [63:0] noco_tdata[PORTS-1:0];
+   wire        noco_tlast[PORTS-1:0];
+   wire        noco_tvalid[PORTS-1:0];
+   wire        noco_tready[PORTS-1:0];
+
+   reg [63:0]  src_tdata;
+   reg 	       src_tlast, src_tvalid;
+   wire        src_tready;
+
+   localparam PORTS = 4;
+
+   wire [63:0] s1o_tdata, s1i_tdata;
+   wire        s1o_tlast, s1i_tlast, s1o_tvalid, s1i_tvalid, s1o_tready, s1i_tready;
+   
+   wire [31:0] pre_tdata, post_tdata;
+   wire        pre_tlast, post_tlast, pre_tvalid, post_tvalid, pre_tready, post_tready;
+   wire [127:0] pre_tuser, post_tuser;
+      
+   axi_wrapper #(.BASE(8), .NUM_AXI_CONFIG_BUS(1), .CONFIG_BUS_FIFO_DEPTH(5), .SIMPLE_MODE(1)) axi_wrapper_ce1
+     (.clk(clk), .reset(reset),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .i_tdata(src_tdata), .i_tlast(src_tlast), .i_tvalid(src_tvalid), .i_tready(src_tready),
+      .o_tdata(s1i_tdata), .o_tlast(s1i_tlast), .o_tvalid(s1i_tvalid), .o_tready(s1i_tready),
+      .m_axis_data_tdata(pre_tdata),
+      .m_axis_data_tuser(pre_tuser),
+      .m_axis_data_tlast(pre_tlast),
+      .m_axis_data_tvalid(pre_tvalid),
+      .m_axis_data_tready(pre_tready),
+      .s_axis_data_tdata(post_tdata),
+      .s_axis_data_tuser(post_tuser),
+      .s_axis_data_tlast(post_tlast),
+      .s_axis_data_tvalid(post_tvalid),
+      .s_axis_data_tready(post_tready)
+      );
+
+   axi_fifo #(.WIDTH(33)) afifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({pre_tlast,pre_tdata}), .i_tvalid(pre_tvalid), .i_tready(pre_tready),
+      .o_tdata({post_tlast,post_tdata}), .o_tvalid(post_tvalid), .o_tready(post_tready));
+
+   assign s1i_tready = 1'b1;
+   
+
+   task SendPacket;
+      input [3:0]  flags;
+      input [11:0] seqnum;
+      input [15:0] len;
+      input [31:0] sid;
+      input [63:0] data;
+      
+      begin
+	 @(posedge clk);
+	 src_tdata <= { flags, seqnum, len+16'd8 + (flags[1] ? 16'd8 : 16'd0), sid };
+	 src_tlast <= 0;
+	 src_tvalid <= 1;
+	 @(posedge clk);
+	 while(~src_tready)
+	   @(posedge clk);
+
+	 // send time if flags request it
+	 if(flags[1])
+	   begin
+	      src_tdata <= 64'h0123_4567_89ab_cdef;
+	      src_tlast <= 0;
+	      src_tvalid <= 1;
+	      @(posedge clk);
+	      while(~src_tready)
+		@(posedge clk);
+	   end
+
+	 src_tdata <= data;
+	 repeat(len[15:3] + (len[2]|len[1]|len[0])- 1 )
+	   begin
+	      @(posedge clk);
+	      while(~src_tready)
+		@(posedge clk);
+	      src_tdata <= src_tdata + 64'd1;
+	   end
+	 src_tlast <= 1;
+	 @(posedge clk);
+	 while(~src_tready)
+	   @(posedge clk);
+	 src_tvalid <= 0;
+	 @(posedge clk);
+      end
+   endtask // SendPacket
+   
+   initial
+     begin
+	src_tdata <= 64'd0;
+	src_tlast <= 1'b0;
+	src_tvalid <= 1'b0;
+	@(negedge reset);
+	@(posedge clk);
+	
+	@(posedge clk);
+
+	#10000;
+	SendPacket(4'h0, 12'd7, 16'd64, 32'h0002_0003, 64'hAAAA_AAAA_0000_0000); // data packet
+	SendPacket(4'h0, 12'd8, 16'd68, 32'h0004_0005, 64'hBBBB_BBBB_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd2, 16'd8, 32'h0000_0001, 64'hCCCC_CCCC_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd3, 16'd8, 32'h0000_0001, 64'hDDDD_DDDD_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd4, 16'd8, 32'h0000_0001, 64'hEEEE_EEEE_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd5, 16'd8, 32'h0000_0001, 64'hFFFF_FFFF_0000_0000); // data packet
+	//SendPacket(4'h0, 12'd6, 16'd8, 32'h0000_0001, 64'h2222_2222_0000_0000); // data packet
+     end
+
+endmodule // axi_wrapper_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/build_axi_wrapper_tb b/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/build_axi_wrapper_tb
new file mode 100755
index 000000000..49b8fe312
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/axi_wrapper/build_axi_wrapper_tb
@@ -0,0 +1 @@
+iverilog -o axi_wrapper_tb axi_wrapper_tb.v -y . -y ../control/ -y ../fifo/ -y /opt/Xilinx/14.6/ISE_DS/ISE/verilog/src/unisims/ -y ../packet_proc/ -y ../timing/ -y ../vita/ -y ../../top/x300/coregen -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib -y ../coregen/ -y ../ -y ../../../usrp2/models/ -Wall
diff --git a/fpga/usrp3/lib/sim/rfnoc/chdr_deframer/chdr_deframer_tb.v b/fpga/usrp3/lib/sim/rfnoc/chdr_deframer/chdr_deframer_tb.v
new file mode 100644
index 000000000..312ca478d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/chdr_deframer/chdr_deframer_tb.v
@@ -0,0 +1,87 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//`timescale 1ns
+module chdr_deframer_tb();
+   
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial $dumpfile("chdr_deframer_tb.vcd");
+   initial $dumpvars(0,chdr_deframer_tb);
+
+   reg [63:0] i_tdata;
+   reg i_tlast, i_tvalid;
+   wire i_tready;
+
+   wire [31:0] o_tdata;
+   wire [127:0] o_tuser;
+   wire        o_tlast, o_tvalid;
+
+   reg 	       o_tready = 1;
+
+   wire [63:0] int_tdata;
+   wire        int_tlast, int_tvalid, int_tready;
+   
+   axi_fifo #(.SIZE(10), .WIDTH(65)) fifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready));
+   
+   chdr_deframer chdr_deframer
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tdata(int_tdata), .i_tlast(int_tlast), .i_tvalid(int_tvalid), .i_tready(int_tready),
+      .o_tdata(o_tdata), .o_tuser(o_tuser), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   reg [63:0]  hdr, vtime, data;
+   
+   initial
+     begin
+	clk = 0;
+	reset = 1;
+	i_tlast = 0;
+	i_tvalid = 0;
+	hdr = 64'hFF00_AAB9_BEEF_0000;
+	vtime = 64'h8888_7777_6666_0000;
+	data = 64'hEEEE_0000_FFFF_0001;
+	#1000 reset = 0;
+	repeat (10)
+	  @(posedge clk);
+	repeat (6)
+	  begin
+	     #1 i_tdata = hdr;
+	     #1 i_tlast = 0;
+	     #1 i_tvalid = 1;
+	     @(posedge clk);
+	     #1 i_tdata = vtime;
+	     @(posedge clk);
+	     #1 hdr = hdr + 1;
+	     #1 vtime = vtime + 1;
+	     repeat (10)
+	       begin
+		  #1 i_tdata = data;
+		  #1 data = data + 64'h0000_0002_0000_0002;
+		  @(posedge clk);
+	       end
+	     #1 i_tdata = data;
+	     #1 data = data + 64'h0000_0002_0000_0002;
+	     #1 i_tlast <= 1;
+	     @(posedge clk);
+	  end // repeat (20)
+	#1 i_tvalid <= 0;
+	#200000 $finish;
+     end
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       if(o_tlast)
+	 $display("%x    LAST",o_tdata);
+       else
+	 $display("%x",o_tdata);
+   
+endmodule // chdr_deframer_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/chdr_framer/chdr_framer_tb.v b/fpga/usrp3/lib/sim/rfnoc/chdr_framer/chdr_framer_tb.v
new file mode 100644
index 000000000..71b507e35
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/chdr_framer/chdr_framer_tb.v
@@ -0,0 +1,80 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+//`timescale 1ns
+module chdr_framer_tb();
+   
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial $dumpfile("chdr_framer_tb.vcd");
+   initial $dumpvars(0,chdr_framer_tb);
+
+   reg [31:0] i_tdata;
+   reg [127:0] i_tuser;
+   reg i_tlast, i_tvalid;
+   wire i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid;
+
+   reg 	       o_tready = 0;
+   
+   chdr_framer #(.SIZE(10)) chdr_framer
+     (.clk(clk), .reset(reset), .clear(0),
+      .i_tdata(i_tdata), .i_tuser(i_tuser), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   always 
+     begin
+	#1 o_tready = 1;
+	repeat (200)
+	  @(posedge clk);
+	#1 o_tready = 0;
+	repeat (120)
+	  @(posedge clk);
+     end
+		   
+	    
+   initial
+     begin
+	clk = 0;
+	reset = 1;
+	i_tlast = 0;
+	i_tvalid = 0;
+	i_tdata = 32'hBEEF_0000;
+	i_tuser = 128'hF123_4567_89ab_cdef_0011_2233_4455_0000;
+	#1000 reset = 0;
+	repeat (10)
+	  @(posedge clk);
+	#1 i_tvalid = 1;
+	repeat (400)
+	  begin
+	     #1 i_tlast = 0;
+	     repeat (22)
+	       begin
+		  #1 i_tdata = i_tdata + 1;
+		  @(posedge clk);
+	       end
+	     #1 i_tdata = i_tdata + 1;
+	     #1 i_tlast = 1;
+	     @(posedge clk);
+	     #1 i_tuser <= i_tuser + 1;
+	  end // repeat (20)
+	#1 i_tvalid <= 0;
+	#100000 $finish;
+     end
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       if(o_tlast)
+	 $display("%x    LAST",o_tdata);
+       else
+	 $display("%x",o_tdata);
+   
+endmodule // chdr_framer_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/display_samples.grc b/fpga/usrp3/lib/sim/rfnoc/display_samples.grc
new file mode 100644
index 000000000..d900da4cc
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/display_samples.grc
@@ -0,0 +1,413 @@
+<?xml version='1.0' encoding='ASCII'?>
+<flow_graph>
+  <timestamp>Wed May 28 15:07:06 2014</timestamp>
+  <block>
+    <key>options</key>
+    <param>
+      <key>id</key>
+      <value>top_block</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value></value>
+    </param>
+    <param>
+      <key>author</key>
+      <value></value>
+    </param>
+    <param>
+      <key>description</key>
+      <value></value>
+    </param>
+    <param>
+      <key>window_size</key>
+      <value>1280, 1024</value>
+    </param>
+    <param>
+      <key>generate_options</key>
+      <value>wx_gui</value>
+    </param>
+    <param>
+      <key>category</key>
+      <value>Custom</value>
+    </param>
+    <param>
+      <key>run_options</key>
+      <value>prompt</value>
+    </param>
+    <param>
+      <key>run</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>max_nouts</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>realtime_scheduling</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(10, 10)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>variable</key>
+    <param>
+      <key>id</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>value</key>
+      <value>32000</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(10, 170)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_interleaved_short_to_complex</key>
+    <param>
+      <key>id</key>
+      <value>blocks_interleaved_short_to_complex_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>vector_input</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(296, 296)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_throttle</key>
+    <param>
+      <key>id</key>
+      <value>blocks_throttle_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>samples_per_second</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>vlen</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>ignoretag</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(524, 220)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_file_source</key>
+    <param>
+      <key>id</key>
+      <value>blocks_file_source_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>file</key>
+      <value>output.dat</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>short</value>
+    </param>
+    <param>
+      <key>repeat</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>vlen</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(165, 203)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>wxgui_fftsink2</key>
+    <param>
+      <key>id</key>
+      <value>wxgui_fftsink2_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value>FFT Plot</value>
+    </param>
+    <param>
+      <key>samp_rate</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>baseband_freq</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>y_per_div</key>
+      <value>10</value>
+    </param>
+    <param>
+      <key>y_divs</key>
+      <value>10</value>
+    </param>
+    <param>
+      <key>ref_level</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>ref_scale</key>
+      <value>2.0</value>
+    </param>
+    <param>
+      <key>fft_size</key>
+      <value>1024</value>
+    </param>
+    <param>
+      <key>fft_rate</key>
+      <value>15</value>
+    </param>
+    <param>
+      <key>peak_hold</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>average</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>avg_alpha</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>win</key>
+      <value>None</value>
+    </param>
+    <param>
+      <key>win_size</key>
+      <value></value>
+    </param>
+    <param>
+      <key>grid_pos</key>
+      <value></value>
+    </param>
+    <param>
+      <key>notebook</key>
+      <value></value>
+    </param>
+    <param>
+      <key>freqvar</key>
+      <value>None</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(751, 242)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>wxgui_scopesink2</key>
+    <param>
+      <key>id</key>
+      <value>wxgui_scopesink2_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value>Scope Plot</value>
+    </param>
+    <param>
+      <key>samp_rate</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>v_scale</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>v_offset</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>t_scale</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>ac_couple</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>xy_mode</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>num_inputs</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>win_size</key>
+      <value></value>
+    </param>
+    <param>
+      <key>grid_pos</key>
+      <value></value>
+    </param>
+    <param>
+      <key>notebook</key>
+      <value></value>
+    </param>
+    <param>
+      <key>trig_mode</key>
+      <value>wxgui.TRIG_MODE_AUTO</value>
+    </param>
+    <param>
+      <key>y_axis_label</key>
+      <value>Counts</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(750, 134)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <connection>
+    <source_block_id>blocks_file_source_0</source_block_id>
+    <sink_block_id>blocks_interleaved_short_to_complex_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_interleaved_short_to_complex_0</source_block_id>
+    <sink_block_id>blocks_throttle_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_throttle_0</source_block_id>
+    <sink_block_id>wxgui_scopesink2_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_throttle_0</source_block_id>
+    <sink_block_id>wxgui_fftsink2_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+</flow_graph>
diff --git a/fpga/usrp3/lib/sim/rfnoc/gen_samples.grc b/fpga/usrp3/lib/sim/rfnoc/gen_samples.grc
new file mode 100644
index 000000000..568c538ba
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/gen_samples.grc
@@ -0,0 +1,381 @@
+<?xml version='1.0' encoding='ASCII'?>
+<flow_graph>
+  <timestamp>Wed May 28 15:55:45 2014</timestamp>
+  <block>
+    <key>options</key>
+    <param>
+      <key>id</key>
+      <value>top_block</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value></value>
+    </param>
+    <param>
+      <key>author</key>
+      <value></value>
+    </param>
+    <param>
+      <key>description</key>
+      <value></value>
+    </param>
+    <param>
+      <key>window_size</key>
+      <value>1280, 1024</value>
+    </param>
+    <param>
+      <key>generate_options</key>
+      <value>wx_gui</value>
+    </param>
+    <param>
+      <key>category</key>
+      <value>Custom</value>
+    </param>
+    <param>
+      <key>run_options</key>
+      <value>prompt</value>
+    </param>
+    <param>
+      <key>run</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>max_nouts</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>realtime_scheduling</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(10, 10)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>variable</key>
+    <param>
+      <key>id</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>value</key>
+      <value>32000</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(10, 170)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_complex_to_interleaved_short</key>
+    <param>
+      <key>id</key>
+      <value>blocks_complex_to_interleaved_short_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(631, 265)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_file_sink</key>
+    <param>
+      <key>id</key>
+      <value>blocks_file_sink_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>file</key>
+      <value>test.dat</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>short</value>
+    </param>
+    <param>
+      <key>vlen</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>unbuffered</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>append</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(769, 142)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>wxgui_fftsink2</key>
+    <param>
+      <key>id</key>
+      <value>wxgui_fftsink2_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>title</key>
+      <value>FFT Plot</value>
+    </param>
+    <param>
+      <key>samp_rate</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>baseband_freq</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>y_per_div</key>
+      <value>10</value>
+    </param>
+    <param>
+      <key>y_divs</key>
+      <value>10</value>
+    </param>
+    <param>
+      <key>ref_level</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>ref_scale</key>
+      <value>2.0</value>
+    </param>
+    <param>
+      <key>fft_size</key>
+      <value>1024</value>
+    </param>
+    <param>
+      <key>fft_rate</key>
+      <value>15</value>
+    </param>
+    <param>
+      <key>peak_hold</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>average</key>
+      <value>False</value>
+    </param>
+    <param>
+      <key>avg_alpha</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>win</key>
+      <value>None</value>
+    </param>
+    <param>
+      <key>win_size</key>
+      <value></value>
+    </param>
+    <param>
+      <key>grid_pos</key>
+      <value></value>
+    </param>
+    <param>
+      <key>notebook</key>
+      <value></value>
+    </param>
+    <param>
+      <key>freqvar</key>
+      <value>None</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(626, 319)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>blocks_throttle</key>
+    <param>
+      <key>id</key>
+      <value>blocks_throttle_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>samples_per_second</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>vlen</key>
+      <value>1</value>
+    </param>
+    <param>
+      <key>ignoretag</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(433, 164)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <block>
+    <key>analog_sig_source_x</key>
+    <param>
+      <key>id</key>
+      <value>analog_sig_source_x_0</value>
+    </param>
+    <param>
+      <key>_enabled</key>
+      <value>True</value>
+    </param>
+    <param>
+      <key>type</key>
+      <value>complex</value>
+    </param>
+    <param>
+      <key>samp_rate</key>
+      <value>samp_rate</value>
+    </param>
+    <param>
+      <key>waveform</key>
+      <value>analog.GR_COS_WAVE</value>
+    </param>
+    <param>
+      <key>freq</key>
+      <value>123.2435</value>
+    </param>
+    <param>
+      <key>amp</key>
+      <value>32000</value>
+    </param>
+    <param>
+      <key>offset</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>affinity</key>
+      <value></value>
+    </param>
+    <param>
+      <key>minoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>maxoutbuf</key>
+      <value>0</value>
+    </param>
+    <param>
+      <key>_coordinate</key>
+      <value>(218, 177)</value>
+    </param>
+    <param>
+      <key>_rotation</key>
+      <value>0</value>
+    </param>
+  </block>
+  <connection>
+    <source_block_id>analog_sig_source_x_0</source_block_id>
+    <sink_block_id>blocks_throttle_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_throttle_0</source_block_id>
+    <sink_block_id>blocks_complex_to_interleaved_short_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_complex_to_interleaved_short_0</source_block_id>
+    <sink_block_id>blocks_file_sink_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+  <connection>
+    <source_block_id>blocks_throttle_0</source_block_id>
+    <sink_block_id>wxgui_fftsink2_0</sink_block_id>
+    <source_key>0</source_key>
+    <sink_key>0</sink_key>
+  </connection>
+</flow_graph>
diff --git a/fpga/usrp3/lib/sim/rfnoc/moving_sum/build_moving_sum_tb b/fpga/usrp3/lib/sim/rfnoc/moving_sum/build_moving_sum_tb
new file mode 100755
index 000000000..f7fd1e9c7
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/moving_sum/build_moving_sum_tb
@@ -0,0 +1 @@
+iverilog -o moving_sum_tb -y . -y ../control/ -y ../fifo/ moving_sum_tb.v -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -Wall
diff --git a/fpga/usrp3/lib/sim/rfnoc/moving_sum/moving_sum_tb.v b/fpga/usrp3/lib/sim/rfnoc/moving_sum/moving_sum_tb.v
new file mode 100644
index 000000000..4ce455af5
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/moving_sum/moving_sum_tb.v
@@ -0,0 +1,43 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module moving_sum_tb();
+   
+   //xlnx_glbl glbl (.GSR(),.GTS());
+   
+   localparam STR_SINK_FIFOSIZE = 9;
+      
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("moving_sum_tb.vcd");
+   initial $dumpvars(0,moving_sum_tb);
+
+   initial #1000000 $finish;
+
+   wire [15:0] i_tdata;
+   wire [25:0] o_tdata;
+   wire        i_tvalid, i_tready, o_tvalid, o_tready;
+   
+   moving_sum #(.MAX_LEN_LOG2(10), .WIDTH(16)) moving_sum
+     (.clk(clk), .reset(reset), .clear(0),
+      .len(20),
+      .i_tdata(i_tdata), .i_tlast(), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   assign i_tdata = 1;
+   assign i_tvalid = 1;
+   assign o_tready = 1;
+   
+      
+endmodule // moving_sum_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/mult/mult_tb.v b/fpga/usrp3/lib/sim/rfnoc/mult/mult_tb.v
new file mode 100644
index 000000000..32b0d47fd
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/mult/mult_tb.v
@@ -0,0 +1,75 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module mult_tb();
+   
+   xlnx_glbl glbl (.GSR(),.GTS());
+   
+   localparam STR_SINK_FIFOSIZE = 9;
+      
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("mult_tb.vcd");
+   initial $dumpvars(0,mult_tb);
+
+   initial #1000000 $finish;
+
+   localparam AW=25;
+   localparam BW=18;
+   localparam PW=48;
+   
+   wire [AW-1:0] a_tdata;
+   wire [BW-1:0] b_tdata;
+   wire [PW-1:0] p_tdata;
+   
+   wire 	 a_tlast, a_tvalid, a_tready, b_tlast, b_tvalid, b_tready;
+   wire 	 p_tlast, p_tvalid;
+   reg 		 p_tready = 0;
+
+   reg 		 ai_tvalid = 0;
+   reg 		 bi_tvalid = 0;
+   
+   counter #(.WIDTH(AW)) ca
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(20),
+      .i_tlast(0), .i_tvalid(ai_tvalid), .i_tready(),
+      .o_tdata(a_tdata), .o_tlast(a_tlast), .o_tvalid(a_tvalid), .o_tready(a_tready));
+   
+   counter #(.WIDTH(BW)) cb
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(20),
+      .i_tlast(0), .i_tvalid(bi_tvalid), .i_tready(),
+      .o_tdata(b_tdata), .o_tlast(b_tlast), .o_tvalid(b_tvalid), .o_tready(b_tready));
+   
+   mult #(.WIDTH_A(AW), .WIDTH_B(BW), .WIDTH_P(PW), .LATENCY(4)) mult
+     (.clk(clk), .reset(reset),
+      .a_tdata(a_tdata), .a_tlast(a_tlast), .a_tvalid(a_tvalid), .a_tready(a_tready),
+      .b_tdata(b_tdata), .b_tlast(b_tlast), .b_tvalid(b_tvalid), .b_tready(b_tready),
+      .p_tdata(p_tdata), .p_tlast(p_tlast), .p_tvalid(p_tvalid), .p_tready(p_tready));
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (100)
+	  @(posedge clk);
+	ai_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	bi_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	p_tready <= 1;
+     end
+      
+endmodule // mult_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/mult_add/mult_add_tb.v b/fpga/usrp3/lib/sim/rfnoc/mult_add/mult_add_tb.v
new file mode 100644
index 000000000..23e772aba
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/mult_add/mult_add_tb.v
@@ -0,0 +1,90 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module mult_add_tb();
+   
+   xlnx_glbl glbl (.GSR(),.GTS());
+   
+   localparam STR_SINK_FIFOSIZE = 9;
+      
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("mult_add_tb.vcd");
+   initial $dumpvars(0,mult_add_tb);
+
+   initial #1000000 $finish;
+
+   localparam AW=25;
+   localparam BW=18;
+   localparam PW=48;
+   
+   wire [AW-1:0] a_tdata;
+   wire [BW-1:0] b_tdata;
+   wire [PW-1:0] pin_tdata;
+   wire [PW-1:0] pout_tdata;
+   
+   wire 	 a_tlast, a_tvalid, a_tready, b_tlast, b_tvalid, b_tready;
+   wire 	 pin_tlast, pin_tvalid;
+   wire 	 pout_tlast, pout_tvalid;
+   wire 	 pin_tready;
+   reg 		 pout_tready = 0;
+
+   reg 		 ai_tvalid = 0;
+   reg 		 bi_tvalid = 0;
+   reg 		 pi_tvalid = 0;
+   
+   counter #(.WIDTH(AW)) ca
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(25'd20),
+      .i_tlast(0), .i_tvalid(ai_tvalid), .i_tready(),
+      .o_tdata(a_tdata), .o_tlast(a_tlast), .o_tvalid(a_tvalid), .o_tready(a_tready));
+   
+   counter #(.WIDTH(BW)) cb
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(18'd20),
+      .i_tlast(0), .i_tvalid(bi_tvalid), .i_tready(),
+      .o_tdata(b_tdata), .o_tlast(b_tlast), .o_tvalid(b_tvalid), .o_tready(b_tready));
+   
+   counter #(.WIDTH(PW)) cp
+     (.clk(clk), .reset(reset), .clear(0),
+      .max(48'd20),
+      .i_tlast(0), .i_tvalid(pi_tvalid), .i_tready(),
+      .o_tdata(pin_tdata), .o_tlast(pin_tlast), .o_tvalid(pin_tvalid), .o_tready(pin_tready));
+   
+   mult_add #(.WIDTH_A(AW), .WIDTH_B(BW), .WIDTH_P(PW),
+	      .LATENCY(3), .CASCADE_IN(1), .CASCADE_OUT(1)) mult_add
+     (.clk(clk), .reset(reset),
+      .a_tdata(a_tdata), .a_tlast(a_tlast), .a_tvalid(a_tvalid), .a_tready(a_tready),
+      .b_tdata(b_tdata), .b_tlast(b_tlast), .b_tvalid(b_tvalid), .b_tready(b_tready),
+      .c_tdata(pin_tdata), .c_tlast(pin_tlast), .c_tvalid(pin_tvalid), .c_tready(pin_tready),
+      .p_tdata(pout_tdata), .p_tlast(pout_tlast), .p_tvalid(pout_tvalid), .p_tready(pout_tready));
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (100)
+	  @(posedge clk);
+	ai_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	bi_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	pi_tvalid <= 1;
+	repeat (10)
+	  @(posedge clk);
+	pout_tready <= 1;
+     end
+      
+endmodule // mult_add_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/null_source/null_source_tb.v b/fpga/usrp3/lib/sim/rfnoc/null_source/null_source_tb.v
new file mode 100644
index 000000000..c9cf29111
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/null_source/null_source_tb.v
@@ -0,0 +1,80 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module null_source_tb();
+   
+   reg clk, reset;
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("null_source_tb.vcd");
+   initial $dumpvars(0,null_source_tb);
+
+   //initial #10000000 $finish;
+
+   reg [31:0] set_data;
+   reg [7:0]  set_addr;
+   reg        set_stb=0;
+
+   wire [63:0] src_tdata;
+   wire	       src_tlast, src_tvalid;
+   wire        src_tready;
+
+   assign src_tready = 1'b1;
+   
+   localparam PORTS = 4;
+
+   null_source #(.BASE(0)) axi_wrapper_ce1
+     (.clk(clk), .reset(reset),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .o_tdata(src_tdata), .o_tlast(src_tlast), .o_tvalid(src_tvalid), .o_tready(src_tready)     );
+
+   initial
+     begin
+
+	@(negedge reset);
+	@(posedge clk);
+	#100000;
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 0;
+	set_data <= 32'hDEADBEEF;
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 1;  // Len
+	set_data <= 32'h8;
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 2;
+	set_data <= 32'h20; // Rate
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 3;
+	set_data <= 1;     // enable
+	@(posedge clk);
+	set_stb <= 0;
+	@(posedge clk);
+	#1000000;
+	@(posedge clk);
+	set_stb <= 1;
+	set_addr <= 3;
+	set_data <= 0;     // disable
+	@(posedge clk);
+	set_stb <= 0;
+	#1000000;
+
+	$finish;
+	
+	
+     end
+
+endmodule // null_source_tb
diff --git a/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb b/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb
new file mode 100755
index 000000000..1af299fd4
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb
@@ -0,0 +1 @@
+iverilog -o window_tb window_tb.v -y ../coregen -y ../../../usrp2/models -y . -y ../control/ -y ../fifo/ -y /opt/Xilinx/14.6/ISE_DS/ISE/verilog/src/unisims/ -y ../packet_proc/ -y ../timing/ -y ../vita/
diff --git a/fpga/usrp3/lib/sim/rfnoc/window/window_tb.v b/fpga/usrp3/lib/sim/rfnoc/window/window_tb.v
new file mode 100644
index 000000000..2449057c8
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/window/window_tb.v
@@ -0,0 +1,341 @@
+`timescale 1ns/1ps
+
+//
+// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+module window_tb();
+   xlnx_glbl glbl (.GSR(),.GTS());
+
+   localparam STR_SINK_FIFOSIZE = 11;
+  
+   reg clk, reset;
+ 
+   localparam PORTS = 5;
+
+   wire [63:0] noci_tdata[PORTS-1:0];
+   wire [PORTS-1:0]       noci_tlast;
+   wire [PORTS-1:0]       noci_tvalid;
+   wire [PORTS-1:0]       noci_tready;
+
+   wire [63:0] noco_tdata[PORTS-1:0];
+   wire [PORTS-1:0]       noco_tlast;
+   wire [PORTS-1:0]       noco_tvalid;
+   wire [PORTS-1:0]       noco_tready;
+   
+   wire [63:0] src_tdata;
+   wire	       src_tlast, src_tvalid;
+   wire        src_tready;
+
+   reg [63:0]  cmdout_tdata;
+   reg 	       cmdout_tlast, cmdout_tvalid;
+   wire        cmdout_tready;
+
+   wire [63:0] dst_tdata;
+   wire        dst_tlast, dst_tvalid;
+   wire        dst_tready = 1;
+ 	       
+   reg 	       set_stb_xbar;
+   reg [15:0]  set_addr_xbar;
+   reg [31:0]  set_data_xbar;
+
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   initial reset = 1;
+   initial #1000 reset = 0;
+   
+   initial $dumpfile("window_tb.vcd");
+   initial $dumpvars(0,window_tb);
+
+   initial #3000000 $finish;
+
+
+   axi_crossbar #(.FIFO_WIDTH(64), .DST_WIDTH(16), .NUM_INPUTS(PORTS), .NUM_OUTPUTS(PORTS)) crossbar
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .local_addr(8'd0),
+      .pkt_present({noci_tvalid[4],noci_tvalid[3],noci_tvalid[2],noci_tvalid[1],noci_tvalid[0]}),
+      
+      .i_tdata({noci_tdata[4],noci_tdata[3],noci_tdata[2],noci_tdata[1],noci_tdata[0]}),
+      .i_tlast({noci_tlast[4],noci_tlast[3],noci_tlast[2],noci_tlast[1],noci_tlast[0]}),
+      .i_tvalid({noci_tvalid[4],noci_tvalid[3],noci_tvalid[2],noci_tvalid[1],noci_tvalid[0]}),
+      .i_tready({noci_tready[4],noci_tready[3],noci_tready[2],noci_tready[1],noci_tready[0]}),
+
+      .o_tdata({noco_tdata[4],noco_tdata[3],noco_tdata[2],noco_tdata[1],noco_tdata[0]}),
+      .o_tlast({noco_tlast[4],noco_tlast[3],noco_tlast[2],noco_tlast[1],noco_tlast[0]}),
+      .o_tvalid({noco_tvalid[4],noco_tvalid[3],noco_tvalid[2],noco_tvalid[1],noco_tvalid[0]}),
+      .o_tready({noco_tready[4],noco_tready[3],noco_tready[2],noco_tready[1],noco_tready[0]}),
+
+      .set_stb(set_stb_xbar), .set_addr(set_addr_xbar), .set_data(set_data_xbar),
+      .rb_rd_stb(1'b0), .rb_addr(4'd0), .rb_data());
+   
+   // Generator on port 0
+   wire        set_stb_0;
+   wire [7:0]  set_addr_0;
+   wire [31:0] set_data_0;
+   
+   noc_shell #(.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell_0
+     (.bus_clk(clk), .bus_rst(reset),
+      .i_tdata(noco_tdata[0]), .i_tlast(noco_tlast[0]), .i_tvalid(noco_tvalid[0]), .i_tready(noco_tready[0]),
+      .o_tdata(noci_tdata[0]), .o_tlast(noci_tlast[0]), .o_tvalid(noci_tvalid[0]), .o_tready(noci_tready[0]),
+      .clk(clk), .reset(reset),
+      .set_data(set_data_0), .set_addr(set_addr_0), .set_stb(set_stb_0), .rb_data(64'd0),
+
+      .cmdout_tdata(64'h0), .cmdout_tlast(1'b0), .cmdout_tvalid(1'b0), .cmdout_tready(),
+      .ackin_tdata(), .ackin_tlast(), .ackin_tvalid(), .ackin_tready(1'b1),
+      
+      .str_sink_tdata(), .str_sink_tlast(), .str_sink_tvalid(), .str_sink_tready(1'b1), // unused port
+      .str_src_tdata(src_tdata), .str_src_tlast(src_tlast), .str_src_tvalid(src_tvalid), .str_src_tready(src_tready)
+      );
+
+   file_source #(.BASE(8), .FILENAME("test.dat")) file_source
+     (.clk(clk), .reset(reset),
+      .set_data(set_data_0), .set_addr(set_addr_0), .set_stb(set_stb_0),
+      .o_tdata(src_tdata), .o_tlast(src_tlast), .o_tvalid(src_tvalid), .o_tready(src_tready));
+      
+   // Simple FIR on port 1
+   wire [31:0] set_data_1;
+   wire [7:0]  set_addr_1;
+   wire        set_stb_1;
+   wire [63:0] s1o_tdata, s1i_tdata;
+   wire        s1o_tlast, s1i_tlast, s1o_tvalid, s1i_tvalid, s1o_tready, s1i_tready;
+
+   wire [31:0] pre_tdata, post_tdata;
+   wire        pre_tlast, pre_tvalid, pre_tready;
+   wire        post_tlast, post_tvalid, post_tready;
+
+   wire [15:0] pre_i = pre_tdata[31:16];
+   wire [15:0] pre_q = pre_tdata[15:0];
+   wire [15:0] post_i = post_tdata[31:16];
+   wire [15:0] post_q = post_tdata[15:0];
+   
+   noc_shell #(.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell_1
+     (.bus_clk(clk), .bus_rst(reset),
+      .i_tdata(noco_tdata[1]), .i_tlast(noco_tlast[1]), .i_tvalid(noco_tvalid[1]), .i_tready(noco_tready[1]),
+      .o_tdata(noci_tdata[1]), .o_tlast(noci_tlast[1]), .o_tvalid(noci_tvalid[1]), .o_tready(noci_tready[1]),
+      .clk(clk), .reset(reset),
+      .set_data(set_data_1), .set_addr(set_addr_1), .set_stb(set_stb_1), .rb_data(64'd0),
+
+      .cmdout_tdata(64'h0), .cmdout_tlast(1'b0), .cmdout_tvalid(1'b0), .cmdout_tready(),
+      .ackin_tdata(), .ackin_tlast(), .ackin_tvalid(), .ackin_tready(1'b1),
+      
+      .str_sink_tdata(s1o_tdata), .str_sink_tlast(s1o_tlast), .str_sink_tvalid(s1o_tvalid), .str_sink_tready(s1o_tready),
+      .str_src_tdata(s1i_tdata), .str_src_tlast(s1i_tlast), .str_src_tvalid(s1i_tvalid), .str_src_tready(s1i_tready)
+      );
+
+   wire [31:0] axis_config_tdata1;
+   wire        axis_config_tvalid1, axis_config_tready1, axis_config_tlast1;
+   
+   axi_wrapper #(.BASE(8)) axi_wrapper_ce1
+     (.clk(clk), .reset(reset),
+      .set_stb(set_stb_1), .set_addr(set_addr_1), .set_data(set_data_1),
+      .i_tdata(s1o_tdata), .i_tlast(s1o_tlast), .i_tvalid(s1o_tvalid), .i_tready(s1o_tready),
+      .o_tdata(s1i_tdata), .o_tlast(s1i_tlast), .o_tvalid(s1i_tvalid), .o_tready(s1i_tready),
+      .m_axis_data_tdata(pre_tdata),
+      .m_axis_data_tlast(pre_tlast),
+      .m_axis_data_tvalid(pre_tvalid),
+      .m_axis_data_tready(pre_tready),
+      .s_axis_data_tdata(post_tdata),
+      .s_axis_data_tlast(post_tlast),
+      .s_axis_data_tvalid(post_tvalid),
+      .s_axis_data_tready(post_tready),
+      .m_axis_config_tdata(axis_config_tdata1),
+      .m_axis_config_tlast(axis_config_tlast1),
+      .m_axis_config_tvalid(axis_config_tvalid1),
+      .m_axis_config_tready(axis_config_tready1)
+      );
+
+   window #(.BASE(0)) window
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb_1), .set_addr(set_addr_1), .set_data(set_data_1),
+      .i_tdata(pre_tdata), .i_tlast(pre_tlast), .i_tvalid(pre_tvalid), .i_tready(pre_tready),
+      .o_tdata(post_tdata), .o_tlast(post_tlast), .o_tvalid(post_tvalid), .o_tready(post_tready));
+
+   assign axis_config_tready1 = 1'b1;
+   
+   // Dumper on port 2
+   noc_shell #(.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell_2
+     (.bus_clk(clk), .bus_rst(reset),
+      .i_tdata(noco_tdata[2]), .i_tlast(noco_tlast[2]), .i_tvalid(noco_tvalid[2]), .i_tready(noco_tready[2]),
+      .o_tdata(noci_tdata[2]), .o_tlast(noci_tlast[2]), .o_tvalid(noci_tvalid[2]), .o_tready(noci_tready[2]),
+      
+      .clk(clk), .reset(reset),
+      .set_data(), .set_addr(), .set_stb(), .rb_data(64'd0),
+
+      .cmdout_tdata(64'h0), .cmdout_tlast(1'b0), .cmdout_tvalid(1'b0), .cmdout_tready(),
+      .ackin_tdata(), .ackin_tlast(), .ackin_tvalid(), .ackin_tready(1'b1),
+      
+      .str_sink_tdata(dst_tdata), .str_sink_tlast(dst_tlast), .str_sink_tvalid(dst_tvalid), .str_sink_tready(dst_tready),
+      .str_src_tdata(64'd0), .str_src_tlast(1'd0), .str_src_tvalid(1'b0), .str_src_tready() // unused port
+      );
+
+   // Control Source on port 3
+   noc_shell #(.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell_3
+     (.bus_clk(clk), .bus_rst(reset),
+      .i_tdata(noco_tdata[3]), .i_tlast(noco_tlast[3]), .i_tvalid(noco_tvalid[3]), .i_tready(noco_tready[3]),
+      .o_tdata(noci_tdata[3]), .o_tlast(noci_tlast[3]), .o_tvalid(noci_tvalid[3]), .o_tready(noci_tready[3]),
+      
+      .clk(clk), .reset(reset),
+      .set_data(), .set_addr(), .set_stb(), .rb_data(64'd0),
+
+      .cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready),
+      .ackin_tdata(), .ackin_tlast(), .ackin_tvalid(), .ackin_tready(1'b1),
+      
+      .str_sink_tdata(), .str_sink_tlast(), .str_sink_tvalid(), .str_sink_tready(1'b1), // unused port
+      .str_src_tdata(64'd0), .str_src_tlast(1'd0), .str_src_tvalid(1'b0), .str_src_tready() // unused port
+      );
+
+   // ////////////////////////////////////////////////////////////////////////////////////
+   
+   task SetXbar;
+      input [15:0] start_reg;
+      input [7:0]  start_val;
+      
+      begin
+	 repeat (PORTS)
+	   begin
+	      repeat (1)
+		begin
+		   SetXbar_reg(start_reg,start_val);
+		   start_reg <= start_reg + 1;
+		   @(posedge clk);
+		end
+	      start_val <= start_val + 1;
+	      @(posedge clk);
+	   end
+      end
+   endtask // SetXbar
+   
+   task SetXbar_reg;
+      input [15:0] addr;
+      input [31:0] data;
+      begin
+	 @(posedge clk);
+	 set_stb_xbar <= 1'b1;
+	 set_addr_xbar <= addr;
+	 set_data_xbar <= data;
+	 @(posedge clk);
+	 set_stb_xbar <= 1'b0;
+	 @(posedge clk);
+      end
+   endtask // set_xbar
+
+   task SendCtrlPacket;
+      input [11:0] seqnum;
+      input [31:0] sid;
+      input [63:0] data;
+      
+      begin
+	 @(posedge clk);
+	 cmdout_tdata <= { 4'h8, seqnum, 16'h16, sid };
+	 cmdout_tlast <= 0;
+	 cmdout_tvalid <= 1;
+	 while(~cmdout_tready) #1;
+	 
+	 @(posedge clk);
+	 cmdout_tdata <= data;
+	 cmdout_tlast <= 1;
+	 while(~cmdout_tready) #1;
+	 
+	 @(posedge clk);
+	 cmdout_tvalid <= 0;
+	 @(posedge clk);
+      end
+   endtask // SendCtrlPacket
+
+   initial
+     begin
+	cmdout_tdata <= 64'd0;
+	cmdout_tlast <= 1'b0;
+	cmdout_tvalid <= 1'b0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	SetXbar(256,0);
+	
+	@(posedge clk);
+	// Port 0
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h0, 32'h0000_0003}); // Command packet to set up source control window size
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h1, 32'h0000_0001}); // Command packet to set up source control window enable
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h3, 32'h8000_0001}); // Command packet to set up flow control
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h8, 32'h0000_0001}); // Command packet to set up SID
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'hA, 32'h0000_0002}); // Command packet to set up Rate
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'hB, 32'h0000_0001}); // Command packet to set up send_time_field
+	SendCtrlPacket(12'd0, 32'h0003_0000, {32'h9, 32'h0000_0200}); // Command packet to set up Len
+	#10000;
+	// Port 1
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h0, 32'h0000_0013}); // Command packet to set up source control window size
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h1, 32'h0000_0001}); // Command packet to set up source control window enable
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h3, 32'h8000_0001}); // Command packet to set up flow control
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h8, 32'h0001_0002}); // Rewrite SID, send on to port 2
+
+
+	#10000;
+	// Port 2
+	SendCtrlPacket(12'd0, 32'h0003_0002, {32'h0, 32'h0000_0003}); // Command packet to set up source control window size
+	SendCtrlPacket(12'd0, 32'h0003_0002, {32'h1, 32'h0000_0001}); // Command packet to set up source control window enable
+	SendCtrlPacket(12'd0, 32'h0003_0002, {32'h3, 32'h8000_0001}); // Command packet to set up flow control
+
+	#1000000;
+	// WINDOW filter
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd0});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd1});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd2});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd3});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd4});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd5});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd6});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd7});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h11, 32'd8});  // frame_len  (FFTsize)
+
+	#1000000;
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h10, 32'd100000});  // frame_len  (FFTsize)
+	SendCtrlPacket(12'd0, 32'h0003_0001, {32'h11, 32'd100000});  // frame_len  (FFTsize)
+
+     end
+
+   reg in_packet = 0;
+
+   integer outfile;
+   
+   initial
+     begin
+	outfile = $fopen("output.dat","wb");
+	//src_tready <= 1'b1;
+     end
+
+   wire signed  [15:0] a,b,c,d;
+   assign a = src_tdata[63:48];
+   assign b = src_tdata[47:32];
+   assign c = src_tdata[31:16];
+   assign d = src_tdata[15:0];
+
+   always @(posedge clk)
+     if(src_tready & src_tvalid)
+       begin
+	  if(src_tlast)
+	    in_packet <= 0;
+	  else
+	    in_packet <= 1;
+	  if(in_packet)
+	    begin
+	       //$fwrite(outfile,"%u",{q_out[15:0],i_out[15:0]}); // Correct endianness for GR
+	       //$write("%d,%d,%d,%d,",a,b,c,d);
+	       $fwrite(outfile,"%u",{dst_tdata[47:32],dst_tdata[63:48]});
+	       $fwrite(outfile,"%u",{dst_tdata[15:0],dst_tdata[31:16]});
+	    end
+       end
+
+endmodule // window_tb