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-rwxr-xr-xfpga/usrp3/lib/sim/rfnoc/window/build_window_tb1
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb b/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb
new file mode 100755
index 000000000..1af299fd4
--- /dev/null
+++ b/fpga/usrp3/lib/sim/rfnoc/window/build_window_tb
@@ -0,0 +1 @@
+iverilog -o window_tb window_tb.v -y ../coregen -y ../../../usrp2/models -y . -y ../control/ -y ../fifo/ -y /opt/Xilinx/14.6/ISE_DS/ISE/verilog/src/unisims/ -y ../packet_proc/ -y ../timing/ -y ../vita/