Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 121 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv
new file mode 100644
index 000000000..c2c69b963
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv
@@ -0,0 +1,121 @@
+//
+// Copyright 2016 Ettus Research
+//
+
+module axi_fifo_2clk_tb();
+
+    localparam WIDTH    = 32;
+    localparam SIZE     = 5;
+
+    reg                 s_axis_clk;
+    reg                 s_axis_rst;
+    reg [WIDTH-1:0]     s_axis_tdata;
+    reg                 s_axis_tvalid;
+    reg                 s_axis_tlast;
+    wire                s_axis_tready;
+    reg                 m_axis_clk;
+    reg                 m_axis_rst;
+    wire [WIDTH-1:0]    m_axis_tdata;
+    wire                m_axis_tvalid;
+    wire                m_axis_tlast;
+    reg                 m_axis_tready;
+    wire [SIZE:0]       s_axis_occupied;
+    wire                s_axis_full;
+    wire                s_axis_empty;
+    wire [SIZE:0]       m_axis_occupied;
+    wire                m_axis_full;
+    wire                m_axis_empty;
+
+    axi_fifo_2clk #(.SIZE(SIZE),.WIDTH(WIDTH)) axi_fifo_2clk (
+        .s_axis_clk(s_axis_clk),
+        .s_axis_rst(s_axis_rst),
+        .s_axis_tdata(s_axis_tdata),
+        .s_axis_tvalid(s_axis_tvalid),
+        .s_axis_tlast(s_axis_tlast),
+        .s_axis_tready(s_axis_tready),
+        .m_axis_clk(m_axis_clk),
+        .m_axis_rst(m_axis_rst),
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid),
+        .m_axis_tlast(m_axis_tlast),
+        .m_axis_tready(m_axis_tready),
+        .s_axis_occupied(s_axis_occupied),
+        .s_axis_full(s_axis_full),
+        .s_axis_empty(s_axis_empty),
+        .m_axis_occupied(m_axis_occupied),
+        .m_axis_full(m_axis_full),
+        .m_axis_empty(m_axis_empty));
+
+    `define S_AXIS_CLK_PERIOD 7
+    initial begin
+        s_axis_clk = 1'b0;
+        forever begin
+            #(`S_AXIS_CLK_PERIOD/2) s_axis_clk = ~s_axis_clk;
+        end
+    end
+
+    `define S_AXIS_RESET_PERIOD 70
+    initial begin
+        s_axis_rst = 1'b1;
+        #(`S_AXIS_RESET_PERIOD) s_axis_rst = 1'b0;
+    end
+
+    `define M_AXIS_CLK_PERIOD 10
+    initial begin
+        m_axis_clk = 1'b0;
+        forever begin
+            #(`M_AXIS_CLK_PERIOD/2) m_axis_clk = ~m_axis_clk;
+        end
+    end
+
+    `define M_AXIS_RESET_PERIOD 100
+    initial begin
+        m_axis_rst = 1'b1;
+        #(`M_AXIS_RESET_PERIOD) m_axis_rst = 1'b0;
+    end
+
+    initial begin
+        @(posedge m_axis_clk);
+        @(posedge s_axis_clk);
+        s_axis_tdata  = 'd0;
+        s_axis_tlast  = 1'b0;
+        s_axis_tvalid = 1'b0;
+        m_axis_tready = 1'b0;
+        assert(~s_axis_full && ~m_axis_full)                 else $error("FIFO is full during reset!");
+        assert(s_axis_empty == 1'b1 && m_axis_empty == 1'b1) else $error("FIFO is not empty during reset!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("FIFO is occupied during reset!");
+        while (s_axis_rst) @(negedge s_axis_rst);
+        while (m_axis_rst) @(negedge m_axis_rst);
+        @(posedge m_axis_clk);
+        @(posedge s_axis_clk);
+        assert(~s_axis_full && ~m_axis_full)                 else $error("FIFO is full after reset!");
+        assert(s_axis_empty == 1'b1 && m_axis_empty == 1'b1) else $error("FIFO is not empty after reset!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("FIFO is occupied after reset!");
+        // Fill FIFO
+        while (~s_axis_tready) @(posedge s_axis_clk);
+        for (int i = 0; i < 1 << DEPTH_LOG2; i++) begin
+            s_axis_tdata  = i+1'b1;
+            s_axis_tvalid = 1'b1;
+            @(posedge s_axis_clk);
+        end
+        repeat (6) @(posedge s_axis_clk);
+        assert(s_axis_full && m_axis_full) else $error("Incorrect FIFO full flag!");
+        assert(~s_axis_empty && ~m_axis_empty) else $error("Incorrect FIFO empty flag!");
+        assert(s_axis_occupied == (1 << DEPTH_LOG2) && m_axis_occupied == (1 << DEPTH_LOG2)) else $error("Incorrect FIFO occupied count!");
+        // Empty FIFO
+        s_axis_tdata  = 'd0;
+        s_axis_tvalid = 1'b0;
+        @(posedge m_axis_clk);
+        while (~m_axis_tvalid) @(posedge m_axis_clk);
+        for (int i = 0; i < 1 << DEPTH_LOG2; i++) begin
+            m_axis_tready = 1'b1;
+            @(posedge m_axis_clk);
+            assert(m_axis_tdata == i+1'b1) else $error("Incorrect FIFO data! (read)");
+        end
+        repeat (6) @(posedge m_axis_clk);
+        assert(~s_axis_full && ~m_axis_full) else $error("Incorrect FIFO full flag!");
+        assert(s_axis_empty && m_axis_empty) else $error("Incorrect FIFO empty flag!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("Incorrect FIFO occupied count!");
+    end
+
+endmodule
\ No newline at end of file