Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

14 files changed, 2230 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/default.wcfg b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/default.wcfg
new file mode 100644
index 000000000..796071597
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/default.wcfg
@@ -0,0 +1,412 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="axi_dram_fifo_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="38" />
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clear" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clear</obj_property>
+      <obj_property name="ObjectShortName">clear</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/count_rx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">count_rx[31:0]</obj_property>
+      <obj_property name="ObjectShortName">count_rx[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/count_tx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">count_tx[31:0]</obj_property>
+      <obj_property name="ObjectShortName">count_tx[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+      <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tlast" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tlast</obj_property>
+      <obj_property name="ObjectShortName">i_tlast</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tvalid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tvalid</obj_property>
+      <obj_property name="ObjectShortName">i_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tready</obj_property>
+      <obj_property name="ObjectShortName">i_tready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">input_state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">input_state[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_ctrl_ready</obj_property>
+      <obj_property name="ObjectShortName">write_ctrl_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_ctrl_valid</obj_property>
+      <obj_property name="ObjectShortName">write_ctrl_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied_input" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied_input[5:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied_input[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group92" type="group">
+      <obj_property name="label">INPUT TIMEOUT</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_count" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_count[7:0]</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_count[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_reset</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_triggered" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_triggered</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_triggered</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group60" type="group">
+      <obj_property name="label">AXI_WADDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_addr_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">write_addr_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">write_addr_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awaddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awaddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awaddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awsize" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awsize[2:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awsize[2:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awburst" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awburst[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awburst[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_data_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">write_data_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">write_data_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group61" type="group">
+      <obj_property name="label">AXI_WDATA</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wstrb" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wstrb[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wstrb[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wlast</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group62" type="group">
+      <obj_property name="label">AXI_WRESP</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bresp" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bresp[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bresp[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bready</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#00ff00</obj_property>
+         <obj_property name="label">/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space[10:0]</obj_property>
+      <obj_property name="ObjectShortName">space[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied[10:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#00ffff</obj_property>
+   </wvobject>
+   <wvobject fp_name="group63" type="group">
+      <obj_property name="label">AXI_RADDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_addr_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">read_addr_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">read_addr_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arsize" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arsize[2:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arsize[2:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arburst" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arburst[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arburst[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group64" type="group">
+      <obj_property name="label">AXI_RDATA</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">read_data_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">read_data_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rresp" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rresp[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rresp[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rlast</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">read_ctrl_valid</obj_property>
+      <obj_property name="ObjectShortName">read_ctrl_valid</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ffff00</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">read_ctrl_ready</obj_property>
+      <obj_property name="ObjectShortName">read_ctrl_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">read_data_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">read_data_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">output_state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">output_state[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space_output" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space_output[5:0]</obj_property>
+      <obj_property name="ObjectShortName">space_output[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group80" type="group">
+      <obj_property name="label">DRAM FIFO OUT</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_output" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_output[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_output[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_output" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_output</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_output</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_output" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_output</obj_property>
+         <obj_property name="ObjectShortName">o_tready_output</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">update_write</obj_property>
+      <obj_property name="ObjectShortName">update_write</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ff00ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">write_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">write_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">update_read</obj_property>
+      <obj_property name="ObjectShortName">update_read</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ff00ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">read_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">read_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group68" type="group">
+      <obj_property name="label">Output TImeout</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_count" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_count[7:0]</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_count[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_reset</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_triggered" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_triggered</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_triggered</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group76" type="group">
+      <obj_property name="label">Extract TLAST</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i0" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_i0[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_i0[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_i0</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_i0</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_i0</obj_property>
+         <obj_property name="ObjectShortName">o_tready_i0</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_i1[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_i1[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_i1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tready_i1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tlast_i1</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+      <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tlast</obj_property>
+      <obj_property name="ObjectShortName">o_tlast</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tvalid</obj_property>
+      <obj_property name="ObjectShortName">o_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tready</obj_property>
+      <obj_property name="ObjectShortName">o_tready</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/run_isim b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/run_isim
new file mode 100755
index 000000000..5d32efcdd
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/run_isim
@@ -0,0 +1,16 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../axi \
+	 --sourcelibdir ../../fifo \
+	 --sourcelibdir ../../../top/b250/coregen \
+	 ../../axi/axi_dram_fifo_tb.v
+
+
+
+fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
+
+# run the simulation scrip
+./axi_dram_fifo_tb.exe -gui #-tclbatch simcmds.tcl
+#./source_flow_control_tb.exe
+
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/default.wcfg b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/default.wcfg
new file mode 100644
index 000000000..796071597
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/default.wcfg
@@ -0,0 +1,412 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="axi_dram_fifo_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="38" />
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/clear" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clear</obj_property>
+      <obj_property name="ObjectShortName">clear</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/count_rx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">count_rx[31:0]</obj_property>
+      <obj_property name="ObjectShortName">count_rx[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/count_tx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">count_tx[31:0]</obj_property>
+      <obj_property name="ObjectShortName">count_tx[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+      <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tlast" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tlast</obj_property>
+      <obj_property name="ObjectShortName">i_tlast</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tvalid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tvalid</obj_property>
+      <obj_property name="ObjectShortName">i_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/i_tready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_tready</obj_property>
+      <obj_property name="ObjectShortName">i_tready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">input_state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">input_state[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_ctrl_ready</obj_property>
+      <obj_property name="ObjectShortName">write_ctrl_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_ctrl_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_ctrl_valid</obj_property>
+      <obj_property name="ObjectShortName">write_ctrl_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied_input" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied_input[5:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied_input[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group92" type="group">
+      <obj_property name="label">INPUT TIMEOUT</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_count" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_count[7:0]</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_count[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_reset</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/input_timeout_triggered" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">input_timeout_triggered</obj_property>
+         <obj_property name="ObjectShortName">input_timeout_triggered</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group60" type="group">
+      <obj_property name="label">AXI_WADDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_addr_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">write_addr_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">write_addr_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awaddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awaddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awaddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awsize" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awsize[2:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awsize[2:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awburst" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awburst[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awburst[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_awready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_awready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_awready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/write_data_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">write_data_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">write_data_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group61" type="group">
+      <obj_property name="label">AXI_WDATA</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wstrb" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wstrb[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wstrb[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wlast</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_wready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_wready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_wready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group62" type="group">
+      <obj_property name="label">AXI_WRESP</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bresp" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bresp[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bresp[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_bready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_bready</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#00ff00</obj_property>
+         <obj_property name="label">/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_bready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space[10:0]</obj_property>
+      <obj_property name="ObjectShortName">space[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied[10:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#00ffff</obj_property>
+   </wvobject>
+   <wvobject fp_name="group63" type="group">
+      <obj_property name="label">AXI_RADDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_addr_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">read_addr_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">read_addr_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arsize" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arsize[2:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arsize[2:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arburst" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arburst[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arburst[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group64" type="group">
+      <obj_property name="label">AXI_RDATA</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">read_data_state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">read_data_state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="UseCustomSignalColor">true</obj_property>
+         <obj_property name="CustomSignalColor">#ffff00</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rid[0:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rid[0:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rresp" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rresp[1:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rresp[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rlast</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">read_ctrl_valid</obj_property>
+      <obj_property name="ObjectShortName">read_ctrl_valid</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ffff00</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_ctrl_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">read_ctrl_ready</obj_property>
+      <obj_property name="ObjectShortName">read_ctrl_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_dma_master_i/read_data_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">read_data_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">read_data_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">output_state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">output_state[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space_output" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space_output[5:0]</obj_property>
+      <obj_property name="ObjectShortName">space_output[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group80" type="group">
+      <obj_property name="label">DRAM FIFO OUT</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_output" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_output[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_output[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_output" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_output</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_output</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_output" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_output</obj_property>
+         <obj_property name="ObjectShortName">o_tready_output</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">update_write</obj_property>
+      <obj_property name="ObjectShortName">update_write</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ff00ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/write_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">write_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">write_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/update_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">update_read</obj_property>
+      <obj_property name="ObjectShortName">update_read</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+      <obj_property name="CustomSignalColor">#ff00ff</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/read_count" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">read_count[3:0]</obj_property>
+      <obj_property name="ObjectShortName">read_count[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group68" type="group">
+      <obj_property name="label">Output TImeout</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_count" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_count[7:0]</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_count[7:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_reset</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/output_timeout_triggered" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">output_timeout_triggered</obj_property>
+         <obj_property name="ObjectShortName">output_timeout_triggered</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group76" type="group">
+      <obj_property name="label">Extract TLAST</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i0" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_i0[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_i0[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_i0</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_i0</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i0" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_i0</obj_property>
+         <obj_property name="ObjectShortName">o_tready_i0</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata_i1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata_i1[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata_i1[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid_i1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tready_i1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast_i1" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast_i1</obj_property>
+         <obj_property name="ObjectShortName">o_tlast_i1</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+      <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tlast</obj_property>
+      <obj_property name="ObjectShortName">o_tlast</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tvalid</obj_property>
+      <obj_property name="ObjectShortName">o_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_tready</obj_property>
+      <obj_property name="ObjectShortName">o_tready</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/run_isim b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/run_isim
new file mode 100755
index 000000000..03eead1f7
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/run_isim
@@ -0,0 +1,17 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../../lib/axi \
+	 --sourcelibdir ../../../lib/fifo \
+         --sourcelibdir ../../../lib/control \
+	 --sourcelibdir ../../../top/x300/coregen \
+	 ../../../lib/axi/axi_dram_fifo_tb.v
+
+
+
+fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
+
+# run the simulation scrip
+./axi_dram_fifo_tb.exe  # -gui #-tclbatch simcmds.tcl
+
+
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/simulation_script.v b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/simulation_script.v
new file mode 100644
index 000000000..974b4e096
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_1/simulation_script.v
@@ -0,0 +1,118 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+reg [31:0] count_rx, count_tx;
+reg status;
+reg fail;
+
+
+//
+// Use task library
+//
+`define USE_TASKS
+
+   initial 
+     begin
+	clk <= 1'b0;
+	reset <= 1'b0;
+	clear <= 1'b0;
+	i_tdata_r <= 0;
+	i_tlast_r <= 0;
+	i_tvalid_r <= 0;
+	o_tready_r <= 0;
+     end
+   
+   always
+     #5 clk <= ~clk;
+   
+   initial
+     begin
+	count_tx = 2;
+	count_rx = 2;
+	status = 0;
+	
+	
+	@(negedge clk);
+	reset <= 1'b1;
+	repeat(10) @(negedge clk);
+	reset <= 1'b0;
+	repeat(10) @(negedge clk);
+
+	// Send 40 packets.
+	repeat(40) begin
+	   send_raw_packet(count_tx);
+	   repeat(2) @(posedge clk);
+	   count_tx = count_tx + 1;
+	   @(posedge clk);
+	end
+	repeat(100) @(posedge clk);
+	
+
+	// Recieve 40 packets
+	repeat(40) begin
+	   receive_raw_packet(count_rx,fail);
+	   status = status || fail;
+	   repeat(2) @(posedge clk);
+	   count_rx = count_rx + 1;
+	   @(posedge clk);
+	end
+	repeat(100) @(posedge clk);
+
+	count_tx = 2;
+	count_rx = 2;
+	
+	// Send 40 packets.
+	repeat(40) begin
+	   send_raw_packet(count_tx);
+	   repeat(2) @(posedge clk);
+	   count_tx = count_tx + 1;
+	   @(posedge clk);
+	end
+	repeat(100) @(posedge clk);
+	// Now fork so send and receive run concurrently
+	fork
+	   begin
+	      // Send 40 packets.
+	      repeat(40) begin
+		 send_raw_packet(count_tx);
+		 repeat(2) @(posedge clk);
+		 count_tx = count_tx + 1;
+		 @(posedge clk);
+	      end
+	   end
+	   begin
+	      // Recieve 80 packets
+	      repeat(80) begin
+		 receive_raw_packet(count_rx,status);
+		 status = status || fail;
+		 repeat(2) @(posedge clk);
+		 count_rx = count_rx + 1;
+		 @(posedge clk);
+		 if (status !== 0) begin
+		    repeat(100) @(posedge clk);
+		    $display("FAILED.");
+		    $finish;	
+		 end
+	      end
+	   end
+	join
+	// Now single threaded agian.
+	repeat(100) @(posedge clk);
+
+	$display;
+	// Should not be able to get to here with FAIL status but check anyhow
+	if (status != 0)
+	  $display("FAILED.");
+	else
+	  $display("PASSED.");
+	
+	@(posedge clk);
+	$finish;
+	
+     end
+   
+   //initial
+   //  o_tready = 1;
+   
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/Default.wcfg b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/Default.wcfg
new file mode 100644
index 000000000..3e6d96fb4
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/Default.wcfg
@@ -0,0 +1,388 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="axi_dram_fifo_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="14" />
+   <wave_markers>
+      <marker time="31415100000" label="" />
+      <marker time="30385518000" label="" />
+      <marker time="23065100000" label="" />
+      <marker time="18355382000" label="" />
+   </wave_markers>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="group31" type="group">
+      <obj_property name="label">chdr_test_pattern</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/start" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">start</obj_property>
+         <obj_property name="ObjectShortName">start</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tlast</obj_property>
+         <obj_property name="ObjectShortName">i_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast</obj_property>
+         <obj_property name="ObjectShortName">o_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_chdr_test_pattern_i/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group11" type="group">
+      <obj_property name="label">embed_tlast</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tlast</obj_property>
+         <obj_property name="ObjectShortName">i_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_embed_tlast_i/state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group18" type="group">
+      <obj_property name="label">fast_fifo_i0</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/state" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">state[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i0/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+         <obj_property name="label">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group25" type="group">
+      <obj_property name="label">fifo_i1</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i1/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group79" type="group">
+      <obj_property name="label">AXI write bus</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_awaddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_awaddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">axi_awaddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_awlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_awlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">axi_awlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_awvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_awvalid</obj_property>
+         <obj_property name="ObjectShortName">axi_awvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_awready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_awready</obj_property>
+         <obj_property name="ObjectShortName">axi_awready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_wdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_wdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">axi_wdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_wvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_wvalid</obj_property>
+         <obj_property name="ObjectShortName">axi_wvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_wready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_wready</obj_property>
+         <obj_property name="ObjectShortName">axi_wready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_bvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_bvalid</obj_property>
+         <obj_property name="ObjectShortName">axi_bvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_bready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">axi_bready</obj_property>
+         <obj_property name="ObjectShortName">axi_bready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/space" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">space[10:0]</obj_property>
+      <obj_property name="ObjectShortName">space[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/occupied" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">occupied[10:0]</obj_property>
+      <obj_property name="ObjectShortName">occupied[10:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="group71" type="group">
+      <obj_property name="label">AXI read bus</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_araddr" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_araddr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arlen" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arlen[7:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_arready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_arready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_arready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rvalid</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/m_axi_rready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">m_axi_rready</obj_property>
+         <obj_property name="ObjectShortName">m_axi_rready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group43" type="group">
+      <obj_property name="label">fifo_i2</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fifo_i2/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group50" type="group">
+      <obj_property name="label">fast_fifo_i1</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/fast_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group58" type="group">
+      <obj_property name="label">axi_fast_extract</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast</obj_property>
+         <obj_property name="ObjectShortName">o_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/axi_fast_extract_tlast_i0/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group63" type="group">
+      <obj_property name="label">dram_fifo_output</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tlast" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tlast</obj_property>
+         <obj_property name="ObjectShortName">o_tlast</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_dram_fifo_tb/axi_dram_fifo_i1/o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/run_isim b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/run_isim
new file mode 100755
index 000000000..46141fcae
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/run_isim
@@ -0,0 +1,19 @@
+/bin/rm -r isim
+
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+
+vlogcomp -work work --sourcelibext .v \
+	 --sourcelibdir ../../../lib/axi \
+	 --sourcelibdir ../../../lib/fifo \
+	 --sourcelibdir ../../../lib/control \
+	 --sourcelibdir ../../../top/x300/coregen \
+	 ../../../lib/axi/axi_dram_fifo_tb.v
+
+
+
+fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
+
+# run the simulation scrip
+./axi_dram_fifo_tb.exe  -gui #-tclbatch simcmds.tcl
+
+
diff --git a/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/simulation_script.v b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/simulation_script.v
new file mode 100644
index 000000000..66de106d7
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_dram_fifo/sim_sram_2/simulation_script.v
@@ -0,0 +1,96 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+wire fail;
+wire done;
+reg start;
+reg [15:0] control;
+
+
+
+axi_chdr_test_pattern axi_chdr_test_pattern_i
+  (
+   .clk(clk),
+   .reset(reset),
+  
+   //
+   // CHDR friendly AXI stream input
+   //
+   .i_tdata(i_tdata),
+   .i_tlast(i_tlast),
+   .i_tvalid(i_tvalid),
+   .i_tready(i_tready),
+   //
+   // CHDR friendly AXI Stream output
+   //
+   .o_tdata(o_tdata),
+   .o_tlast(o_tlast),
+   .o_tvalid(o_tvalid),
+   .o_tready(o_tready),
+   //
+   // Test flags
+   //
+   .start(start),
+   .fail(fail),
+   .done(done),
+   .control(control)
+   );
+
+   
+   always
+     #5 clk <= ~clk;
+   
+   initial
+     begin
+	clk <= 1'b0;
+	reset <= 1'b0;
+	clear <= 1'b0;
+	start <= 1'b0;
+	control <= 16'h0101;
+	
+	
+	@(negedge clk);
+	reset <= 1'b1;
+	repeat(10) @(negedge clk);
+	reset <= 1'b0;
+	repeat(10) @(negedge clk);
+	// Now activate BIST
+	start <= 1'b1;
+	
+	// Wait until simulation is done.
+	while(!done)
+	  @(negedge clk);
+	
+	$display;
+	
+	if (fail)
+	  $display("FAILED.");
+	else
+	  $display("Done 1st pass.");
+	
+	@(posedge clk);
+	start <= 1'b0;
+	repeat(10) @(negedge clk);
+	// Now activate BIST
+	start <= 1'b1;
+	
+	// Wait until simulation is done.
+	while(!done)
+	  @(negedge clk);
+	
+	$display;
+	
+	if (fail)
+	  $display("FAILED.");
+	else
+	  $display("PASSED.");
+	
+	$finish;
+	
+     end
+   
+   //initial
+   //  o_tready = 1;
+   
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo/Makefile b/fpga/usrp3/lib/sim/fifo/axi_fifo/Makefile
new file mode 100644
index 000000000..3cd861176
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../top)
+# Include viv_sim_preamble after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+# Define only one toplevel module
+SIM_TOP = axi_fifo_tb
+
+SIM_SRCS = $(abspath \
+axi_fifo_tb.sv \
+$(LIB_DIR)/fifo/axi_fifo.v \
+$(LIB_DIR)/fifo/axi_fifo_flop.v \
+$(LIB_DIR)/fifo/axi_fifo_flop2.v \
+$(LIB_DIR)/fifo/axi_fifo_short.v \
+$(LIB_DIR)/fifo/axi_fifo_bram.v \
+)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv b/fpga/usrp3/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv
new file mode 100644
index 000000000..c2832cade
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv
@@ -0,0 +1,134 @@
+//
+// Copyright 2016 Ettus Research
+//
+
+`timescale 1ns/1ps
+`define SIM_TIMEOUT_US 1000
+`define NS_PER_TICK 1
+`define NUM_TEST_CASES 4
+
+`include "sim_exec_report.vh"
+`include "sim_clks_rsts.vh"
+`include "sim_cvita_lib.svh"
+`include "sim_axis_lib.svh"
+`include "sim_set_rb_lib.svh"
+
+module axi_fifo_tb();
+  /*********************************************
+  ** Setup Testbench
+  *********************************************/
+  `TEST_BENCH_INIT("axi_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK);
+  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
+  `DEFINE_CLK(clk, CLK_PERIOD, 50);
+  `DEFINE_RESET(reset, 0, 100);
+
+  // 4 variants: axi_fifo_flop, axi_fifo_flop2, axi_fifo_short, axi_fifo_bram
+  localparam NUM_FIFOS = 4;
+  localparam integer FIFO_SIZES[NUM_FIFOS-1:0] = '{0,1,5,8};
+  localparam NUM_ITERATIONS = 10000;
+
+  /*********************************************
+  ** DUTs
+  ** - Instances of all variations of AXI FIFO
+  *********************************************/
+  reg  [NUM_FIFOS-1:0] clear;
+  axis_master #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) m_axis(.clk(clk));
+  axis_slave #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) s_axis(.clk(clk));
+
+  genvar n;
+  generate
+    for (n = 0; n < NUM_FIFOS; n = n + 1) begin
+      axi_fifo #(
+        .SIZE(FIFO_SIZES[n]),
+        .WIDTH(32))
+      axi_fifo (
+        .clk(clk), .reset(reset), .clear(clear[n]),
+        .i_tdata(m_axis.axis.tdata[32*n +: 32]), .i_tvalid(m_axis.axis.tvalid[n]), .i_tready(m_axis.axis.tready[n]),
+        .o_tdata(s_axis.axis.tdata[32*n +: 32]), .o_tvalid(s_axis.axis.tvalid[n]), .o_tready(s_axis.axis.tready[n]),
+        .space(), .occupied());
+    end
+  endgenerate
+
+  /*********************************************
+  ** Testbench
+  *********************************************/
+  int write_word = 0;
+  int read_word = 0;
+  logic last;
+  string s;
+
+  initial begin
+    clear = 'd0;
+
+    /********************************************************
+    ** Test 1 -- Reset
+    ********************************************************/
+    `TEST_CASE_START("Wait for Reset");
+    m_axis.reset();
+    s_axis.reset();
+    while (reset) @(posedge clk);
+    `TEST_CASE_DONE(~reset);
+
+    /********************************************************
+    ** Test 2 -- Check filling FIFOs
+    ********************************************************/
+    `TEST_CASE_START("Check filling FIFOs");
+    for (int i = 0; i < NUM_FIFOS; i++) begin
+      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
+      for (int k = 0; k < 2**FIFO_SIZES[i]; k++) begin
+        $sformat(s,"FIFO size should be %0d entries, but detected %0d!",2**FIFO_SIZES[i],k);
+        `ASSERT_FATAL(m_axis.axis.tready[i],s);
+        m_axis.push_word(k,0,i);
+      end
+      $sformat(s,"FIFO depth appears to be greater than %0d entries! Might be due to output registering.",2**FIFO_SIZES[i]);
+      `ASSERT_WARN(~m_axis.axis.tready[i],s);
+    end
+    `TEST_CASE_DONE(1);
+
+    /********************************************************
+    ** Test 3 -- Check emptying FIFOs
+    ********************************************************/
+    `TEST_CASE_START("Check emptying FIFOs");
+    for (int i = 0; i < NUM_FIFOS; i++) begin
+      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
+      for (int k = 0; k < 2**FIFO_SIZES[i]; k = k + 1) begin
+        $sformat(s,"FIFO prematurely empty! Occured after %0d reads!",k);
+        `ASSERT_FATAL(s_axis.axis.tvalid[i],s);
+        s_axis.pull_word(read_word,last,i);
+        $sformat(s,"Read invalid FIFO word! Expected: %0d, Actual: %0d",k,read_word);
+        `ASSERT_FATAL(read_word == k,s);
+      end
+      `ASSERT_FATAL(~s_axis.axis.tvalid[i],"FIFO not empty after reading all entries!");
+    end
+    `TEST_CASE_DONE(1);
+
+    /********************************************************
+    ** Test 4 -- Randomized Write / Read Timing
+    ********************************************************/
+    `TEST_CASE_START("Randomized Write / Read");
+    for (int i = 0; i < NUM_FIFOS; i++) begin
+      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
+      fork
+      begin
+        write_word = 0;
+        for (int k = 0; k < NUM_ITERATIONS; k++) begin
+          while ($signed($random()) > 0) @(posedge clk);
+          m_axis.push_word(write_word,0,i);
+          write_word++;
+        end
+      end
+      begin
+        for (int k = 0; k < NUM_ITERATIONS; k++) begin
+          while ($signed($random()) > 0) @(posedge clk);
+          s_axis.pull_word(read_word,last,i);
+          $sformat(s,"Read invalid FIFO word! Expected: %0d, Actual: %0d",read_word,k);
+          `ASSERT_FATAL(read_word == k,s);
+        end
+      end
+      join
+    end
+    `TEST_CASE_DONE(1);
+    `TEST_BENCH_DONE;
+  end
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv
new file mode 100644
index 000000000..c2c69b963
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/axi_fifo_2clk_tb.sv
@@ -0,0 +1,121 @@
+//
+// Copyright 2016 Ettus Research
+//
+
+module axi_fifo_2clk_tb();
+
+    localparam WIDTH    = 32;
+    localparam SIZE     = 5;
+
+    reg                 s_axis_clk;
+    reg                 s_axis_rst;
+    reg [WIDTH-1:0]     s_axis_tdata;
+    reg                 s_axis_tvalid;
+    reg                 s_axis_tlast;
+    wire                s_axis_tready;
+    reg                 m_axis_clk;
+    reg                 m_axis_rst;
+    wire [WIDTH-1:0]    m_axis_tdata;
+    wire                m_axis_tvalid;
+    wire                m_axis_tlast;
+    reg                 m_axis_tready;
+    wire [SIZE:0]       s_axis_occupied;
+    wire                s_axis_full;
+    wire                s_axis_empty;
+    wire [SIZE:0]       m_axis_occupied;
+    wire                m_axis_full;
+    wire                m_axis_empty;
+
+    axi_fifo_2clk #(.SIZE(SIZE),.WIDTH(WIDTH)) axi_fifo_2clk (
+        .s_axis_clk(s_axis_clk),
+        .s_axis_rst(s_axis_rst),
+        .s_axis_tdata(s_axis_tdata),
+        .s_axis_tvalid(s_axis_tvalid),
+        .s_axis_tlast(s_axis_tlast),
+        .s_axis_tready(s_axis_tready),
+        .m_axis_clk(m_axis_clk),
+        .m_axis_rst(m_axis_rst),
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid),
+        .m_axis_tlast(m_axis_tlast),
+        .m_axis_tready(m_axis_tready),
+        .s_axis_occupied(s_axis_occupied),
+        .s_axis_full(s_axis_full),
+        .s_axis_empty(s_axis_empty),
+        .m_axis_occupied(m_axis_occupied),
+        .m_axis_full(m_axis_full),
+        .m_axis_empty(m_axis_empty));
+
+    `define S_AXIS_CLK_PERIOD 7
+    initial begin
+        s_axis_clk = 1'b0;
+        forever begin
+            #(`S_AXIS_CLK_PERIOD/2) s_axis_clk = ~s_axis_clk;
+        end
+    end
+
+    `define S_AXIS_RESET_PERIOD 70
+    initial begin
+        s_axis_rst = 1'b1;
+        #(`S_AXIS_RESET_PERIOD) s_axis_rst = 1'b0;
+    end
+
+    `define M_AXIS_CLK_PERIOD 10
+    initial begin
+        m_axis_clk = 1'b0;
+        forever begin
+            #(`M_AXIS_CLK_PERIOD/2) m_axis_clk = ~m_axis_clk;
+        end
+    end
+
+    `define M_AXIS_RESET_PERIOD 100
+    initial begin
+        m_axis_rst = 1'b1;
+        #(`M_AXIS_RESET_PERIOD) m_axis_rst = 1'b0;
+    end
+
+    initial begin
+        @(posedge m_axis_clk);
+        @(posedge s_axis_clk);
+        s_axis_tdata  = 'd0;
+        s_axis_tlast  = 1'b0;
+        s_axis_tvalid = 1'b0;
+        m_axis_tready = 1'b0;
+        assert(~s_axis_full && ~m_axis_full)                 else $error("FIFO is full during reset!");
+        assert(s_axis_empty == 1'b1 && m_axis_empty == 1'b1) else $error("FIFO is not empty during reset!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("FIFO is occupied during reset!");
+        while (s_axis_rst) @(negedge s_axis_rst);
+        while (m_axis_rst) @(negedge m_axis_rst);
+        @(posedge m_axis_clk);
+        @(posedge s_axis_clk);
+        assert(~s_axis_full && ~m_axis_full)                 else $error("FIFO is full after reset!");
+        assert(s_axis_empty == 1'b1 && m_axis_empty == 1'b1) else $error("FIFO is not empty after reset!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("FIFO is occupied after reset!");
+        // Fill FIFO
+        while (~s_axis_tready) @(posedge s_axis_clk);
+        for (int i = 0; i < 1 << DEPTH_LOG2; i++) begin
+            s_axis_tdata  = i+1'b1;
+            s_axis_tvalid = 1'b1;
+            @(posedge s_axis_clk);
+        end
+        repeat (6) @(posedge s_axis_clk);
+        assert(s_axis_full && m_axis_full) else $error("Incorrect FIFO full flag!");
+        assert(~s_axis_empty && ~m_axis_empty) else $error("Incorrect FIFO empty flag!");
+        assert(s_axis_occupied == (1 << DEPTH_LOG2) && m_axis_occupied == (1 << DEPTH_LOG2)) else $error("Incorrect FIFO occupied count!");
+        // Empty FIFO
+        s_axis_tdata  = 'd0;
+        s_axis_tvalid = 1'b0;
+        @(posedge m_axis_clk);
+        while (~m_axis_tvalid) @(posedge m_axis_clk);
+        for (int i = 0; i < 1 << DEPTH_LOG2; i++) begin
+            m_axis_tready = 1'b1;
+            @(posedge m_axis_clk);
+            assert(m_axis_tdata == i+1'b1) else $error("Incorrect FIFO data! (read)");
+        end
+        repeat (6) @(posedge m_axis_clk);
+        assert(~s_axis_full && ~m_axis_full) else $error("Incorrect FIFO full flag!");
+        assert(s_axis_empty && m_axis_empty) else $error("Incorrect FIFO empty flag!");
+        assert(s_axis_occupied == 0 && m_axis_occupied == 0) else $error("Incorrect FIFO occupied count!");
+    end
+
+endmodule
\ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk_sim.v b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk_sim.v
new file mode 100644
index 000000000..cf31ae2d9
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk_sim.v
@@ -0,0 +1,230 @@
+//
+// Copyright 2016 Ettus Research
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+module axi_fifo_2clk #(
+    parameter SYNC_STAGES = 2,
+    parameter SIZE        = 10,
+    parameter WIDTH       = 32,
+    parameter PIPELINE    = "<UNUSED>")
+(
+    input reset,
+    input i_aclk,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output reg i_tready = 1'b0,
+    input o_aclk,
+    output [WIDTH-1:0] o_tdata,
+    output reg o_tvalid = 1'b0,
+    input o_tready
+);
+
+    localparam FIFOSIZE = (SIZE < 5) ? 5 : SIZE;
+
+    // Synchronizers
+    wire o_rst_sync, i_rst_sync;
+    synchronizer #(
+        .INITIAL_VAL(1'b1),
+        .WIDTH(1),
+        .STAGES(SYNC_STAGES))
+    synchronizer_i_rst (
+        .clk(i_aclk), .rst(1'b0),
+        .in(reset), .out(i_rst_sync));
+    synchronizer #(
+        .INITIAL_VAL(1'b1),
+        .WIDTH(1),
+        .STAGES(SYNC_STAGES))
+    synchronizer_o_rst (
+        .clk(o_aclk), .rst(1'b0),
+        .in(reset), .out(o_rst_sync));
+
+    // Gray counter encode / decode + synchronizers
+    reg [FIFOSIZE-1:0] wr_addr, rd_addr;
+    wire [FIFOSIZE-1:0] wr_addr_sync, rd_addr_sync;
+    wire [FIFOSIZE-1:0] wr_addr_gray_sync, wr_addr_gray, rd_addr_gray_sync, rd_addr_gray;
+    synchronizer #(
+        .INITIAL_VAL(0),
+        .WIDTH(FIFOSIZE),
+        .STAGES(SYNC_STAGES))
+    synchronizer_rd_addr_gray (
+        .clk(i_aclk), .rst(o_rst_sync),
+        .in(rd_addr_gray), .out(rd_addr_gray_sync));
+    synchronizer #(
+        .INITIAL_VAL(0),
+        .WIDTH(FIFOSIZE),
+        .STAGES(SYNC_STAGES))
+    synchronizer_wr_addr_gray (
+        .clk(o_aclk), .rst(i_rst_sync),
+        .in(wr_addr_gray), .out(wr_addr_gray_sync));
+    bin2gray #(.WIDTH(FIFOSIZE))
+    bin2gray_wr_addr (.bin(wr_addr), .gray(wr_addr_gray));
+    bin2gray #(.WIDTH(FIFOSIZE))
+    bin2gray_rd_addr (.bin(rd_addr), .gray(rd_addr_gray));
+    gray2bin #(.WIDTH(FIFOSIZE))
+    gray2bin_wr_addr (.gray(wr_addr_gray_sync), .bin(wr_addr_sync));
+    gray2bin #(.WIDTH(FIFOSIZE))
+    gray2bin_rd_addr (.gray(rd_addr_gray_sync), .bin(rd_addr_sync));
+
+    reg [FIFOSIZE:0] i_occupied;
+    reg [FIFOSIZE:0] i_space;
+    reg i_full;
+    reg i_empty;
+    reg [FIFOSIZE:0] o_occupied;
+    reg [FIFOSIZE:0] o_space;
+    reg o_full;
+    reg o_empty;
+
+    reg [WIDTH:0] mem[0:2**(FIFOSIZE)-1];
+    integer i;
+    initial begin
+        for (i = 0; i < 1 << FIFOSIZE; i = i + 1) begin
+            mem[i] = 'd0;
+        end
+    end
+
+    // Write
+    always @(posedge i_aclk) begin
+        if (i_rst_sync) begin
+            wr_addr <= 'd0;
+        end else begin
+            if (i_tvalid & i_tready) begin
+                mem[wr_addr] <= i_tdata;
+                wr_addr      <= wr_addr + 1'b1;
+            end
+        end
+    end
+
+    // Write ready, full, empty, occupied signals
+    always @(posedge i_aclk) begin
+        if (i_rst_sync) begin
+            i_tready   <= 1'b0;
+            i_full     <= 1'b0;
+            i_empty    <= 1'b1;
+            i_occupied <= 'd0;
+            i_space    <= (1'b1 << FIFOSIZE);
+        end else begin
+            if ((rd_addr_sync-1'b1 == wr_addr) & i_tvalid & i_tready) begin
+                i_tready <= 1'b0;
+                i_full   <= 1'b1;
+            end else if ((rd_addr_sync != wr_addr) & i_full) begin
+                i_tready <= 1'b1;
+                i_full   <= 1'b0;
+            end
+            if ((rd_addr_sync == wr_addr) & ~i_full) begin
+                i_tready <= 1'b1;
+                if (~i_tvalid) begin
+                    i_empty  <= 1'b1;
+                end
+            end else begin
+                i_empty  <= 1'b0;
+            end
+            if (i_tvalid) begin
+                if (wr_addr == rd_addr_sync) begin
+                    if (i_full) begin
+                        i_occupied <= 1'b1 << FIFOSIZE;
+                        i_space    <= 'd0;
+                    end else begin
+                        i_occupied <= 'd1;
+                        i_space    <= (1'b1 << FIFOSIZE)-1'b1;
+                    end
+                end else if (wr_addr > rd_addr_sync) begin
+                    i_occupied <= wr_addr - rd_addr_sync + 1'b1;
+                    i_space    <= (1'b1 << FIFOSIZE) - (wr_addr - rd_addr_sync + 1'b1);
+                end else begin
+                    i_occupied <= wr_addr+1'b1 + (1'b1 << FIFOSIZE)-1'b1 - rd_addr_sync + 1'b1;
+                    i_space    <= rd_addr_sync - wr_addr - 1'b1;
+                end
+            end else begin
+                if (wr_addr == rd_addr_sync) begin
+                    if (i_full) begin
+                        i_occupied <= 1'b1 << FIFOSIZE;
+                        i_space    <= 'd0;
+                    end else begin
+                        i_occupied <= 'd0;
+                        i_space    <= 1'b1 << FIFOSIZE;
+                    end
+                end else if (wr_addr > rd_addr_sync) begin
+                    i_occupied <= wr_addr - rd_addr_sync;
+                    i_space    <= (1'b1 << FIFOSIZE) - (wr_addr - rd_addr_sync);
+                end else begin
+                    i_occupied <= wr_addr+1'b1 + (1'b1 << FIFOSIZE)-1'b1 - rd_addr_sync;
+                    i_space    <= rd_addr_sync - wr_addr;
+                end
+            end
+        end
+    end
+
+    // Read
+    always @(posedge o_aclk) begin
+        if (o_rst_sync) begin
+            rd_addr <= 'd0;
+        end else begin
+            if (o_tvalid & o_tready) begin
+                rd_addr <= rd_addr + 1'b1;
+            end
+        end
+    end
+
+    assign o_tdata = mem[rd_addr];
+
+    // Read valid, full, empty, occupied signals
+    always @(posedge o_aclk) begin
+        if (o_rst_sync) begin
+            o_tvalid   <= 1'b0;
+            o_full     <= 1'b0;
+            o_empty    <= 1'b1;
+            o_occupied <= 'd0;
+            o_space    <= 'd0;
+        end else begin
+            if ((rd_addr+1'b1 == wr_addr_sync) & o_tready & o_tvalid) begin
+                o_tvalid <= 1'b0;
+                o_empty  <= 1'b1;
+            end else if ((rd_addr != wr_addr_sync) & o_empty) begin
+                o_tvalid <= 1'b1;
+                o_empty  <= 1'b0;
+            end
+            if ((rd_addr == wr_addr_sync) & ~o_empty & ~o_tready) begin
+                o_full   <= 1'b1;
+            end else begin
+                o_full   <= 1'b0;
+            end
+            if (o_tready) begin
+                if (wr_addr_sync == rd_addr) begin
+                    if (~o_empty) begin
+                        o_occupied <= (1'b1 << FIFOSIZE) - 1'b1;
+                        o_space    <= 'd1;
+                    end else begin
+                        o_occupied <= 'd0;
+                        o_space    <= (1'b1 << FIFOSIZE);
+                    end
+                end else if (wr_addr_sync > rd_addr) begin
+                    o_occupied <= wr_addr_sync - rd_addr - 1'b1;
+                    o_space    <= (1'b1 << FIFOSIZE) - (wr_addr_sync - rd_addr - 1'b1);
+                end else begin
+                    o_occupied <= wr_addr_sync+1'b1 + (1'b1 << FIFOSIZE)-1'b1 - rd_addr - 1'b1;
+                    o_space    <= rd_addr - wr_addr_sync + 1'b1;
+                end
+            end else begin
+                if (wr_addr_sync == rd_addr) begin
+                    if (~o_empty) begin
+                        o_occupied <= 1'b1 << FIFOSIZE;
+                        o_space    <= 'd0;
+                    end else begin
+                        o_occupied <= 'd0;
+                        o_space    <= 1'b1 << FIFOSIZE;
+                    end
+                end else if (wr_addr_sync > rd_addr) begin
+                    o_occupied <= wr_addr_sync - rd_addr;
+                    o_space    <= (1'b1 << FIFOSIZE) - (wr_addr_sync - rd_addr);
+                end else begin
+                    o_occupied <= wr_addr_sync+1'b1 + (1'b1 << FIFOSIZE)-1'b1 - rd_addr;
+                    o_space    <= rd_addr - wr_addr_sync;
+                end
+            end
+        end
+    end
+
+endmodule
diff --git a/fpga/usrp3/lib/sim/fifo/axi_fifo_32_64/axi_fifo_32_64_tb.v b/fpga/usrp3/lib/sim/fifo/axi_fifo_32_64/axi_fifo_32_64_tb.v
new file mode 100644
index 000000000..b3acab3ca
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_fifo_32_64/axi_fifo_32_64_tb.v
@@ -0,0 +1,121 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+`timescale 1ns/1ps
+
+module axi_fifo_32_64_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("axi_fifo_32_64_tb.vcd");
+   initial $dumpvars(0,axi_fifo_32_64_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [2:0]  user;
+      input [31:0] len;
+      
+      begin
+	 @(posedge clk);
+	 {i_tuser, i_tlast, i_tdata} <= { 3'd0, 1'b0, data_start };
+	 repeat(len-1)
+	   begin
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+	   end
+	 i_tuser <= user;
+	 i_tlast <= 1;
+	 @(posedge clk);
+	 i_tvalid <= 1'b0;
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   reg [63:0] i_tdata;
+   reg [2:0]  i_tuser;
+   reg 	      i_tlast;
+   reg 	      i_tvalid;
+   wire       i_tready;
+
+   wire [63:0] i_tdata_int;
+   wire [2:0]  i_tuser_int;
+   wire        i_tlast_int, i_tvalid_int, i_tready_int;
+
+   wire [63:0] o_tdata;
+   wire [31:0] o_tdata_int, o_tdata_int2;
+   wire [2:0]  o_tuser;
+   wire [1:0]  o_tuser_int, o_tuser_int2;
+   wire        o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int;
+   wire        o_tlast_int2, o_tvalid_int2, o_tready_int2;
+   
+   localparam RPT_COUNT = 16;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	send_packet(64'hA0000000_A0000001, 3'd7, 4);
+	@(posedge clk);
+     end // initial begin
+
+   axi_fifo #(.WIDTH(68), .SIZE(10)) fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
+
+   axi_fifo64_to_fifo32 dut
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(i_tdata_int), .i_tuser(i_tuser_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata(o_tdata_int), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+
+   /*
+   axi_fifo #(.WIDTH(35), .SIZE(10)) fifo_middle
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast_int2,o_tuser_int2,o_tdata_int2}), .o_tvalid(o_tvalid_int2), .o_tready(o_tready_int2));
+*/
+   assign o_tdata_int2 = o_tdata_int;
+   assign o_tlast_int2 = o_tlast_int;
+   assign o_tuser_int2 = o_tuser_int;
+   assign o_tvalid_int2 = o_tvalid_int;
+   assign o_tready_int = o_tready_int2;
+   
+   axi_fifo32_to_fifo64 dut2
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(o_tdata_int2), .i_tuser(o_tuser_int2), .i_tlast(o_tlast_int2), .i_tvalid(o_tvalid_int2), .i_tready(o_tready_int2),
+      .o_tdata(o_tdata), .o_tuser(o_tuser), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   assign o_tready = 1'b1;
+   
+   always @(posedge clk)
+     if(i_tvalid & i_tready)
+       $display("IN: TUSER %x\tTLAST %x\tTDATA %x", i_tuser, i_tlast, i_tdata);
+
+   always @(posedge clk)
+     if(o_tvalid_int & o_tready_int)
+       $display("\t\t\t\t\t\tMIDDLE: TUSER %x\tTLAST %x\tTDATA %x", o_tuser_int, o_tlast_int, o_tdata_int);
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("\t\t\t\t\t\t\t\t\t\t\tOUT: TUSER %x\tTLAST %x\tTDATA %x", o_tuser, o_tlast, o_tdata);
+
+endmodule // axi_fifo_32_64_tb
diff --git a/fpga/usrp3/lib/sim/fifo/axi_packet_gate/axi_packet_gate_tb.v b/fpga/usrp3/lib/sim/fifo/axi_packet_gate/axi_packet_gate_tb.v
new file mode 100644
index 000000000..9df01baf0
--- /dev/null
+++ b/fpga/usrp3/lib/sim/fifo/axi_packet_gate/axi_packet_gate_tb.v
@@ -0,0 +1,112 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+`timescale 1ns/1ps
+
+module axi_packet_gate_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("axi_packet_gate_tb.vcd");
+   initial $dumpvars(0,axi_packet_gate_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [2:0]  user;
+      input [31:0] len;
+      input 	   error;
+      
+      begin
+	 // Send a packet
+	 @(posedge clk);
+	 {i_terror, i_tuser, i_tlast, i_tdata} <= { 1'b0, user, 1'b0, data_start };
+	 repeat(len-1)
+	   begin
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tdata <= i_tdata + 1;
+	   end
+	 i_tlast <= 1;
+	 i_terror <= error;
+	 i_tdata <= i_tdata + 1;
+	 @(posedge clk);
+	 i_tvalid <= 1'b0;
+	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   wire [63:0]  o_tdata;
+   reg [63:0] 	i_tdata;
+   wire [2:0] 	o_tuser;
+   reg [2:0] 	i_tuser;
+   reg 		i_tlast;
+   wire 	o_tlast;
+   wire		o_tvalid, i_tready;
+   reg 		i_tvalid, o_tready;
+   reg 		i_terror;
+   
+   localparam RPT_COUNT = 16;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	send_packet(64'hA0,3'd0, 16, 0);
+	send_packet(64'hB0,3'd0, 16, 0);
+	o_tready <= 1;
+	send_packet(64'hC0,3'd0, 16, 1);
+	send_packet(64'hD0,3'd0, 16, 0);
+	send_packet(64'hE0,3'd0, 16, 0);
+	send_packet(64'hF0,3'd0, 16, 0);
+
+	@(posedge clk);
+
+     end // initial begin
+
+   wire i_terror_int, i_tlast_int, i_tready_int, i_tvalid_int;
+   wire [2:0] i_tuser_int;
+   wire [63:0] i_tdata_int;
+   wire o_tlast_int, o_tready_int, o_tvalid_int;
+   wire [2:0] o_tuser_int;
+   wire [63:0] o_tdata_int;
+   
+   axi_fifo #(.WIDTH(69), .SIZE(10)) fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_terror,i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({i_terror_int,i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
+
+   axi_packet_gate #(.WIDTH(67), .SIZE(10)) dut
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tuser_int,i_tdata_int}), .i_terror(i_terror_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata({o_tuser_int,o_tdata_int}), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+
+   axi_fifo #(.WIDTH(68), .SIZE(10)) fifo_out
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast,o_tuser,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("TUSER %x\tTLAST %x\tTDATA %x",o_tuser,o_tlast, o_tdata);
+
+endmodule // axi_packet_gate_tb