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| author | Wade Fife <wade.fife@ettus.com> | 2020-07-02 13:50:23 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-07-20 15:33:22 -0500 |
| commit | e962cc4a5e51e2326eb656ee2a779ea26774687b (patch) | |
| tree | 48a02d613160a7d3a84d6dea351ae1c4be7d5c4a /fpga/usrp3/lib/rfnoc/xport_sv | |
| parent | dc32aa5cd4fb174ee3c616f854f499a53137aa75 (diff) | |
| download | uhd-e962cc4a5e51e2326eb656ee2a779ea26774687b.tar.gz uhd-e962cc4a5e51e2326eb656ee2a779ea26774687b.tar.bz2 uhd-e962cc4a5e51e2326eb656ee2a779ea26774687b.zip | |
fpga: rfnoc: Fix testbenches to run under ModelSim
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/xport_sv')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile b/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile index b2cc6908e..d40b6f341 100644 --- a/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile +++ b/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile @@ -30,13 +30,8 @@ include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs -BUILD_IP_DIR = $(abspath $(BASE_DIR)/x300/build-ip/xc7k410tffg900-2) - -IP_SRC = \ -$(abspath $(BUILD_IP_DIR)/fifo_short_2clk/fifo_short_2clk_sim_netlist.v) -# Xilinx IP wants lots of libraries -MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm -MODELSIM_ARGS += glbl -t 1fs +IP_DIR = $(BASE_DIR)/x300/ip +include $(BASE_DIR)/x300/ip/fifo_short_2clk/Makefile.inc DESIGN_SRCS = $(abspath \ eth_ifc_synth_test.sv \ @@ -51,22 +46,26 @@ $(RFNOC_XPORT_SRCS) \ $(RFNOC_XPORT_SV_SRCS) \ $(RFNOC_XBAR_SRCS) \ $(RFNOC_CORE_SRCS) \ -$(IP_SRC) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ ) #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module +MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4 +MODELSIM_ARGS += glbl -t 1fs +# Define toplevel module TB_TOP_MODULE ?= eth_ifc_all_tb #TB_TOP_MODULE ?= eth_ifc_synth_test SIM_TOP = $(TB_TOP_MODULE) SIM_SRCS = \ +$(abspath $(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v) \ $(abspath eth_ifc_tb.sv) \ -$(abspath $(TB_TOP_MODULE).sv) +$(abspath $(TB_TOP_MODULE).sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ -# supressing the following worthless reminder. +# Suppressing the following worthless reminder. #* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] - # Extra checking for conflicts with always_comb and always_latch variables is done at vopt time SVLOG_ARGS = -suppress 2583 -keep_delta |