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| author | Michael West <michael.west@ettus.com> | 2020-03-15 01:17:50 -0700 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-05-12 12:03:31 -0500 |
| commit | 12dfb97c8efce40494efb35bdd81d06b6f8b9b62 (patch) | |
| tree | 7a5e7f12425dd6a3c5fbb9e2b2ff7faf3a276482 /fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc | |
| parent | 7886b71f13e9f6e5786c95286ef98f49ab716119 (diff) | |
| download | uhd-12dfb97c8efce40494efb35bdd81d06b6f8b9b62.tar.gz uhd-12dfb97c8efce40494efb35bdd81d06b6f8b9b62.tar.bz2 uhd-12dfb97c8efce40494efb35bdd81d06b6f8b9b62.zip | |
DUC/DDC: Add variable time increment
Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample. Defaults to legacy behavior.
Minor compat number bumped on DUC and DDC blocks.
Signed-off-by: Michael West <michael.west@ettus.com>
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v | 6 | ||||
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh | 3 |
2 files changed, 6 insertions, 3 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v index 69e816980..48a439105 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v @@ -1,5 +1,6 @@ // // Copyright 2019 Ettus Research, a National Instruments Company +// Copyright 2020 Ettus Research, a National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -73,7 +74,7 @@ module rfnoc_block_duc #( localparam NIPC = 1; localparam COMPAT_MAJOR = 16'h0; - localparam COMPAT_MINOR = 16'h0; + localparam COMPAT_MINOR = 16'h1; `include "rfnoc_block_duc_regs.vh" `include "../../core/rfnoc_axis_ctrl_utils.vh" @@ -316,7 +317,8 @@ module rfnoc_block_duc #( .MAX_M(MAX_M), .SR_N_ADDR(SR_N_ADDR), .SR_M_ADDR(SR_M_ADDR), - .SR_CONFIG_ADDR(SR_CONFIG_ADDR)) + .SR_CONFIG_ADDR(SR_CONFIG_ADDR), + .SR_TIME_INCR_ADDR(SR_TIME_INCR_ADDR)) axi_rate_change ( .clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user), .src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]), diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh index fa239857e..dd87a2250 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh @@ -1,5 +1,6 @@ // // Copyright 2019 Ettus Research, A National Instruments Company +// Copyright 2020 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -22,4 +23,4 @@ localparam SR_CONFIG_ADDR = 130; localparam SR_INTERP_ADDR = 131; localparam SR_FREQ_ADDR = 132; localparam SR_SCALE_IQ_ADDR = 133; - +localparam SR_TIME_INCR_ADDR = 137; |