From 12dfb97c8efce40494efb35bdd81d06b6f8b9b62 Mon Sep 17 00:00:00 2001 From: Michael West Date: Sun, 15 Mar 2020 01:17:50 -0700 Subject: DUC/DDC: Add variable time increment Sets time increment based on tick rate and sample rate instead of assuming one tick per sample. Defaults to legacy behavior. Minor compat number bumped on DUC and DDC blocks. Signed-off-by: Michael West --- fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v | 6 ++++-- fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc') diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v index 69e816980..48a439105 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v @@ -1,5 +1,6 @@ // // Copyright 2019 Ettus Research, a National Instruments Company +// Copyright 2020 Ettus Research, a National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -73,7 +74,7 @@ module rfnoc_block_duc #( localparam NIPC = 1; localparam COMPAT_MAJOR = 16'h0; - localparam COMPAT_MINOR = 16'h0; + localparam COMPAT_MINOR = 16'h1; `include "rfnoc_block_duc_regs.vh" `include "../../core/rfnoc_axis_ctrl_utils.vh" @@ -316,7 +317,8 @@ module rfnoc_block_duc #( .MAX_M(MAX_M), .SR_N_ADDR(SR_N_ADDR), .SR_M_ADDR(SR_M_ADDR), - .SR_CONFIG_ADDR(SR_CONFIG_ADDR)) + .SR_CONFIG_ADDR(SR_CONFIG_ADDR), + .SR_TIME_INCR_ADDR(SR_TIME_INCR_ADDR)) axi_rate_change ( .clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user), .src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]), diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh index fa239857e..dd87a2250 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh @@ -1,5 +1,6 @@ // // Copyright 2019 Ettus Research, A National Instruments Company +// Copyright 2020 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -22,4 +23,4 @@ localparam SR_CONFIG_ADDR = 130; localparam SR_INTERP_ADDR = 131; localparam SR_FREQ_ADDR = 132; localparam SR_SCALE_IQ_ADDR = 133; - +localparam SR_TIME_INCR_ADDR = 137; -- cgit v1.2.3