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| author | Wade Fife <wade.fife@ettus.com> | 2020-05-07 14:43:32 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-05-19 14:22:55 -0500 |
| commit | a40f2a4a5d04aad3ef3e222033fbacc521233782 (patch) | |
| tree | 98137f9d7e2b8a00f20b6c2dd9366185ec9bf2d1 /fpga/usrp3/lib/dsp | |
| parent | eb4bedf3133ce1ed275d03b36839ec61d75f2e60 (diff) | |
| download | uhd-a40f2a4a5d04aad3ef3e222033fbacc521233782.tar.gz uhd-a40f2a4a5d04aad3ef3e222033fbacc521233782.tar.bz2 uhd-a40f2a4a5d04aad3ef3e222033fbacc521233782.zip | |
fpga: rfnoc: Add Vector IIR RFNoC block
Diffstat (limited to 'fpga/usrp3/lib/dsp')
| -rw-r--r-- | fpga/usrp3/lib/dsp/variable_delay_line.v | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/fpga/usrp3/lib/dsp/variable_delay_line.v b/fpga/usrp3/lib/dsp/variable_delay_line.v index ccef6172f..b31cdade0 100644 --- a/fpga/usrp3/lib/dsp/variable_delay_line.v +++ b/fpga/usrp3/lib/dsp/variable_delay_line.v @@ -42,9 +42,7 @@ module variable_delay_line #( input wire [$clog2(DEPTH)-1:0] delay, output wire [WIDTH-1:0] data_out ); - //FIXME: Change to localparam when Vivado doesn't freak out - // about the use of clog2. - parameter ADDR_W = $clog2(DEPTH+1); + localparam ADDR_W = $clog2(DEPTH+1); localparam DATA_W = WIDTH; //----------------------------------------------------------- |