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authorMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
committerMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
commitfd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch)
tree3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/lib/dsp/Makefile.srcs
parent3b66804e41891e358c790b453a7a59ec7462dba4 (diff)
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Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/dsp/Makefile.srcs')
-rw-r--r--fpga/usrp3/lib/dsp/Makefile.srcs40
1 files changed, 0 insertions, 40 deletions
diff --git a/fpga/usrp3/lib/dsp/Makefile.srcs b/fpga/usrp3/lib/dsp/Makefile.srcs
deleted file mode 100644
index 44bd6f930..000000000
--- a/fpga/usrp3/lib/dsp/Makefile.srcs
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# Copyright 2013 Ettus Research LLC
-#
-
-##################################################
-# DSP Sources
-##################################################
-DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/dsp/, \
-ddc_chain_x300.v \
-ddc_chain.v \
-duc_chain.v \
-sign_extend.v \
-cordic_z24.v \
-clip_reg.v \
-cordic_stage.v \
-clip.v \
-cic_strober.v \
-cic_decim.v \
-cic_interp.v \
-cic_dec_shifter.v \
-cic_int_shifter.v \
-small_hb_dec.v \
-small_hb_int.v \
-hb_dec.v \
-hb_interp.v \
-round_sd.v \
-add2_and_clip_reg.v \
-add2_and_clip.v \
-add2.v \
-add2_reg.v \
-add2_and_round_reg.v \
-add2_and_round.v \
-round_reg.v \
-round.v \
-srl.v \
-acc.v \
-rx_frontend.v \
-tx_frontend.v \
-rx_dcoffset.v \
-))