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| author | Wade Fife <wade.fife@ettus.com> | 2021-03-02 10:25:57 -0600 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-03 11:26:54 -0500 |
| commit | c64258e09b221d0bfeb55e01085a20e37c5b62ba (patch) | |
| tree | 452efc39a225538f19549200a17f8fdd20a7481b /fpga/usrp3/lib/axi4s_sv | |
| parent | 7f36cced81fb05d3cc107a0a0773fcdfc26f8d64 (diff) | |
| download | uhd-c64258e09b221d0bfeb55e01085a20e37c5b62ba.tar.gz uhd-c64258e09b221d0bfeb55e01085a20e37c5b62ba.tar.bz2 uhd-c64258e09b221d0bfeb55e01085a20e37c5b62ba.zip | |
fpga: lib: Add clock domain comments to interfaces
Diffstat (limited to 'fpga/usrp3/lib/axi4s_sv')
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv index d312b6f32..647e1dc1c 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv @@ -14,6 +14,7 @@ module axi4s_fifo #( int SIZE = 1 // default size set to one to act as a pipe phase ) ( + // Clock domain: i.clk (o.clk is unused) input logic clear=1'b0, interface i, // AxiStreamIf or AxiStreamPacketIf interface o, // AxiStreamIf or AxiStreamPacketIf |