From c64258e09b221d0bfeb55e01085a20e37c5b62ba Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Tue, 2 Mar 2021 10:25:57 -0600 Subject: fpga: lib: Add clock domain comments to interfaces --- fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv | 1 + 1 file changed, 1 insertion(+) (limited to 'fpga/usrp3/lib/axi4s_sv') diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv index d312b6f32..647e1dc1c 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv @@ -14,6 +14,7 @@ module axi4s_fifo #( int SIZE = 1 // default size set to one to act as a pipe phase ) ( + // Clock domain: i.clk (o.clk is unused) input logic clear=1'b0, interface i, // AxiStreamIf or AxiStreamPacketIf interface o, // AxiStreamIf or AxiStreamPacketIf -- cgit v1.2.3