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authorJosh Blum <josh@joshknows.com>2012-04-09 16:37:46 -0700
committerJosh Blum <josh@joshknows.com>2012-04-09 16:37:46 -0700
commit1e143bddd2a246ca6ffae6fb54aa416b35293078 (patch)
tree6257015af38732f6ecc0837e33b817ea8ff4c5f4 /fpga/usrp2/top/N2x0
parent00c241844a62c22cac538316d507c524acc1c393 (diff)
parentf136b06211dc0fe572d77219b6ce579963d435fe (diff)
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Merge branch 'fpga_maint' into maint
Diffstat (limited to 'fpga/usrp2/top/N2x0')
-rw-r--r--fpga/usrp2/top/N2x0/u2plus_core.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v
index 369f01183..abc32406e 100644
--- a/fpga/usrp2/top/N2x0/u2plus_core.v
+++ b/fpga/usrp2/top/N2x0/u2plus_core.v
@@ -436,8 +436,8 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd9, 16'd0}; //major, minor
- wire [31:0] churn = status; //tweak churn until timing meets!
+ localparam compat_num = {16'd9, 16'd1}; //major, minor
+ wire [31:0] churn = 0; //tweak churn until timing meets!
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),