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| author | Josh Blum <josh@joshknows.com> | 2011-07-08 12:17:54 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-07-08 12:17:54 -0700 |
| commit | 17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9 (patch) | |
| tree | e2d0d39d6b44b72c759b8be1380b2024de50bdf6 /fpga/usrp2/top/E1x0/core_compile | |
| parent | 60933a242cce0b1ec45e9f948e3da9ab72b2fd90 (diff) | |
| parent | 4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4 (diff) | |
| download | uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.tar.gz uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.tar.bz2 uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/E1x0/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/E1x0/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile index dc0cd081e..02d7f006e 100755 --- a/fpga/usrp2/top/E1x0/core_compile +++ b/fpga/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |