diff options
| author | Josh Blum <josh@joshknows.com> | 2011-07-08 12:17:54 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-07-08 12:17:54 -0700 |
| commit | 17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9 (patch) | |
| tree | e2d0d39d6b44b72c759b8be1380b2024de50bdf6 /fpga | |
| parent | 60933a242cce0b1ec45e9f948e3da9ab72b2fd90 (diff) | |
| parent | 4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4 (diff) | |
| download | uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.tar.gz uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.tar.bz2 uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga')
47 files changed, 5325 insertions, 768 deletions
diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs index a3a5d826d..5b2bc665a 100644 --- a/fpga/usrp2/coregen/Makefile.srcs +++ b/fpga/usrp2/coregen/Makefile.srcs @@ -24,4 +24,6 @@ fifo_xlnx_512x36_2clk_18to36.v \ fifo_xlnx_512x36_2clk_18to36.xco \ fifo_xlnx_512x36_2clk_prog_full.v \ fifo_xlnx_512x36_2clk_prog_full.xco \ +fifo_xlnx_1Kx18_2clk.v \ +fifo_xlnx_1Kx18_2clk.xco \ )) diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp index dd85a7f50..01d31bf5b 100644 --- a/fpga/usrp2/coregen/coregen.cgp +++ b/fpga/usrp2/coregen/coregen.cgp @@ -1,5 +1,4 @@ -# Date: Fri Oct 15 07:50:19 2010 - +# Date: Fri Jun 10 23:12:37 2011 SET addpads = false SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped @@ -19,4 +18,3 @@ SET verilogsim = true SET vhdlsim = false SET workingdirectory = /tmp/ -# CRC: 983b9b45 diff --git a/fpga/usrp2/coregen/fifo_generator_ug175.pdf b/fpga/usrp2/coregen/fifo_generator_ug175.pdf Binary files differindex 5fba6029c..2c3e3c200 100644 --- a/fpga/usrp2/coregen/fifo_generator_ug175.pdf +++ b/fpga/usrp2/coregen/fifo_generator_ug175.pdf diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.ngc new file mode 100644 index 000000000..dc9519357 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$4464g<,[o}e~g`n;"2*413&;$>"9 > %02?*rjx&Uhk"hffn]{hk~X9Br:4R<llj,mcj7<8<1;<=>?4193456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0127?5238;1;4<5>3:3-445<990BB][[:@FGVD:>294:?6??:HLSQQ<FLMXI044?>0d855<NFY__6}|`g^gntqX|axne26:1<12>772@D[YY4rne\ahvsqV~c~h}g_`qpawr;13:5>;5>0;KMTPR=x{elShctx]wlwct`Vdnklzj<883:4c<990BB][[:qplcZ`rdeUdk|h=;94;4238:1EC^ZT;rqkbYa}efTxe|jsi]bwvcu|531<3<:;029MKVR\3zycjQiumn\pmtb{aUeijo{e=;94;7f38;1CXZ_UU8geqgXkfex1??:1<2`>762F__\XZ5re]geqgXkfex1??:1<2`>762F__\XZ5ws]geqgXkfex1??:1<26>712@D[YY4KI@>21?699;1::7GAPTV9@LD;9<0;2<=4178LQQVR\3NDM1?::1<27>712F__\XZ5DN@?50<76880=54FNQWW>aoi48=1<3?;;0:9KPRW]]0ocxz31683:4=5<28;<=<42932?7<NFY__6IG_A=394;763;0BB][[:EKSF97=87;97?4@UURVP?BHXH6:6=0>2:09KPRW]]0OC]L31;2=0>5799n0?~<?01dd000*=81?86;;543821=18J:97;<=;7;7?3?>>=1=5L?=;7A7?3EDK;1=I?58F594BC@631804=:481236>>5923?74>?939:21=>>?3?7L<NA59BE7G?3HNO^L2?>99B@ATF48437LJKR@>1:==FLMXJ0>07;@FGVD:3611JHI\N<4<;?DBCZH6=255NDEPB828?3HNO^L27>`9B@ATF400;255NDEPB8<8?3HNO^O2?>99B@ATE48437LJKRC>1:==FLMXI0>07;@FGVG:3611JHI\M<4<;?DBCZK6=255NDEPA828?3HNO^O27>`9B@ATE400;255NDEPA8<8>3HYRBNQ]EF68FDGF;2H^>55MUR]JJCI63J>0OL6N2:AF57=D@LI@SAGLEOQF[Q_WM;1HE95LLJC7?FJLJ:1H@_74CNONMQRBL8>0OB\J_FGMAWGSAFDTECH@7:AQADRBL81O86J:8108@L0<L@K7<394DHC?55803MCJ0<?17:FJE9756>1OEL2>3?58@LG;9=427IGN<0794;1<L@K7=809;EKB84813MCJ0?09;EKB86813MCJ0909;EKB80813MCJ0;09;EKB82813MCJ0509;EKB8<813MCI0=08;EKA8469?2NBN1?>>69GMG:6:7=0HDL312<4?AOE48>556JFB=36>5803MCI0<;16:FJF979>2NBN1<16:FJF959>2NBN1:16:FJF939>2NBN1816:FJF919>2NBN1616:FJF9?9?2NB\L2?>89GMUG;93:5;6JFP@>2:2=CAYH7<374DHRA84<76>1OE]L31?48@JG;87=0HBO311<4?AIF48;5;6J@A=31:2=CGH6:?394DNC?518>3MEJ0<;50?58@JG;9<4=7IAN<0<5?AIF4;4=7IAN<2<5?AIF4=4=7IAN<4<5?AIF4?4=7IAN<6<5?AIF414=7IAN<8<5?AIE494<7IAM<02=3>BHJ5;:2:5KOC>26;1<LFH7=>08;EMA842912NDN1?::1<4?AIE48?5:6J@B=3=2>BHJ585:6J@B=1=2>BHJ5>5:6J@B=7=2>BHJ5<5:6J@B=5=2>BHJ525:6J@B=;=3>BHXH6;245KOQC?5?69?2ND\L2>>69GKUD;8730HB^M<083:2=CGYH7=3?4E59FE1633LKH<>5JN@18AKD53O297KJ<;GF@0>@CKL>0JIM_3:DGT1=ALYO?7KH8F49Eeiub92M87J@K1:K1?L653@;97D<=;H1;?LHN\YU;<55FNHVS[57?3@DBX]Q?299JJLRWW9937D@FTQ]30==NF@^[S=;7;HLJPUY7>11BBDZ__15:?LHN\Z^JXH94IOKW[5603@DBXR>>7:KMMQY7:>1BBDZP0258MKOSW9><7D@FT^263>OIA]U;::5FNHV\421<AGC_S=68;HLJPZ6>?2CEEYQ?A69JJLRX8K=0ECG[_1A4?LHN\V:O;6GAIU]3A2=NF@^T<K94IOKW[4603@DBXR?>7:KMMQY6:>1BBDZP1258MKOSW8><7D@FT^363>OIA]U:::5FNHV\521<AGC_S<68;HLJPZ7>?2CEEYQ>A69JJLRX9K=0ECG[_0A4?LHN\V;O;6GAIU]2A2=NF@^T=K94IOKW[7603@DBXR<>7:KMMQY5:>1BBDZP2258MKOSW;><7D@FT^063>OIA]U9::5FNHV\621<AGC_S?68;HLJPZ4>?2CEEYQ=A69JJLRX:K=0ECG[_3A4?LHN\V8O;6GAIU]1A2=NF@^T>K94IOKW[6603@DBXR=>7:KMMQY4:>1BBDZP3258MKOSW:><7D@FT^163>OIA]U8::5FNHV\721<AGC_S>68;HLJPZ5>?2CEEYQ<A69JJLRX;K=0ECG[_2A4?LHN\V9O;6GAIU]0A2=NF@^T?K84IOKW[D0<AGC_SO=4IOT0?LIE:2FB>6B@6:NLEACC?2FDKDMNL59OQQ733E__>;5CUU0\@1=K]]9=7A[[3^F5?ISS;VF?7A[[479OQQ2XL?1GYY:PL49NWBII=2G^TNWl;LcikwPbzzcdbn5BiomqR`ttafd97C?<;O330>H68<>0B<>94:L2422<F8:386@>0818J4733G;:<95A1037?K76:=1E=<=;;O3201=I98??7C?>659M54133G;:495A10;0?K75<2D:>=:4N0020>H6:;>0B<<<4:L2612<F882?6@>359M56633G;8=95A1207?K74;=1E=>:;;O3011=I9:<?7C?<759M56>33G;85>5A1568J425<2D:8>:4N0670>H6<<>0B<:94:L2022<F8>386@>4818J4333G;><95A1437?K72::1E=;=4N050?K7?;2D:5?5A229M655<F;;87C<=3:L176=I:<90B?9<;O137>H49:1E?>=4N277?K529:1E?;=4N250?K5?<2D84<=4N2;1?K243G>;?6@;139M27=I?;1E4>5A8518J=343G2<?6@7939M=6=I19l0BOQMURRJJZVUGYY<7CK[WNPH0>HHFL;0C?5@K09S0>VFZ]k0\D@PBTQJ@]d<X@DTNX]AALG0?UTB92[n7_OBB04\W4>X[82:7^?<;RKN[FIKD@YBCCQLHDAH2>UH][IN;6]]V@N\E2=TZ_KGSO:4SRPB0>UTZK>0XT^J339V4*aun'xm#jmw.bnh|*Kg{UyhR~ats]dgZ~hz9:;<R\jstnw564<]9%l~k }f.e`|+ekcq%Ftb|Pre]sjqtXojUsc>?00]Qavsk|8997X> gsd-vc)`kq$h`fv Mymq[wbXxg~ySjmPxnp3454XZly~`y?<2:W3+bta&{l$knv!cmi{+H~hzVxoS}`{r^e`[}iu89:8S_k|umv277=R8&myj#|i/fa{*fjlp&GscQ}d^rmpwY`kVrd~=>?4^Pfwpjs9:80Y=!hrg,qb*adp'iggu!Bxnp\vaYwf}xTknQwos2340YUmzgx<==;T2,cw`)zo%lou lljz,I}iuW{nT|cz}_fa\|jt789<T^h}zlu306>S7'nxm"h gbz-gim'Drd~R|k_qlwvZadWqey<=>8_Sgpqir6;;1^<"i}f/pe+be&jf`t"Cwos]q`Zvi|{UloRv`r123<ZTb{|f=><4U1-dvc(un&mht#mcky-N|jtX{U{by|Pgb]{kw6789UYi~{ct011?P6(o{l%~k!hcy,`hn~(EqeySz|Ppovq[beXpfx;<=?PRdqvhq74:2_;#j|i.sd,cf~)keas#@v`r^uq[uhszVmhSua}0121[Wct}e~:??5Z0.eqb+ta'nis"nbdx.O{kwYpzVzexQhc^zlv567;VXnxb{1208Q5)`zo$yj"ilx/aoo})JpfxT{Qnup\cfYg{:;<9Q]erwop4553\:$kh!rg-dg}(ddbr$Aua}_vp\tkruWniTtb|?017\V`urd};8>6[?/fpe*w`(ojr%oaew/LzlvZquWyd~Ril_ymq4561W[oxyaz>339V4*aun'xm#jmw.bnh|*Kg{U|~R~ats]dgZ~hz9:;;R\jstnw564<]9%l~k }f.e`|+ekcq%Ftb|Pws]sjqtXojUsc>?09]Qavsk|88:7X> gsd-vc)`kq$h`fv re]sjqtXj`d7<3<>;T2,cw`)zo%lou lljz,vaYwf}xTnd`31?02?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl?6;463\:$kh!rg-dg}(ddbr$~iQnup\flh;;78:7X> gsd-vc)`kq$h`fv re]sjqtXj`d783<>;T2,cw`)zo%lou lljz,vaYwf}xTnd`35?02?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl?2;463\:$kh!rg-dg}(ddbr$~iQnup\flh;?78:7X> gsd-vc)`kq$h`fv re]sjqtXj`d743<>;T2,cw`)zo%lou lljz,vaYwf}xTnd`39?03?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\476<]9%l~k }f.e`|+ekcq%yhR~ats]amkY6:91^<"i}f/pe+be&jf`t"|k_qlwvZdnfV89<6[?/fpe*w`(ojr%oaew/sf\tkruWkceS><?;T2,cw`)zo%lou lljz,vaYwf}xTnd`P4328Q5)`zo$yj"ilx/aoo})ulVzexQmio]665=R8&myj#|i/fa{*fjlp&xoS}`{r^`jjZ0582_;#j|i.sd,cf~)keas#jPpovq[goiW>8;7X> gsd-vc)`kq$h`fv re]sjqtXj`dT4?>4U1-dvc(un&mht#mcky-q`Zvi|{UiecQ6279V4*aun'xm#jmw.bnh|*tcWyd~Rlfn^zlv5678;=0Y=!hrg,qb*adp'iggu!}d^rmpwYeagUsc>?01312>S7'nxm"h gbz-gim'{nT|cz}_ckm[}iu89::>:5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbRv`r12354413\:$kh!rg-dg}(ddbr$~iQnup\flhXpfx;<=<=7:W3+bta&{l$knv!cmi{+wbXxg~ySoga_ymq45659;<0Y=!hrg,qb*adp'iggu!}d^rmpwYeagUsc>?0204?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\|jt78999>;5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbRv`r123071<]9%l~k }f.e`|+ekcq%yhR~ats]amkYg{:;<9?=6:W3+bta&{l$knv!cmi{+wbXxg~ySoga_ymq4562:>1^<"i}f/pe+be&jf`t"|k_qlwvZdnfVrd~=>?5005?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\|jt789<946[?/fpe*w`(ojr%oaew/sf\tkruWkceSua}012554403\:$kh!rg-dg}(ddbr$~iQnup\flhXpfx;<=8=2c9V4*aun'xm#jmw.bnh|*tcWyd~Rlfn^zlv567>Vhoh=<9;T2,cw`)zo%lou lljz,vaYwf}xTnd`Pxnp34515?2_;#j|i.sd,cf~)keas#jPpovq[goiWqey<=>81348Q5)`zo$yj"ilx/aoo})ulVzexQmio]{kw67818<7X> gsd-vc)`kq$h`fv re]sjqtXj`dTtb|?01:265=R8&myj#|i/fa{*fjlp&xoS}`{r^e`858582_;#j|i.sd,cf~)keas#jPpovq[be;978;7X> gsd-vc)`kq$h`fv re]sjqtXoj692?>4U1-dvc(un&mht#mcky-q`Zvi|{Ulo1=1219V4*aun'xm#jmw.bnh|*tcWyd~Ril<5<14>S7'nxm"h gbz-gim'{nT|cz}_fa?1;473\:$kh!rg-dg}(ddbr$~iQnup\cf:16;:0Y=!hrg,qb*adp'iggu!}d^rmpwY`k5=5>=5Z0.eqb+ta'nis"nbdx.pg[uhszVmh050=0:W3+bta&{l$knv!cmi{+wbXxg~ySjm39?3e?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb]35c=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[47a3\:$kh!rg-dg}(ddbr$~iQnup\cfY59o1^<"i}f/pe+be&jf`t"|k_qlwvZadW:;m7X> gsd-vc)`kq$h`fv re]sjqtXojU?=k5Z0.eqb+ta'nis"nbdx.pg[uhszVmhS8?i;T2,cw`)zo%lou lljz,vaYwf}xTknQ91g9V4*aun'xm#jmw.bnh|*tcWyd~Ril_63e?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb];5c=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[<413\:$kh!rg-dg}(ddbr$~iQnup\cfYf{{ol0=0=6:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfc979:?1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyij2=>348Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`a;;78=7X> gsd-vc)`kq$h`fv re]sjqtXojUjkh<5<12>S7'nxm"h gbz-gim'{nT|cz}_fa\evtbo5?5>;5Z0.eqb+ta'nis"nbdx.pg[uhszVmhSl}}ef>5:70<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlm7;3<9;T2,cw`)zo%lou lljz,vaYwf}xTknQnssgd8=85>2_;#j|i.sd,cf~)keas#jPpovq[beXizxnk171249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY7:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ>249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY5:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ<249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY3:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ:249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY1:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ8249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY?:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ6289V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc95:5>45Z0.eqb+ta'nis"nbdx.pg[uhszVmhSl}}ef]g5979:01^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQk1=0=6<=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=1=1289V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc95>5>45Z0.eqb+ta'nis"nbdx.pg[uhszVmhSl}}ef]g5939:01^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQk1=4=6<=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=191289V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc9525>45Z0.eqb+ta'nis"nbdx.pg[uhszVmhSl}}ef]g59?9:11^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQk1^21<>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboVn:S<<7;T2,cw`)zo%lou lljz,vaYwf}xTknQnssgd[a7X:;20Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiPd0]06==R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=R:=8:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb6W<837X> gsd-vc)`kq$h`fv re]sjqtXojUjkh_e3\27><]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<Q8299V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc9V2946[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^f2[<423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<=<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2344423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<?<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2346423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<9<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2340423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<;<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2342423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<5<>;T2,cw`)zo%lou lljz,swYwf}xTnd`30?02?P6(o{l%~k!hcy,`hn~({U{by|Pbhl?5;463\:$kh!rg-dg}(ddbr${Qnup\flh;:78:7X> gsd-vc)`kq$h`fv ws]sjqtXj`d7?3<>;T2,cw`)zo%lou lljz,swYwf}xTnd`34?02?P6(o{l%~k!hcy,`hn~({U{by|Pbhl?1;463\:$kh!rg-dg}(ddbr${Qnup\flh;>78:7X> gsd-vc)`kq$h`fv ws]sjqtXj`d7;3<>;T2,cw`)zo%lou lljz,swYwf}xTnd`38?02?P6(o{l%~k!hcy,`hn~({U{by|Pbhl?=;473\:$kh!rg-dg}(ddbr${Qnup\flhX8;:0Y=!hrg,qb*adp'iggu!xr^rmpwYeagU:>=5Z0.eqb+ta'nis"nbdx.uq[uhszVhbbR<=0:W3+bta&{l$knv!cmi{+rtXxg~ySoga_203?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\076<]9%l~k }f.e`|+ekcq%|~R~ats]amkY2:91^<"i}f/pe+be&jf`t"y}_qlwvZdnfV<9<6[?/fpe*w`(ojr%oaew/vp\tkruWkceS:<?;T2,cw`)zo%lou lljz,swYwf}xTnd`P8328Q5)`zo$yj"ilx/aoo})pzVzexQmio]:63=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ~hz9:;<?94U1-dvc(un&mht#mcky-tvZvi|{UiecQwos234575>2_;#j|i.sd,cf~)keas#z|Ppovq[goiWqey<=>>269V4*aun'xm#jmw.bnh|*quWyd~Rlfn^zlv567988=7X> gsd-vc)`kq$h`fv ws]sjqtXj`dTtb|?01013>S7'nxm"h gbz-gim'~xT|cz}_ckm[}iu89:9=?84U1-dvc(un&mht#mcky-tvZvi|{UiecQwos2346403\:$kh!rg-dg}(ddbr${Qnup\flhXpfx;<===279V4*aun'xm#jmw.bnh|*quWyd~Rlfn^zlv567<;=0Y=!hrg,qb*adp'iggu!xr^rmpwYeagUsc>?05312>S7'nxm"h gbz-gim'~xT|cz}_ckm[}iu89:>>:5Z0.eqb+ta'nis"nbdx.uq[uhszVhbbRv`r12314413\:$kh!rg-dg}(ddbr${Qnup\flhXpfx;<=8=8:W3+bta&{l$knv!cmi{+rtXxg~ySoga_ymq4561988<7X> gsd-vc)`kq$h`fv ws]sjqtXj`dTtb|?01416g=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ~hz9:;:Rlkd105?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\|jt789=9;6[?/fpe*w`(ojr%oaew/vp\tkruWkceSua}0124570<]9%l~k }f.e`|+ekcq%|~R~ats]amkYg{:;<5<8;T2,cw`)zo%lou lljz,swYwf}xTnd`Pxnp345>6:91^<"i}f/pe+be&jf`t"y}_qlwvZad4949<6[?/fpe*w`(ojr%oaew/vp\tkruWni7=3<?;T2,cw`)zo%lou lljz,swYwf}xTkn2=>328Q5)`zo$yj"ilx/aoo})pzVzexQhc=1=65=R8&myj#|i/fa{*fjlp&}yS}`{r^e`818582_;#j|i.sd,cf~)keas#z|Ppovq[be;=78;7X> gsd-vc)`kq$h`fv ws]sjqtXoj6=2?>4U1-dvc(un&mht#mcky-tvZvi|{Ulo191219V4*aun'xm#jmw.bnh|*quWyd~Ril<9<14>S7'nxm"h gbz-gim'~xT|cz}_fa?=;7a3\:$kh!rg-dg}(ddbr${Qnup\cfY79o1^<"i}f/pe+be&jf`t"y}_qlwvZadW8;m7X> gsd-vc)`kq$h`fv ws]sjqtXojU9=k5Z0.eqb+ta'nis"nbdx.uq[uhszVmhS>?i;T2,cw`)zo%lou lljz,swYwf}xTknQ;1g9V4*aun'xm#jmw.bnh|*quWyd~Ril_43e?P6(o{l%~k!hcy,`hn~({U{by|Pgb]55c=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[27a3\:$kh!rg-dg}(ddbr${Qnup\cfY?9o1^<"i}f/pe+be&jf`t"y}_qlwvZadW08=7X> gsd-vc)`kq$h`fv ws]sjqtXojUjkh<1<12>S7'nxm"h gbz-gim'~xT|cz}_fa\evtbo5;5>;5Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef>1:70<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlm7?3<9;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd8185>2_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnk1;1279V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqab:16;<0Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hi37?05?P6(o{l%~k!hcy,`hn~({U{by|Pgb]bwwc`4149:6[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg=;=60=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU;>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]260=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU9>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]060=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU?>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]660=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU=>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]460=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU3>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]:6<=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=1>1289V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc95;5>45Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g5949:01^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1=1=6<=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=1:1289V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc95?5>45Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g5909:01^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1=5=6<=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=161289V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc9535>55Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g5Z6502_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnkRj>_00;?P6(o{l%~k!hcy,`hn~({U{by|Pgb]bwwc`Wm;T>?64U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\`4Y4:11^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1^61<>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboVn:S8<7;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[a7X>;20Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hiPd0]46==R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=R6=8:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfcZb6W08>7X> gsd-vc)`kq$h`fv ws]sjqtXojUsc>?0106?P6(o{l%~k!hcy,`hn~({U{by|Pgb]{kw67888>7X> gsd-vc)`kq$h`fv ws]sjqtXojUsc>?0306?P6(o{l%~k!hcy,`hn~({U{by|Pgb]{kw678:8>7X> gsd-vc)`kq$h`fv ws]sjqtXojUsc>?0506?P6(o{l%~k!hcy,`hn~({U{by|Pgb]{kw678<8>7X> gsd-vc)`kq$h`fv ws]sjqtXojUsc>?0706?P6(o{l%~k!hcy,`hn~({U{by|Pgb]{kw678>8>7X> gsd-vc)`kq$h`fv ws]sjqtXojUsc>?091;?P6(o{l%~k!hl1,q`*au9'myhn<!rea,IdbcW{nThnQf_`fgwpd789::<>64U1-dvc(un&mg<#|k/fp2*btck;$yhn!Baef\vaYckVcTmij|uc234575;11^<"i}f/pe+bj7&{n$k?!gsf`6+tck&GjhiQ}d^f`[lYflmy~n=>?0060<>S7'nxm"h gm2-va)`z8$l~im=.sf`+HgclVxoSimPi^cg`vse89:;=;=8;T2,cw`)zo%l`= }d.eq5+aulj8%~im M`fg[wbXljUbSljkst`34565;>1^<"i}f/pe+bj7&{n$k?!gsf`6+tck&GjhiQ}d^f`[lYflmy~n=>?0514?P6(o{l%~k!hl1,q`*au9'myhn<!rea,IdbcW{nThnQf_`fgwpd789:=?:5Z0.eqb+ta'nf;"j gs3-cwbd:'xoo"Cnde]q`ZbdW`Ujhi}zb1234=5d3\:$kh!rg-dh5(ul&my=#i}db0-vae(EhnoSjPdb]j[dbc{|h;<=>Pcx>2:6><]9%l~k }f.eo4+tc'nx:"j|kc3,q`f)J{|hThdhi_vp\vaYseyUhu1>1399V4*aun'xm#jb?.sf,cw7)o{nh>#|kc.OpqgYcaolT{Q}d^vntZe~484846[?/fpe*w`(oe:%~i!hr0,dvae5&{nh#@}zb^fjbcYpzVxoSyc_b{?6;5?3\:$kh!rg-dh5(ul&my=#i}db0-vae(EziSigif^uq[wbX|dzTot2<>2:8Q5)`zo$yj"ic0/pg+bt6&nxoo? }db-NwpdXl`lmSz|Pre]wiuYdq5>5?55Z0.eqb+ta'nf;"j gs3-cwbd:'xoo"C|uc]gmc`X{UyhRzbp^az808402_;#j|i.sd,ci6)zm%l~< hrea1*wbd'Dy~nRjffg]tvZtcW}g{Snw36?1;?P6(o{l%~k!hl1,q`*au9'myhn<!rea,IvseWmcmjRy}_sf\phvXkp6<2>64U1-dvc(un&mg<#|k/fp2*btck;$yhn!Bst`\`l`aW~xT~iQ{mq]`}9>9;01^<"i}f/pe+bj7&{n$k?!gsf`6+tck&GxyoQkigd\swYulV~f|Rbzt=2=7<=R8&myj#|i/fn3*wb(o{;%kjl2/pgg*Kt}kUoekhPws]q`ZrjxVf~x1?1389V4*aun'xm#jb?.sf,cw7)o{nh>#|kc.OpqgYcaolT{Q}d^vntZjr|585?45Z0.eqb+ta'nf;"j gs3-cwbd:'xoo"C|uc]gmc`X{UyhRzbp^nvp959;01^<"i}f/pe+bj7&{n$k?!gsf`6+tck&GxyoQkigd\swYulV~f|Rbzt=6=7<=R8&myj#|i/fn3*wb(o{;%kjl2/pgg*Kt}kUoekhPws]q`ZrjxVf~x1;1389V4*aun'xm#jb?.sf,cw7)o{nh>#|kc.OpqgYcaolT{Q}d^vntZjr|5<5?45Z0.eqb+ta'nf;"j gs3-cwbd:'xoo"C|uc]gmc`X{UyhRzbp^nvp919;01^<"i}f/pe+bj7&{n$k?!gsf`6+tck&GxyoQkigd\swYulV~f|Rbzt=:=7<=R8&myj#|i/fn3*wb(o{;%kjl2/pgg*Kt}kUoekhPws]q`ZrjxVf~x171389V4*aun'xm#jb?.sf,cw7)o{nh>#|kc.OpqgYcaolT{Q}d^vntZ~hz5:5?45Z0.eqb+ta'nf;"j gs3-cwbd:'xoo"C|uc]gmc`X{UyhRzbp^zlv979;01^<"i}f/pe+bj7&{n$k?!gsf`6+tck&GxyoQkigd\swYulV~f|Rv`r=0=7<=R8&myj#|i/fn3*wb(o{;%kjl2/pgg*Kt}kUoekhPws]q`ZrjxVrd~1=1389V4*aun'xm#jb?.sf,cw7)o{nh>#|kc.OpqgYcaolT{Q}d^vntZ~hz5>5?45Z0.eqb+ta'nf;"j gs3-cwbd:'xoo"C|uc]gmc`X{UyhRzbp^zlv939;01^<"i}f/pe+bj7&{n$k?!gsf`6+tck&GxyoQkigd\swYulV~f|Rv`r=4=7<=R8&myj#|i/fn3*wb(o{;%kjl2/pgg*Kt}kUoekhPws]q`ZrjxVrd~191389V4*aun'xm#jb?.sf,cw7)o{nh>#|kc.OpqgYcaolT{Q}d^vntZ~hz525?45Z0.eqb+ta'nf;"j gs3-cwbd:'xoo"C|uc]gmc`X{UyhRzbp^zlv9?9;91^<"i}f/pe+bj7&{n$k?!gsf`6+tck&nbjkQxr^pg[qkw494946[?/fpe*w`(oe:%~i!hr0,dvae5&{nh#jPdb]j[54?3\:$kh!rg-dh5(ul&my=#i}db0-vae(zmUooRgP13;8Q5)`zo$yj"ic0/pg+bt6&nxoo? }db-q`ZbdW`U:<?64U1-dvc(un&mg<#|k/fp2*btck;$yhn!}d^f`[lY5:11^<"i}f/pe+bj7&{n$k?!gsf`6+tck&xoSimPi^11<>S7'nxm"h gm2-va)`z8$l~im=.sf`+wbXljUbS9<7;T2,cw`)zo%l`= }d.eq5+aulj8%~im re]ggZoX=;20Y=!hrg,qb*ak8'xo#j|>.fpgg7(ulj%yhRjl_h]56==R8&myj#|i/fn3*wb(o{;%kjl2/pgg*tcWmiTeR9=8:W3+bta&{l$ka>!re-dv4(`zmi9"jl/sf\`fYnW1837X> gsd-vc)`d9$yh"i}1/eq`f4)zmi$~iQkc^k\=67<]9%l~k }f.eo4+tc'nx:"j|kc3,q`f)ulVnhSdQbuy2347:76:80Y=!hrg,qb*ak8'xo#j|>.fpgg7(ulj%yhRjl_h]nq}678;6;2<==;T2,cw`)zo%l`= }d.eq5+aulj8%~im re]ggZoXe|r;<=<311<07>S7'nxm"h gm2-va)`z8$l~im=.sf`+wbXljUbS`{w012184699:;0Y=!hrg,qb*ak8'xo#j|>.fpgg7(ulj%yhRjl_h]nq}678;6:2><4U1-dvc(un&mg<#|k/fp2*btck;$yhn!}d^f`[lYj}q:;<?2>>012?P6(o{l%~k!hl1,q`*au9'myhn<!rea,vaYckVcTaxv?010?6;553\:$kh!rg-dh5(ul&my=#i}db0-vae(zmUooRgPmtz3454;:7;8=6[?/fpe*w`(oe:%~i!hr0,dvae5&{nh#jPdb]j[hs89:90>0<2:W3+bta&{l$ka>!re-dv4(`zmi9"jl/sf\`fYnWds<=>=<2<274=R8&myj#|i/fn3*wb(o{;%kjl2/pgg*tcWmiTeRczx1236929;;1^<"i}f/pe+bj7&{n$k?!gsf`6+tck&xoSimPi^ov|567:5>5=>:4U1-dvc(un&mg<#|k/fp2*btck;$yhn!}d^f`[lYj}q:;<?2;>0327==R8&myj#|i/fn3*wb(o{;%kjl2/pgg*tcWmiTeRczx123692998;T_Z><1:W3+bta&{l$ka>!re-dv4(`zmi9"jl/sf\`fYnWds<=>=<4<07>S7'nxm"h gm2-va)`z8$l~im=.sf`+wbXljUbS`{w012180869:80Y=!hrg,qb*ak8'xo#j|>.fpgg7(ulj%yhRjl_h]nq}678;6>2?=>;T2,cw`)zo%l`= }d.eq5+aulj8%~im re]ggZoXe|r;<=<36?16?P6(o{l%~k!hl1,q`*au9'myhn<!rea,vaYckVcTaxv?010?2;YT_99:7X> gsd-vc)`d9$yh"i}1/eq`f4)zmi$~iQkc^k\ip~78987;3=:;T2,cw`)zo%l`= }d.eq5+aulj8%~im re]ggZoXe|r;<=<37?]PS5563\:$kh!rg-dh5(ul&my=#i}db0-vae(zmUooRgPmtz3454;079>7X> gsd-vc)`d9$yh"i}1/eq`f4)zmi$~iQkc^k\ip~7898743Q\W116?P6(o{l%~k!hl1,q`*au9'myhn<!rea,vaYckVcTaxv?010?<;YT_8927X> gsd-vc)`d9$yh"i}1/eq`f4)zmi$~iQkc^k\ip~7898743Q\W0]PS5563\:$kh!rg-dh5(ul&my=#i}db0-vae(zmUooRgPmtz3454;17987X> gsd-vc)`d9$yh"i}1/eq`f4)zmi$~iQkc^k\ip~7898753<>369V4*aun'xm#jb?.sf,cw7)o{nh>#|kc.pg[aeXaVg~t=>?2=;=64YT_99<7X> gsd-vc)`d9$yh"i}1/eq`f4)zmi$~iQkc^k\ip~7898753<>_RU272=R8&myj#|i/fn3*wb(o{;%kjl2/pgg*tcWmiTeRczx12369?9;9UX[==<;T2,cw`)zo%l`= }d.eq5+aulj8%~im re]ggZoXe|r;<=<39?1276=R8&myj#|i/fn3*wb(o{;%kjl2/pgg*tcWmiTeRczx12369?9;1997X> gsd-vc)`d9$yh"i}1/eq`f4)zmi$~iQkc^k\ip~7898753:<3:W3+bta&{l$ka>!re-dv4(`zmi9"jl/sf\`fYnWds<=>=<8<7561<]9%l~k }f.eo4+tc'nx:"j|kc3,q`f)ulVnhSdQbuy2347:>6=;T_Z>=a:W3+bta&{l$ka>!re-dv4(un~l#_OB_SF\AKYA_O^:>45Z0.eqb+ta'nf;"j gs3-vcqa|&XJAR\JGNWW[@H6:k1^<"i}f/pe+bj7&{n$k?!rguep*TFEV\J@DJPFVDW54543\:$kh!rg-dh5(ul&my=#|iwgv,gptuWo}mxR}{aug\BVKXNOn:?;5Z0.eqb+ta'nf;"j gs3-vcqa|&i~~Qiwgv\wqgsmVLXARHId0/Jj6><]9%l~k }f.eo4+tc'nx:"hxfu-`qwtXn~lS~zntd]EWHYANm;&Ec?>329V4*aun'xm#jb?.sf,cw7)zo}mx"mzrs]escrX{}kiRH\M^DE`7513\:$kh!rg-dh5(ul&my=#|iwgv,gptuWo}mxR}{aug\BVKXNOn9!D`<8:W3+bta&{l$ka>!re-dv4(un~l#n{}r^dtbqYt|h~nSK]B_GDg6(Oi98837X> gsd-vc)`d9$yh"i}1/pescr(mdzuRhxfu]ef71<]9%l~k }f.eo4+tc'nx:"hxfu-fiur~Wo}mxRg=e:W3+bta&{l$ka>!re-dv4(un~l#hctx]escrXaVey<=>?2g9V4*aun'xm#jb?.sf,cw7)zo}mx"kbpu{\br`sW`Ud~=>?0006?P6(o{l%~k!hl1,q`*au9'xm{kz urgq[sgkam827X> gsd-vc)`d9$yh"i}ar,qwqu(k9%hm|vndv?4;4>3\:$kh!rg-dh5(ul&mym~ }suq,g5)di{xrbhz31?0:?P6(o{l%~k!hl1,q`*auiz$yy} c1-`ewt~fl~7>3<6;T2,cw`)zo%l`= }d.eqev(u{}y$o=!laspzj`r;;78m7X> gsd-vc)`d9$yh"i}ar,qwqu(k9%laxv!glY3Y+aj9'g:>k5Z0.eqb+ta'nf;"j gscp*wus{&i;#jczx/en_4[)ody%a~<i;T2,cw`)zo%l`= }d.eqev(u{}y$o=!hmtz-ch]5U'mf#c|2g9V4*aun'xm#jb?.sf,cwgt&{y"m?/fov|+ajS:W%k`}!mr0e?P6(o{l%~k!hl1,q`*auiz$yy} c1-dip~)odQ?Q#ibs/op66=R8&myj#|i/fn3*wb(o{kx"}{s.a3+s7;87887X> gsd-vc)`d9$yh"i}ar,qwqu(k9%}=1?1229V4*aun'xm#jb?.sf,cwgt&{y"m?/w3?6;443\:$kh!rg-dh5(ul&mym~ }suq,g5)q9595>>5Z0.eqb+ta'nf;"j gscp*wus{&i;#{?34?0a?P6(o{l%~k!hl1,q`*auiz$yy} c1-u5Z6Xign;<=>>2c9V4*aun'xm#jb?.sf,cwgt&{y"m?/w3\5Zgil9:;<<<m;T2,cw`)zo%l`= }d.eqev(u{}y$o=!y1^0\ekb789::>o5Z0.eqb+ta'nf;"j gscp*wus{&i;#{?P3^cm`567888i7X> gsd-vc)`d9$yh"i}ar,qwqu(k9%}=R:Paof34566:01^<"i}f/pe+bj7&{n$ko|.sqww*e6'jky~t`jt=2=6<=R8&myj#|i/fn3*wb(o{kx"}{s.a2+fguzpdnx1?1289V4*aun'xm#jb?.sf,cwgt&{y"m>/bcqv|hb|585>45Z0.eqb+ta'nf;"j gscp*wus{&i:#no}rxlfp959:o1^<"i}f/pe+bj7&{n$ko|.sqww*e6'ng~t#ib[1_-ch7)e88m7X> gsd-vc)`d9$yh"i}ar,qwqu(k8%laxv!glY2Y+aj{'gx>k5Z0.eqb+ta'nf;"j gscp*wus{&i:#jczx/en_7[)ody%a~<i;T2,cw`)zo%l`= }d.eqev(u{}y$o<!hmtz-ch]4U'mf#c|2g9V4*aun'xm#jb?.sf,cwgt&{y"m>/fov|+ajS=W%k`}!mr00?P6(o{l%~k!hl1,q`*auiz$yy} c0-u5969::1^<"i}f/pe+bj7&{n$ko|.sqww*e6';7=3<<;T2,cw`)zo%l`= }d.eqev(u{}y$o<!y1=0=66=R8&myj#|i/fn3*wb(o{kx"}{s.a2+s7;;7887X> gsd-vc)`d9$yh"i}ar,qwqu(k8%}=1:12c9V4*aun'xm#jb?.sf,cwgt&{y"m>/w3\4Zgil9:;<<<m;T2,cw`)zo%l`= }d.eqev(u{}y$o<!y1^3\ekb789::>o5Z0.eqb+ta'nf;"j gscp*wus{&i:#{?P2^cm`567888i7X> gsd-vc)`d9$yh"i}ar,qwqu(k8%}=R=Paof34566:k1^<"i}f/pe+bj7&{n$ko|.sqww*e6';T8Road12344473\:$kh!rg-dh5(ul&mym~ }suq,gjkw8;:0Y=!hrg,qb*ak8'xo#j|ns/pppv)dgdz:>45Z0.eqb+ta'nf;"j gscp*wus{&xjaRkbpu{\bgYn;91^<"i}f/pe+bj7&{n$ko|.sqww*tfeVof|ywPfc]j[jt789:8=6[?/fpe*w`(oe:%~i!hr`q-vvrt'{kfShctx]efZoXg{:;<=?>f:W3+bta&{l$ka>!re-qehYqiecoSkyit318Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkr5<2_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfex<<;;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw672<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~8>95Z0.eqb+ta'nf;"j rqlwv*Kdg|dSnaznu610>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|<8?7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{6368Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkr0:=1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~by6=4:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmp<4>3\:$kh!rg-dh5(ul&x{by| MbmvjqYdg|dSnw30?0`?P6(o{l%~k!hl1,q`*twf}x$Anaznu]`kphsWjs7<3Q}t3;8Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkrXkp6:2?m4U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\g|:66Vx>45Z0.eqb+ta'nf;"j rqlwv*Kdg|dSnaznu]`}949:j1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQly=0=[wr512_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfexRmv<2<1g>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vir0>0Pru0:?P6(o{l%~k!hl1,q`*twf}x$Anaznu]`kphsWjs783<l;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[f;<7Uyx?74U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\g|:26;i0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPcx>6:Zts:01^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQly=4=6f=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Uhu181_sv1=>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vir0:0=c:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmpZe~4>4T~y<6;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[f;078h7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_b{?<;Yu|;k0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPxnp?4;4f3\:$kh!rg-dh5(ul&x{by| MbmvjqYdg|dSua}<0<1e>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vrd~1<12`9V4*aun'xm#jb?.sf,vuhsz&Ghcx`{_bmvjqYg{682?o4U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\|jt;<78j7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_ymq8085i2_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfexRv`r=4=6d=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Usc28>3c8Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkrXpfx743<n;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[}iu4049h6[?/fpe*w`(oe:%~i!}povq+Heh}g~Tob{at^zlv9?9W{~:j6[?/fpe*w`(oe:%~i!}povq+firf}6;2<h4U1-dvc(un&mg<#|k/srmpw)dg|d0<0>f:W3+bta&{l$ka>!re-qtkru'je~by2=>0d8Q5)`zo$yj"ic0/pg+wvi|{%hcx`{<2<2b>S7'nxm"h gm2-va)uxg~y#naznu>7:4`<]9%l~k }f.eo4+tc'{zex!lotlw8086n2_;#j|i.sd,ci6)zm%y|cz}/bmvjq:168l0Y=!hrg,qb*ak8'xo#~ats-`kphs4>4:j6[?/fpe*w`(oe:%~i!}povq+firf}632<h4U1-dvc(un&mg<#|k/srmpw)dg|d040>e:W3+bta&{l$ka>!re-qtkru'je~byQ?1d9V4*aun'xm#jb?.sf,vuhsz&idyczP10g8Q5)`zo$yj"ic0/pg+wvi|{%hcx`{_33f?P6(o{l%~k!hl1,q`*twf}x$ob{at^12a>S7'nxm"h gm2-va)uxg~y#naznu]75`=R8&myj#|i/fn3*wb(zyd~"m`uov\14c<]9%l~k }f.eo4+tc'{zex!lotlw[37b3\:$kh!rg-dh5(ul&x{by| cnwmpZ16m2_;#j|i.sd,ci6)zm%y|cz}/bmvjqY?9l1^<"i}f/pe+bj7&{n$~}`{r.alqkrX1;80Y=!hrg,qb*ak8'xo#~ats-`kphsWm;7<3<=;T2,cw`)zo%l`= }d.psjqt(kfexRj><0<16>S7'nxm"h gm2-va)uxg~y#naznu]g5949:;1^<"i}f/pe+bj7&{n$~}`{r.alqkrXl8682?<4U1-dvc(un&mg<#|k/srmpw)dg|dSi?34?01?P6(o{l%~k!hl1,q`*twf}x$ob{at^f28085:2_;#j|i.sd,ci6)zm%y|cz}/bmvjqYc95<5>?5Z0.eqb+ta'nf;"j rqlwv*eh}g~Th<28>308Q5)`zo$yj"ic0/pg+wvi|{%hcx`{_e3?<;453\:$kh!rg-dh5(ul&x{by| cnwmpZb64049=6[?/fpe*w`(oe:%~i!}povq+firf}Uo=R>=1:W3+bta&{l$ka>!re-qtkru'je~byQk1^315>S7'nxm"h gm2-va)uxg~y#naznu]g5Z4592_;#j|i.sd,ci6)zm%y|cz}/bmvjqYc9V99=6[?/fpe*w`(oe:%~i!}povq+firf}Uo=R:=1:W3+bta&{l$ka>!re-qtkru'je~byQk1^715>S7'nxm"h gm2-va)uxg~y#naznu]g5Z0592_;#j|i.sd,ci6)zm%y|cz}/bmvjqYc9V=9=6[?/fpe*w`(oe:%~i!}povq+firf}Uo=R6=1:W3+bta&{l$ka>!re-qtkru'je~byQk1^;1=>S7'nxm"h gm2-sw)`hy%{~z|/b3,gdtuqgo0=0=9:W3+bta&{l$ka>!ws-dsdu)z~x#n? c`pq}kcs484956[?/fpe*w`(oe:%{!hw`q-svrt'j;$ol|}yogw878512_;#j|i.sd,ci6){%l{l}!wrvp+f7(khxyuck{<2<1b>S7'nxm"h gm2-sw)`hy%{~z|/b3,chs&ngP<P hm0,n57`<]9%l~k }f.eo4+qu'n}j#y|tr-`5*aj}q$laV?R.fop*hu5n2_;#j|i.sd,ci6){%l{l}!wrvp+f7(ods"jcT2\,div(j{;l0Y=!hrg,qb*ak8'}y#jyns/uppv)d9&mfyu hmZ1^*bkt&dy9j6[?/fpe*w`(oe:%{!hw`q-svrt'j;$k`{w.foX0X(`ez$f?=4U1-dvc(un&mg<#y}/fubw+qt|z%h="x><1<17>S7'nxm"h gm2-sw)`hy%{~z|/b3,r4:66;90Y=!hrg,qb*ak8'}y#jyns/uppv)d9&|:0?0=3:W3+bta&{l$ka>!ws-dsdu)z~x#n? v0>0:75<]9%l~k }f.eo4+qu'n}j#y|tr-`5*p64=49n6[?/fpe*w`(oe:%{!hw`q-svrt'j;$z<Q?_`lg45679;h0Y=!hrg,qb*ak8'}y#jyns/uppv)d9&|:S<Qnne234575j2_;#j|i.sd,ci6){%l{l}!wrvp+f7(~8U9Sl`k012357d<]9%l~k }f.eo4+qu'n}j#y|tr-`5*p6W:Ujbi>?0131f>S7'nxm"h gm2-sw)`hy%{~z|/b3,r4Y3Whdo<=>?13;8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.abvwim}6;2?74U1-dvc(un&mg<#y}/fubw+qt|z%h>"mnrs{maq:66;30Y=!hrg,qb*ak8'}y#jyns/uppv)d:&ij~waeu>1:7?<]9%l~k }f.eo4+qu'n}j#y|tr-`6*efz{seiy2<>3d8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.enq}(`eR:V"jc>.l31b>S7'nxm"h gm2-sw)`hy%{~z|/b0,chs&ngP=P hmr,nw7`<]9%l~k }f.eo4+qu'n}j#y|tr-`6*aj}q$laV<R.fop*hu5n2_;#j|i.sd,ci6){%l{l}!wrvp+f4(ods"jcT3\,div(j{;l0Y=!hrg,qb*ak8'}y#jyns/uppv)d:&mfyu hmZ6^*bkt&dy9?6[?/fpe*w`(oe:%{!hw`q-svrt'j8$z<2?>318Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.t28485;2_;#j|i.sd,ci6){%l{l}!wrvp+f4(~8692?=4U1-dvc(un&mg<#y}/fubw+qt|z%h>"x><2<17>S7'nxm"h gm2-sw)`hy%{~z|/b0,r4:36;h0Y=!hrg,qb*ak8'}y#jyns/uppv)d:&|:S=Qnne234575j2_;#j|i.sd,ci6){%l{l}!wrvp+f4(~8U:Sl`k012357d<]9%l~k }f.eo4+qu'n}j#y|tr-`6*p6W;Ujbi>?0131f>S7'nxm"h gm2-sw)`hy%{~z|/b0,r4Y4Whdo<=>?13`8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.t2[1Yffm:;<=?=0:W3+bta&{l$ka>!ws-dsdu)z~x#nabp003?P6(o{l%~k!hl1,tv*apiz$|y} cnos67><]9%l~k }f.eo4+qu'n}j#y|tr-qehYa}efTjoQf249V4*aun'xm#jb?.vp,crgt&~y"|nm^dvhiYn:j1^<"i}f/pe+bj7&~x$kzo|.vqww*tfeVl~`aQf_np34565l2_;#j|i.sd,ci6){%l{l}!wrvp+wgjWog`RgPos234574k2_;#j|i.sd,ci6){%l{im>.vf`a}r(EhnoSz|Pd`vb[firf}UbSljk0123555d3\:$kh!rg-dh5(pz&m|hn?!weaf|q)JimnT{Qkauc\gjsi|VcTmij?012266e<]9%l~k }f.eo4+qu'n}oo< xdbg{p*KflmU|~Rjnt`]`kphsW`Ujhi>?01377f=R8&myj#|i/fn3*rt(o~nh=#ykcdzw+HgclV}ySio{a^alqkrXaVkoh=>?0040f>S7'nxm"h gm2-sw)`mi:"zjleyv,IdbcW~xThlzn_bmvjqYnWhno<=>?22`8Q5)`zo$yj"ic0/uq+bqck8$|hnkwt.Ob`aYpzVnjxlQlotlw[lYflm:;<=:<b:W3+bta&{l$ka>!ws-dsae6&~nhiuz M`fg[rtXlh~jSnaznu]j[dbc89:;:>l4U1-dvc(un&mg<#y}/fugg4(pljosx"Cnde]tvZbf|hUhcx`{_h]b`a67892?<6[?/fpe*w`(oe:%{!hwea2*rbdmq~$Aljk_vp\`drfWje~byQf_`fg4567Wjs7=3:?;T2,cw`)zo%l`= xr.et`f7)minty!Baef\swYci}kTob{at^k\eab789:Tot26>548Q5)`zo$yj"ic0/uq+bqck8$|hnkwt.Ob`aYpzVnjxlQlotlw[lYflm:;<=Qly=;=74YT_8>97X> gsd-vc)`d9$|~"ixdb3-saebp}%FmijPws]geqgXkfexRgPaef3456Xkp6229?;5:W3+bta&{l$ka>!ws-dsae6&~nhiuz M`fg[rtXlh~jSnaznu]j[dbc89:;Snw39?]a`a2312_;#j|i.sd,ci6){%l{im>.vf`a}r(EhnoSz|Pd`vb[firf}UbSljk0123[}iu484:=RGAV^277>S7'nxm"h gm2-sw)`mi:"zjleyv,IdbcW~xThlzn_bmvjqYnWhno<=>?_ymq87869=90Y=!hrg,qb*ak8'}y#jykc0,t`fc|&GjhiQxr^fbpdYdg|dSdQnde2345Yg{682<?;3:W3+bta&{l$ka>!ws-dsae6&~nhiuz M`fg[rtXlh~jSnaznu]j[dbc89:;Sua}<5<2561<]9%l~k }f.eo4+qu'n}oo< xdbg{p*Kt}kUoekhPws]q`ZrjxVir0=0<7:W3+bta&{l$ka>!ws-dsae6&~nhiuz Mrwa[aoanV}ySjPtlr\g|:66:=0Y=!hrg,qb*ak8'}y#jykc0,t`fc|&GxyoQkigd\swYulV~f|Rmv<3<03>S7'nxm"h gm2-sw)`mi:"zjleyv,IvseWmcmjRy}_sf\phvXkp682>94U1-dvc(un&mg<#y}/fugg4(pljosx"C|uc]gmc`X{UyhRzbp^az8184?2_;#j|i.sd,ci6){%l{im>.vf`a}r(EziSigif^uq[wbX|dzTot2:>258Q5)`zo$yj"ic0/uq+bqck8$|hnkwt.OpqgYcaolT{Q}d^vntZe~4?48;6[?/fpe*w`(oe:%{!hwea2*rbdmq~$A~{m_ekebZquW{nTx`~Pcx>4:61<]9%l~k }f.eo4+qu'n}oo< xdbg{p*Kt}kUoekhPws]q`ZrjxVir050<8:W3+bta&{l$ka>!ws-dsae6&~nhiuz Mrwa[aoanV}ySjPtlr\hpr;87937X> gsd-vc)`d9$|~"ixdb3-saebp}%FxlPdhde[rtXzmUa}Qcuu>2:6><]9%l~k }f.eo4+qu'n}oo< xdbg{p*Kt}kUoekhPws]q`ZrjxVf~x1<1399V4*aun'xm#jb?.vp,crbd9'}oohv{/LqvfZbnnoU|~R|k_uos[iss4:4846[?/fpe*w`(oe:%{!hwea2*rbdmq~$A~{m_ekebZquW{nTx`~Pltv?0;5?3\:$kh!rg-dh5(pz&m|hn?!weaf|q)J{|hThdhi_vp\vaYseyUgyy2:>2:8Q5)`zo$yj"ic0/uq+bqck8$|hnkwt.OpqgYcaolT{Q}d^vntZjr|5<5?55Z0.eqb+ta'nf;"z| gvf`5+qcklr#@}zb^fjbcYpzVxoSyc_mww828402_;#j|i.sd,ci6){%l{im>.vf`a}r(EziSigif^uq[wbX|dzT`xz38?1;?P6(o{l%~k!hl1,tv*aplj;%{imjxu-NwpdXl`lmSz|Pre]wiuYk}}622>64U1-dvc(un&mg<#y}/fugg4(pljosx"C|uc]gmc`X{UyhRzbp^zlv969;11^<"i}f/pe+bj7&~x$kzjl1/ugg`~s'Dy~nRjffg]tvZtcW}g{Sua}<0<0<>S7'nxm"h gm2-sw)`mi:"zjleyv,IvseWmcmjRy}_sf\phvXpfx7>3=7;T2,cw`)zo%l`= xr.et`f7)minty!Bst`\`l`aW~xT~iQ{mq]{kw:46:20Y=!hrg,qb*ak8'}y#jykc0,t`fc|&GxyoQkigd\swYulV~f|Rv`r=6=7==R8&myj#|i/fn3*rt(o~nh=#ykcdzw+HurjVnbjkQxr^pg[qkwWqey080<8:W3+bta&{l$ka>!ws-dsae6&~nhiuz Mrwa[aoanV}ySjPtlr\|jt;>7937X> gsd-vc)`d9$|~"ixdb3-saebp}%FxlPdhde[rtXzmUa}Qwos>4:6><]9%l~k }f.eo4+qu'n}oo< xdbg{p*Kt}kUoekhPws]q`ZrjxVrd~161399V4*aun'xm#jb?.vp,crbd9'}oohv{/LqvfZbnnoU|~R|k_uos[}iu4049j6[?/fpe*w`(oe:%{!hwea2*rbdmq~$hdhi_vp\vaYsey6;2?h4U1-dvc(un&mg<#y}/fugg4(pljosx"y}_ecweZeh}g~TeR>=f:W3+bta&{l$ka>!ws-dsae6&~nhiuz ws]geqgXkfexRgP1228Q5)`zo$yj"ic0/uq+bqck8$|hnkwt.uq[agsiVidyczPi^336c=R8&myj#|i/fn3*rt(o~nh=#ykcdzw+rtXlh~jSnaznu]j[74a3\:$kh!rg-dh5(pz&m|hn?!weaf|q)pzVnjxlQlotlw[lY4:o1^<"i}f/pe+bj7&~x$kzjl1/ugg`~s'~xThlzn_bmvjqYnW=8m7X> gsd-vc)`d9$|~"ixdb3-saebp}%|~Rjnt`]`kphsW`U>>k5Z0.eqb+ta'nf;"z| gvf`5+qcklr#z|Pd`vb[firf}UbS;<i;T2,cw`)zo%l`= xr.et`f7)minty!xr^fbpdYdg|dSdQ82g9V4*aun'xm#jb?.vp,crbd9'}oohv{/vp\`drfWje~byQf_90e?P6(o{l%~k!hl1,tv*aplj;%{imjxu-tvZbf|hUhcx`{_h]:7==R8&myj#|i/fn3*rt(o~nh=#ykcdzw+rtXlh~jSnaznu]j[dbc89:;0<0<8:W3+bta&{l$ka>!ws-dsae6&~nhiuz ws]geqgXkfexRgPaef3456;:7937X> gsd-vc)`d9$|~"ixdb3-saebp}%|~Rjnt`]`kphsW`Ujhi>?01>0:6><]9%l~k }f.eo4+qu'n}oo< xdbg{p*quWmkmRm`uov\mZgcl9:;<1:1399V4*aun'xm#jb?.vp,crbd9'}oohv{/vp\`drfWje~byQf_`fg45674<4856[?/fpe*w`(oe:%{!hwea2*rbdmq~${Qkauc\gjsi|VcTmij?012?1;7402_;#j|i.sd,ci6){%l{im>.vf`a}r({UomyoPcnwmpZoXimn;<=>36?1:?P6(o{l%~k!hl1,tv*aplj;%{imjxu-tvZbf|hUhcx`{_h]b`a67896=2<=7;T2,cw`)zo%l`= xr.et`f7)minty!xr^fbpdYdg|dSdQnde2345:06:30Y=!hrg,qb*ak8'}y#jykc0,t`fc|&}ySio{a^alqkrXaVkoh=>?0=5=56><]9%l~k }f.eo4+qu'n}oo< xdbg{p*quWmkmRm`uov\mZgcl9:;<161389V4*aun'xm#jb?.vp,crbd9'}oohv{/vp\`drfWje~byQf_`fg4567414:?55Z0.eqb+ta'nf;"z| gvf`5+qcklr#z|Pd`vb[firf}UbSljk01238<8382_;#j|i.sd,ci6){%l{im>.vf`a}r({UomyoPcnwmpZoXimn;<=>39?]PS5YT_9;o7X> gsd-vc)`d9$|~"|nm^uq[`hXa8887X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{259V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjq75<2_;#j|i.sd,ci6){%||cz}/LalqkrXkfex?<;;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw772<]9%l~k }f.eo4+qu'~zex!BcnwmpZeh}g~?>95Z0.eqb+ta'nf;"z| wqlwv*Kdg|dSnaznu710>S7'nxm"h gm2-sw)pxg~y#@m`uov\gjsi|?8?7X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{7368Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkr?:=1^<"i}f/pe+bj7&~x${}`{r.O`kphsWje~by7=9:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmpZe~4949o6[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^az858Xz}827X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{_b{?5;4d3\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|dSnw31?]qp7?<]9%l~k }f.eo4+qu'~zex!BcnwmpZeh}g~Tot2=>3a8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXkp692R|{289V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYdq595>n5Z0.eqb+ta'nf;"z| wqlwv*Kdg|dSnaznu]`}959W{~956[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^az8185k2_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRmv<5<\vq4>3\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|dSnw35?0`?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphsWjs793Q}t3;8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXkp6=2?m4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov\g|:16Vx>45Z0.eqb+ta'nf;"z| wqlwv*Kdg|dSnaznu]`}919:j1^<"i}f/pe+bj7&~x${}`{r.O`kphsWje~byQly=5=[wr512_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRmv<9<1g>S7'nxm"h gm2-sw)pxg~y#@m`uov\gjsi|Vir050Pru0b?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphsWqey0=0=a:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmpZ~hz5;5>l5Z0.eqb+ta'nf;"z| wqlwv*Kdg|dSnaznu]{kw:56;k0Y=!hrg,qb*ak8'}y#z~ats-Ngjsi|VidyczPxnp?7;4f3\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|dSua}<5<1e>S7'nxm"h gm2-sw)pxg~y#@m`uov\gjsi|Vrd~1;12`9V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYg{6=2?o4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov\|jt;?78j7X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{_ymq8=85i2_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRv`r=;=6a=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}Usc26>^pw5c=R8&myj#|i/fn3*rt(yd~"m`uov?4;7a3\:$kh!rg-dh5(pz&}{by| cnwmp9799o1^<"i}f/pe+bj7&~x${}`{r.alqkr;:7;m7X> gsd-vc)`d9$|~"ynup,gjsi|595=k5Z0.eqb+ta'nf;"z| wqlwv*eh}g~783?i;T2,cw`)zo%l`= xr.usjqt(kfex1;11g9V4*aun'xm#jb?.vp,suhsz&idycz36?3e?P6(o{l%~k!hl1,tv*qwf}x$ob{at=5=5c=R8&myj#|i/fn3*rt(yd~"m`uov?<;7a3\:$kh!rg-dh5(pz&}{by| cnwmp9?99l1^<"i}f/pe+bj7&~x${}`{r.alqkrX88o0Y=!hrg,qb*ak8'}y#z~ats-`kphsW8;n7X> gsd-vc)`d9$|~"ynup,gjsi|V8:i6[?/fpe*w`(oe:%{!xpovq+firf}U8=h5Z0.eqb+ta'nf;"z| wqlwv*eh}g~T8<k4U1-dvc(un&mg<#y}/vrmpw)dg|dS8?j;T2,cw`)zo%l`= xr.usjqt(kfexR8>e:W3+bta&{l$ka>!ws-ttkru'je~byQ81d9V4*aun'xm#jb?.vp,suhsz&idyczP80g8Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_801?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f28585:2_;#j|i.sd,ci6){%||cz}/bmvjqYc95;5>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th<2=>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e3?7;453\:$kh!rg-dh5(pz&}{by| cnwmpZb64=49>6[?/fpe*w`(oe:%{!xpovq+firf}Uo=1;1239V4*aun'xm#jb?.vp,suhsz&idyczPd0>5:74<]9%l~k }f.eo4+qu'~zex!lotlw[a7;?7897X> gsd-vc)`d9$|~"ynup,gjsi|Vn:050=2:W3+bta&{l$ka>!ws-ttkru'je~byQk1=;=64=R8&myj#|i/fn3*rt(yd~"m`uov\`4Y7:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl8U:><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th<Q=209V4*aun'xm#jb?.vp,suhsz&idyczPd0]064=R8&myj#|i/fn3*rt(yd~"m`uov\`4Y3:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl8U>><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th<Q9209V4*aun'xm#jb?.vp,suhsz&idyczPd0]464=R8&myj#|i/fn3*rt(yd~"m`uov\`4Y?:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl8U2>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th?2?>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e0?5;453\:$kh!rg-dh5(pz&}{by| cnwmpZb54;49>6[?/fpe*w`(oe:%{!xpovq+firf}Uo>1=1239V4*aun'xm#jb?.vp,suhsz&idyczPd3>7:74<]9%l~k }f.eo4+qu'~zex!lotlw[a4;=7897X> gsd-vc)`d9$|~"ynup,gjsi|Vn90;0=2:W3+bta&{l$ka>!ws-ttkru'je~byQk2=5=67=R8&myj#|i/fn3*rt(yd~"m`uov\`7:?6;80Y=!hrg,qb*ak8'}y#z~ats-`kphsWm8753<>;T2,cw`)zo%l`= xr.usjqt(kfexRj=_102?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f1[4463\:$kh!rg-dh5(pz&}{by| cnwmpZb5W;8:7X> gsd-vc)`d9$|~"ynup,gjsi|Vn9S><>;T2,cw`)zo%l`= xr.usjqt(kfexRj=_502?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f1[0463\:$kh!rg-dh5(pz&}{by| cnwmpZb5W?8:7X> gsd-vc)`d9$|~"ynup,gjsi|Vn9S:<>;T2,cw`)zo%l`= xr.usjqt(kfexRj=_902?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f1[<713\:$kh!rg-nah)cg|~TeR>>6:W3+bta&{l$ahc dnww[lY69>1^<"i}f/pe+hcj'me~xRgP1134?P6(o{l%~k!bel-gkprXaV;:=:5Z0.eqb+ta'dof#iazt^k\57703\:$kh!rg-nah)cg|~TeR?<169V4*aun'xm#`kb/emvpZoX9=;<7X> gsd-vc)jmd%ocxzPi^3652=R8&myj#|i/lgn+air|VcT=;?8;T2,cw`)zo%fi`!kotv\mZ709?1^<"i}f/pe+hcj'me~xRgP2048Q5)`zo$yj"cjm.flqqYnW:;=7X> gsd-vc)jmd%ocxzPi^622>S7'nxm"h mdo,`jssW`U>=;5Z0.eqb+ta'dof#iazt^k\240<]9%l~k }f.ofi*bh}}UbS:?9;T2,cw`)zo%fi`!kotv\mZ>6>2_;#j|i.sd,i`k(lfSdQ6189V4*aun'xm#`kb/emvpZkbe5:5=l5Z0.eqb+ta'dof#iazt^ofi97768k0Y=!hrg,qb*kbe&ndyyQbel>25;7f3\:$kh!rg-nah)cg|~Tahc313<2e>S7'nxm"h mdo,`jssWdof0<=11`9V4*aun'xm#`kb/emvpZkbe5;?2<o4U1-dvc(un&gna"j`uu]nah:6=7;j7X> gsd-vc)jmd%ocxzPmdo?5386i2_;#j|i.sd,i`k(lfS`kb<05=5<=R8&myj#|i/lgn+air|Vgna1?1189V4*aun'xm#`kb/emvpZkbe585=45Z0.eqb+ta'dof#iazt^ofi959901^<"i}f/pe+hcj'me~xRcjm=6=5<=R8&myj#|i/lgn+air|Vgna1;1189V4*aun'xm#`kb/emvpZkbe5<5=45Z0.eqb+ta'dof#iazt^ofi919901^<"i}f/pe+hcj'me~xRcjm=:=5<=R8&myj#|i/lgn+air|Vgna1716d9V4*aun'xm#`kb/f`n*bdjo'miajo!nfg`g+djo&hggRcjm^efj`tf|fx$zlbfd/appw)uidfdc}U?]/pbi+t(~;Uecd`ft/pbi*bw91r:4#|nm0`8Q5)`zo$yj"cjm.vntZtfeVxoSh`>c:W3+bta&{l$ahc tlr\vdkXzmUnb<?<;T2,cw`)zo%ym`Q}d^gm52=R8&myj#|i/scn[wc`g|~Tic?<;T2,cw`)zo%ym`Qxr^gm5a=R8&myj#|i/sqwfim(zmUyyQnssgd65=R8&myj#|i/sqwfim(zmUyyQnssgd[a7582_;#j|i.sd,vvredb%yhR||t^cpv`aXl;;h7X> gsd-vc)u{}hgg"|k_sqw[fijj8n0Y=!hrg,qb*tt|kf`#jPrrv\gjke98o0Y=!hrg,qb*tt|kf`#jPrrv\v`a;87;n7X> gsd-vc)u{}hgg"|k_sqw[wc`484:i6[?/fpe*w`(zz~i`f!}d^pppZtbo585=i5Z0.eqb+ta'{ynae re]qwqYumnU;=i5Z0.eqb+ta'{ynae re]qwqYumnU:=i5Z0.eqb+ta'{ynae re]qwqYumnU9=i5Z0.eqb+ta'{ynae ws]qwqYf{{ol>=5Z0.eqb+ta'{ynae ws]qwqYf{{olSi?=0:W3+bta&{l$~~zmlj-tvZtt|Vkx~hiPd33`?P6(o{l%~k!}su`oo*quW{ySnabb0f8Q5)`zo$yj"||tcnh+rtXzz~Tobcm10g8Q5)`zo$yj"||tcnh+rtXzz~T~hi30?3f?P6(o{l%~k!}su`oo*quW{ySkh<0<2`>S7'nxm"h rrvahn)pzVxxxR|jg^22`>S7'nxm"h rrvahn)pzVxxxR|jg^3b?PUBZVKGEL]l;TQFVZPN[@HGI>5YCB;8RLCPW]S[I>5XE@18S@De3^XBXHQIISQWg>QUA]OTABJJ_@a8SWOSMVGDHHQM1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF5:ZLVF_13QY_@DL8;YQW[BHC?2RXXRXLCc9[[FIUMVCEJB84Xe`\Ma`<PmbT\gbVdppmjh682RoaRCnjnpUawungg;;7Ujb_LkmkwPbzzcdbn5nllmppZcjx}si7lbborv\bpjk>2hjof{d:`bgnswWdkygh|<;bnh`>bf|hUhcx`{(1+g?agsiVidycz'1(g8`drfWje~by&>0(f8`drfWje~by&=)e9geqgXkfex%=&d:fbpdYdg|d$9'k;ecweZeh}g~#9$j4d`vb[firf}"=%i5kauc\gjsi|!="h6jnt`]`kphs 1#o7io{a^alqkr/1 n0hlzn_bmvjq:768:0hlzn_bmvjq:683:5;6jmiugqv3=cag";%;5kio*2-2=cag":<$94dhl+54/03mce$<<&7:fjj-74!>1oec&>4(58`lh/9<#<7iga(04*3>bnf!;<%;5kio*1-3=cag"8%;5kio*7-3=cag">%;5kio*5-3=cag"<%;5kio*;-3=cag"2%;5kio>3:2=cag6:<394dhl?54803mce0<<17:fjj9746>1oec2>4?58`lh;9<4<7iga<04==>bnf5;<6=08;ekm8419>2nbb1?16:fjj949>2nbb1=16:fjj929>2nbb1;16:fjj909>2nbb1916:fjj9>9>2nbb1717:flqq.7!>1ocxz'1(:8`jss 8:"46j`uu*25,><lf$<<&8:flqq.6; 20hb{{(06*<>bh}}":9$64dnww,40.02ndyy&>7(58`jss ;#<7iazt)1*3>bh}}"?%:5kotv+1,1<lf$;'8;emvp-1.?2ndyy&7)69gkpr/1 =0hb{{<1<;?air|5;;255kotv?548?3me~x1?=>99gkpr;9:437iazt=37:==cg|~7=807;emvp9716h1ocxz31683:==cg|~7=:08;emvp979?2ndyy2=>69gkpr;;7=0hb{{<5<4?air|5?5;6j`uu>5:2=cg|~7;394dnww8=803me~x1718:ggmc4iom?0i`~{y208bl`hWnoeio{os]u0Z5+(Qcgecv/CNPF$Bcim{kc.>0/3-46733ocmcRvcny]2O}7?W;igg><4fhdl[}jipV;@t<6P2bnh(coagVmnbh|ntnp\r1Y4$GEEI!@@ND1`=>`nnfUs`cvP1Jz2<Z4ddb&mekaPgdlfvdrhzV|?S>"tc^jbwZoi|Vigg0>#c^jbwZuu{}7; nQ}d^dqat;6$jUcm~Q}d^fbpdYdg|d1<"l_ekm[roc|a7:4!mPh`q\swYci}kTob{at<3/gZ`rdeUm`li|_sqw[sgk58&hSdcldofjqgsafdTxt~j=3.`[pubWlgiiijjd^pfc86+kV}ySk|jq<3/gZstmVndyyQ}su?2(fYrfmoyjaax_mmt95*dWakxSbxjrgnls86+kVzyiaand^nbp`hdq4:'oRj`uu]tmaro582'oRc|gnl\rdj:9%iT~iQkeqvk9465<%iTdl}Puoffvcjh4:'oRfns^coijusWog`0>#c^jbwZtt|4;'oRjnt`]`kphsW~coxe3>1-a\lduX{Ujof3?,b]vw`Ybkj7; nQlololjZekgja6<!mPws]bgnYkg~7; nQ}d^rmpwYpam~c1<>#c^wpaZ`pn}UomyoPcnwmp87+kVbjRocmnqw[`kw|p7; nQ}d^fbpdYdg|dSzgkti?25)eXgoyjaax_mmt95*dW~xT|cz}_vkgpm;68%iT|ah_dosp|Ysqyo6<!mPws]geqgXkfexRyfduj>54*dWyxn`bok_sgdw87+kVndyyQ}su]uei;7$jUcm~Qkauc\gjsi|4:'oR~}of]eqijX|axneQaefcwaZpfd4;;>?"l_vp\``vs`4;;>9"l_qplcZcjx}sTxe|jsi]mabgsmV|j`0;#c^rqkbYbey~rSyf}erj\evubz}U}ma3;,b]kevYqieco1="l_qplcZ`rdeUdk|h^cpw`tsWkg1<>=3-aliuiimg~Tblcj=gkekZ~kfqU:Gu?7_3aoo)eX~hfbhRb`w<2/gZvuadUmekaPtxrf94m91&hS}|`g^dvhiYsqyo6<!mPmdolv|Ysqyo6=!s=e:djbjYdgrT=Fv>8^0`hnYaaoeTkh`jr`vlvZp3W:UsyQ>4:dvhi1<ag~Toae7;oe`fpokl11dzh|ilnub?uthoVof|yw>4:rqkbYbey~rSyf}erj+4,733yxdkRkbpu{\pmtb{a":%<:4psmd[`kw|pUdk|h)0*51=wzfmTi`~{y^vkv`uo :#:86~}of]fiur~W}byi~f'4(37?uthoVof|ywPtipfwm.2!8>0|ah_dosp|Ys`{oxd%8&159svjaXmdzuRzgrdqk,2/6<2zycjQjmqvz[qnumzb#4$?;;qplcZcjx}sTxe|jsi*:-40<x{elShctx]wlwct`531<3?m;qplcZcjx}sTxe|jsi]bwvcu|!:"=o5rne\ahvsqV~c~h}g_`qpawr/9 ;i7}|`g^gntqX|axneQnsrgqp-4.9k1{~biPelrw}ZrozlycSl}|esv+7,7e3yxdkRkbpu{\pmtb{aUj~k}t)6*5g=wzfmTi`~{y^vkv`uoWhyxiz'5(3a?uthoVof|ywPtipfwmYf{zoyx%8&1c9svjaXmdzuRzgrdqk[dutm{~#;$?m;qplcZcjx}sTxe|jsi]bwvcu|!2"=o5rne\ahvsqV~c~h}g_`qpawr/1 ;o7}|`g^gntqX|axneQnsrgqp9?=87;i7}|`g^gntqX|axneQaefcwa-6.9k1{~biPelrw}ZrozlycSckhaug+5,7e3yxdkRkbpu{\pmtb{aUeijo{e)0*5g=wzfmTi`~{y^vkv`uoWgolmyk'3(3a?uthoVof|ywPtipfwmYimnki%:&1c9svjaXmdzuRzgrdqk[kc`i}o#9$?m;qplcZcjx}sTxe|jsi]mabgsm!<"=o5rne\ahvsqV~c~h}g_ogdeqc/? ;i7}|`g^gntqX|axneQaefcwa->.9k1{~biPelrw}ZrozlycSckhaug+=,7c3yxdkRkbpu{\pmtb{aUeijo{e=;94;?<x{elSk{cl018twi`Wog`Rzgrdqk,5/6;2zycjQiumn\pmtb{a":%<=4psmd[cskdV~c~h}g(3+27>vugnUmyabPtipfwm.4!890|ah_gwohZrozlyc$9'>3:rqkbYa}efTxe|jsi*6-45<x{elSk{cl^vkv`uo ?#:?6~}of]eqijX|axne&8)018twi`Wog`Rzgrdqk,=/6;2zycjQiumn\pmtb{a"2%<;4psmd[cskdV~c~h}g<883:4g<x{elSk{cl^vkv`uoWhyxiz'0(3b?uthoVl~`aQ{hsgplZgt{lx$<'>a:rqkbYa}efTxe|jsi]bwvcu|!8"=l5rne\bpjkW}byi~fParqfvq.4!8k0|ah_gwohZrozlycSl}|esv+0,7f3yxdkRhzlm]wlwct`Vkxh|{(4+2e>vugnUmyabPtipfwmYf{zoyx%8&1`9svjaXn|fgSyf}erj\evubz}"<%<o4psmd[cskdV~c~h}g_`qpawr/0 ;j7}|`g^dvhiYs`{oxdRo|sdpw,</6k2zycjQiumn\pmtb{aUj~k}t=;94;7f3yxdkRhzlm]wlwct`Vdnklzj(1+2e>vugnUmyabPtipfwmYimnki%?&1`9svjaXn|fgSyf}erj\j`af|l"9%<o4psmd[cskdV~c~h}g_ogdeqc/; ;j7}|`g^dvhiYs`{oxdR`jg`vf,1/6i2zycjQiumn\pmtb{aUeijo{e)7*5d=wzfmTjxbc_ujqavnXflmjxh&9)0c8twi`Wog`Rzgrdqk[kc`i}o#;$?n;qplcZ`rdeUdk|h^lfcdrb 1#:m6~}of]eqijX|axneQaefcwa-?.9j1{~biPftno[qnumzbTbhintd>:>5813{nToae>0:pg[agsiVidycz'0(33?wbXlh~jSnaznu*2-47<zmUomyoPcnwmp-77!8:0~iQkauc\gjsi|!8"==5}d^fbpdYdg|d$>'>0:pg[agsiVidycz'4(33?wbXlh~jSnaznu*6-46<zmUomyoPcnwmp-0.991yhRjnt`]`kphs >#:<6|k_ecweZeh}g~#4$??;sf\`drfWje~by&6)028vaYci}kTob{at=2=56=ulVnjxlQlotlw846=87;:7jPd`vb[firf}6:<3??;sf\`drfWje~by2>>028vaYci}kTob{at=0=55=ulVnjxlQlotlw868682xoSio{a^alqkr;<7;;7jPd`vb[firf}6>2<>4re]geqgXkfex181119q`Zbf|hUhcx`{<6<24>tcWmkmRm`uov?<;773{nThlzn_bmvjq:>6<1yhRka6:pg[wus;2xxx:5|bhvfvw2<{{y86z}ud;8qkbbzofd{85yamkg2>quWhi`:6y}_bnh55=pzVnjxlQlotlw,5/682}ySio{a^alqkr/9 ;:7z|Pd`vb[firf}":<$??;vp\`drfWje~by&=)028swYci}kTob{at)1*55=pzVnjxlQlotlw,1/682}ySio{a^alqkr/= ;;7z|Pd`vb[firf}"=%<>4ws]geqgXkfex%9&119tvZbf|hUhcx`{(9+24>quWmkmRm`uov+=,773~xThlzn_bmvjq:76890{Qkauc\gjsi|5;;6=0>1:uq[agsiVidycz311<24>quWmkmRm`uov?5;773~xThlzn_bmvjq:568:0{Qkauc\gjsi|595==5xr^fbpdYdg|d090>0:uq[agsiVidycz35?33?rtXlh~jSnaznu>5:46<{UomyoPcnwmp919991|~Rjnt`]`kphs414:<6y}_ecweZeh}g~753;4ws]fj3=pzVxxxpNOpeg2?EF93L187?tS4g90ad=03;8>ij>2;1;37?|f==h6<5a46f90>"3?h0?;95rS4a90ad=03;8>ij>2;1;37?<[8;=69k;:18277bc9;084:<n;R7`>1c3290:??jk1380<24e3m>oi7>51;3xW0c=<mh147?<2ef26?5??;30zY?75;295?7=9l>p_8k54e`9<?74:mn:>7=773;8 10b28;<7[:8b;0xq444281~=?:50:'52b=:;1i8ik50;62>6<39rB?:n5U528745=9;0:57?7:|&2<d<3ll1/8:754ef8m0252900c8:j:18'52`==<20b<9j:198k031290/=:h554:8j41b2810c8;::18'52`==<20b<9j:398k033290/=:h554:8j41b2:10c8;<:18'52`==<20b<9j:598k035290/=:h554:8j41b2<10c8;>:18'52`==<20b<9j:798k037290/=:h554:8j41b2>10c8:i:18'52`==<20b<9j:998k02c290/=:h554:8j41b2010c8:l:18'52`==<20b<9j:`98k04c290/=:h55258j41b2910c8=::18'52`==:=0b<9j:098k053290/=:h55258j41b2;10c8=<:18'52`==:=0b<9j:298k055290/=:h55258j41b2=10c8=>:18'52`==:=0b<9j:498k057290/=:h55258j41b2?10c8<i:18'52`==:=0b<9j:698k04b290/=:h55258j41b2110c8<l:18'52`==:=0b<9j:898k04e290/=:h55258j41b2h10e88<:188k1c52900c9jl:188m02e2900e8:;:188k1da290/=:h54e28j41b2910c9lj:18'52`=<m:0b<9j:098k1dc290/=:h54e28j41b2;10c9ll:18'52`=<m:0b<9j:298k1de290/=:h54e28j41b2=10c9ln:18'52`=<m:0b<9j:498k1d>290/=:h54e28j41b2?10c9l7:18'52`=<m:0b<9j:698k1e0290/=:h54e28j41b2110c9m9:18'52`=<m:0b<9j:898k1e2290/=:h54e28j41b2h10c9m;:18'52`=<m:0b<9j:c98k1e4290/=:h54e28j41b2j10c9m=:18'52`=<m:0b<9j:e98k1e6290/=:h54e28j41b2l10c9m?:18'52`=<m:0b<9j:g98k1d0290/=:h54e28j41b28:07b:m6;29 41a2=n;7c?8e;32?>o31h0;6)?8f;6bf>h6?l0;76g;9883>!70n3>jn6`>7d82?>o3110;6)?8f;6bf>h6?l0976g;9683>!70n3>jn6`>7d80?>o31?0;6)?8f;6bf>h6?l0?76g;9483>!70n3>jn6`>7d86?>o31=0;6)?8f;6bf>h6?l0=76g;9283>!70n3>jn6`>7d84?>o3i;0;6)?8f;6bf>h6?l0376g;a083>!70n3>jn6`>7d8:?>o3i90;6)?8f;6bf>h6?l0j76g;9g83>!70n3>jn6`>7d8a?>o31l0;6)?8f;6bf>h6?l0h76g;9e83>!70n3>jn6`>7d8g?>o31j0;6)?8f;6bf>h6?l0n76g;9c83>!70n3>jn6`>7d8e?>o31;0;6)?8f;6bf>h6?l0:<65f48394?"6?o0?mo5a16g954=<a<8j6=44b54g>5<6290;wE:9c:&2<d<3>m1d=:m50;9~ff7=83;1<7>tH54`?!7?i3i:7bm?:188yg35290257?m6;3f0~N3>j1Q9>4>6za956<6:3;;6<?5e;3:>g<603l1h7?>:0195<<6:3i1=54>0;d9a?b=j3w/=5o54d38 4742kl0(8954ed8 0b=<l:0(<98:05a?l33;3:17b;?8;29?l33>3:17b:8e;29?j3313:17d:71;29?l2aj3:1(<9i:5d`?k70m3:07d:ia;29 41a2=lh7c?8e;38?l2a13:1(<9i:5d`?k70m3807d:i8;29 41a2=lh7c?8e;18?l2a?3:1(<9i:5d`?k70m3>07d:i6;29 41a2=lh7c?8e;78?l2a=3:1(<9i:5d`?k70m3<07d:i4;29 41a2=lh7c?8e;58?l2a;3:1(<9i:5d`?k70m3207d:i2;29 41a2=lh7c?8e;;8?l33:3:17b:j5;29?j33m3:1(<9i:47;?k70m3:07b;:6;29 41a2<?37c?8e;38?j32=3:1(<9i:47;?k70m3807b;:4;29 41a2<?37c?8e;18?j32;3:1(<9i:47;?k70m3>07b;:2;29 41a2<?37c?8e;78?j3293:1(<9i:47;?k70m3<07b;:0;29 41a2<?37c?8e;58?j33n3:1(<9i:47;?k70m3207b;;d;29 41a2<?37c?8e;;8?j33k3:1(<9i:47;?k70m3k07b;=d;29 41a2<9<7c?8e;28?j34=3:1(<9i:414?k70m3;07b;<4;29 41a2<9<7c?8e;08?j34;3:1(<9i:414?k70m3907b;<2;29 41a2<9<7c?8e;68?j3493:1(<9i:414?k70m3?07b;<0;29 41a2<9<7c?8e;48?j35n3:1(<9i:414?k70m3=07b;=e;29 41a2<9<7c?8e;:8?j35k3:1(<9i:414?k70m3307b;=b;29 41a2<9<7c?8e;c8?l3503:1(<9i:40:?k70m3:07d;=7;29 41a2<827c?8e;38?l35>3:1(<9i:40:?k70m3807d;=5;29 41a2<827c?8e;18?l35<3:1(<9i:40:?k70m3>07d;=3;29 41a2<827c?8e;78?l35:3:1(<9i:40:?k70m3<07d;=1;29 41a2<827c?8e;58?l3583:1(<9i:40:?k70m3207d;>f;29 41a2<827c?8e;;8?l31;3:17b:75;29 41a2=2m7c?8e;28?j2?l3:1(<9i:5:e?k70m3;07b:7c;29 41a2=2m7c?8e;08?j2?j3:1(<9i:5:e?k70m3907b:7a;29 41a2=2m7c?8e;68?j2?13:1(<9i:5:e?k70m3?07b:78;29 41a2=2m7c?8e;48?j2??3:1(<9i:5:e?k70m3=07b:76;29 41a2=2m7c?8e;:8?j2?<3:1(<9i:5:e?k70m3307b:73;29 41a2=2m7c?8e;c8?j2b:3:17b:kc;29?l36:3:1(<9i:430?k70m3:07d;>1;29 41a2<;87c?8e;38?l3683:1(<9i:430?k70m3807d;?f;29 41a2<;87c?8e;18?l37m3:1(<9i:430?k70m3>07d;?d;29 41a2<;87c?8e;78?l37k3:1(<9i:430?k70m3<07d;?b;29 41a2<;87c?8e;58?l37i3:1(<9i:430?k70m3207d;?9;29 41a2<;87c?8e;;8?l33j3:17d:j3;29?l2?:3:17d;94;29?j33=3:17b;;a;29?j20n3:17b;;8;29?l33<3:17b:mf;29 41a2=n;7c?8e;28?j2em3:1(<9i:5f3?k70m3;07b:md;29 41a2=n;7c?8e;08?j2ek3:1(<9i:5f3?k70m3907b:mb;29 41a2=n;7c?8e;68?j2ei3:1(<9i:5f3?k70m3?07b:m9;29 41a2=n;7c?8e;48?j2e03:1(<9i:5f3?k70m3=07b:l7;29 41a2=n;7c?8e;:8?j2d>3:1(<9i:5f3?k70m3307b:l5;29 41a2=n;7c?8e;c8?j2d<3:1(<9i:5f3?k70m3h07b:l3;29 41a2=n;7c?8e;a8?j2d:3:1(<9i:5f3?k70m3n07b:l1;29 41a2=n;7c?8e;g8?j2d83:1(<9i:5f3?k70m3l07b:m7;29 41a2=n;7c?8e;33?>i3j?0;6)?8f;6g4>h6?l0:=65f4g294?"6?o0?j<5a16g94>=n<ll1<7*>7g87b4=i9>o1=65f4dg94?"6?o0?j<5a16g96>=n<ln1<7*>7g87b4=i9>o1?65f4da94?"6?o0?j<5a16g90>=n<lh1<7*>7g87b4=i9>o1965f4dc94?"6?o0?j<5a16g92>=n<l31<7*>7g87b4=i9>o1;65f4d:94?"6?o0?j<5a16g9<>=n<l=1<7*>7g87b4=i9>o1565f48c94?"6?o0?mo5a16g94>=n<031<7*>7g87eg=i9>o1=65f48:94?"6?o0?mo5a16g96>=n<0=1<7*>7g87eg=i9>o1?65f48494?"6?o0?mo5a16g90>=n<0?1<7*>7g87eg=i9>o1965f48694?"6?o0?mo5a16g92>=n<091<7*>7g87eg=i9>o1;65f4`094?"6?o0?mo5a16g9<>=n<h;1<7*>7g87eg=i9>o1565f4`294?"6?o0?mo5a16g9e>=n<0l1<7*>7g87eg=i9>o1n65f48g94?"6?o0?mo5a16g9g>=n<0n1<7*>7g87eg=i9>o1h65f48a94?"6?o0?mo5a16g9a>=n<0h1<7*>7g87eg=i9>o1j65f48094?"6?o0?mo5a16g955=<a=3:6=4+16d90dd<f8=n6<?4;h6;4?6=3`?:h7>5$05e>07b3g;<i7>4;h72g?6=,8=m68?j;o34a?7<3`?:n7>5$05e>07b3g;<i7<4;h72e?6=,8=m68?j;o34a?5<3`?:57>5$05e>07b3g;<i7:4;h72<?6=,8=m68?j;o34a?3<3`?:;7>5$05e>07b3g;<i784;h722?6=,8=m68?j;o34a?1<3`?:97>5$05e>07b3g;<i764;h720?6=,8=m68?j;o34a??<3`?;:7>5$05e>0603g;<i7>4;h731?6=,8=m68>8;o34a?7<3`?;87>5$05e>0603g;<i7<4;h737?6=,8=m68>8;o34a?5<3`?;>7>5$05e>0603g;<i7:4;h735?6=,8=m68>8;o34a?3<3`?;<7>5$05e>0603g;<i784;h6eb?6=,8=m68>8;o34a?1<3`>mi7>5$05e>0603g;<i764;h6e`?6=,8=m68>8;o34a??<3f>n:7>5;n6:4?6=3`?9m7>5;c643?6=93:1<v*>8`8`5>N3??1C8;m4ob294?=zj==36=4>:183!7?i3>=h6F;779K03e<g8=h6=44}c66=?6=;3:1<v*>8`8a<>N3??1C8;m4H428 4462<><7)mi:39j11<722c>j7>5;n3;5?6=3th?:94?:283>5}#91k1n55G4648L10d3A?;7)?=1;773>"dn380e8:50;9j1c<722e:4<4?::a00>=8391<7>t$0:b>g><@===7E:9c:J64>"6:80>8:5+cg81?l332900e8h50;9l5=7=831vn98=:186>5<7s-;3m7lk;I642>N3>j1C9=5+1339111<,jl1>6g:4;29?l312900e8h50;9j5=6=831d=5?50;9~f10429086=4?{%3;e?d?3A><:6F;6b9K15=#9;;19994$bd96>o2<3:17d;i:188k4>62900qo::7;291?6=8r.:4l4md:J733=O<?i0D8>4$002>0203-im6?5f5583>>o2>3:17d;i:188m4>72900c<6>:188yg2193:187>50z&2<d<ek2B?;;5G47a8 f`=:2c>87>5;h7e>5<<a82;6=44o0:2>5<<uk>=<7>54;294~"60h0io6F;779K03e<,jl1>6g:4;29?l3a2900e<6?:188k4>62900qo::f;290?6=8r.:4l4mc:J733=O<?i0(nh52:k60?6=3`?m6=44i0:3>5<<g82:6=44}c65e?6=<3:1<v*>8`8ag>N3??1C8;m4$bd96>o2<3:17d;i:188m4>72900c<6>:188yg2113:187>50z&2<d<ek2B?;;5G47a8 f`=:2c>87>5;h7e>5<<a82;6=44o0:2>5<<uk9;>7>54;294~"60h0io6F;779K03e<,jl1;6g:4;29?l3a2900e<6?:188k4>62900qo<6e;291?6=8r.:4l4mb:J733=O<?i0(nh52:k60?6=3`?i6=44i4d94?=n91:1<75`19394?=zj;3m6=4::183!7?i3hi7E:86:J72f=#ko097d;;:188m0d=831b9k4?::k2<5<722e:4<4?::a6d7=83?1<7>t$0:b>gd<@===7E:9c:&`b?4<a<>1<75f5c83>>o2n3:17d?70;29?j7?93:17pl=a383>0<729q/=5o5bc9K020<@=<h7)mi:39j11<722c>n7>5;h7e>5<<a82;6=44o0:2>5<<uk8j?7>55;294~"60h0in6F;779K03e<,jl1>6g:4;29?l3e2900e8h50;9j5=6=831d=5?50;9~f7g3290>6=4?{%3;e?de3A><:6F;6b9'gc<53`??6=44i4`94?=n=o0;66g>8183>>i6080;66sm2`794?3=83:p(<6n:c`8L1113A>=o6*lf;08m02=831b9o4?::k6b?6=3`;3<7>5;n3;5?6=3th9m;4?:483>5}#91k1no5G4648L10d3-im6?5f5583>>o2j3:17d;i:188m4>72900c<6>:188yg4f?3:197>50z&2<d<ej2B?;;5G47a8 f`=:2c>87>5;h7a>5<<a<l1<75f19294?=h91;1<75rb3c;>5<2290;w)?7a;`a?M20>2B?:n5+cg81?l332900e8l50;9j1c<722c:4=4?::m2<4<722wi>l>50;794?6|,82j6ol4H555?M21k2.hj7<4i4694?=n=k0;66g:f;29?l7?83:17b?71;29?xd4?l0;694?:1y'5=g=jj1C8:84H54`?!ea2;1b994?::k6b?6=3`;3<7>5;n3;5?6=3th8;i4?:583>5}#91k1nn5G4648L10d3-im6?5f5583>>o2n3:17d?70;29?j7?93:17pl<b183>1<729q/=5o5b89K020<@=<h7)mi:39j11<722c>n7>5;h7e>5<<g82:6=44}c1a5?6=<3:1<v*>8`8a=>N3??1C8;m4$bd96>o2<3:17d;m:188m0`=831d=5?50;9~f6d4290?6=4?{%3;e?d>3A><:6F;6b9'gc<53`??6=44i4`94?=n=o0;66a>8083>>{e;k>1<7:50;2x 4>f2k30D999;I65g>"dn380e8:50;9j1g<722c>j7>5;n3;5?6=3th8n84?:583>5}#91k1n45G4648L10d3-im6?5f5583>>o2j3:17d;i:188k4>62900qo=m6;290?6=8r.:4l4m9:J733=O<?i0(nh52:k60?6=3`?i6=44i4d94?=h91;1<75rb2`4>5<3290;w)?7a;`:?M20>2B?:n5+cg81?l332900e8l50;9j1c<722e:4<4?::a7g>=83>1<7>t$0:b>g?<@===7E:9c:&`b?4<a<>1<75f5c83>>o2n3:17b?71;29?xd4j00;694?:1y'5=g=j01C8:84H54`?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk9im7>54;294~"60h0i56F;779K03e<,jl1>6g:4;29?l3e2900e8h50;9l5=7=831vn>l=:187>5<7s-;3m7l6;I642>N3>j1/ok4=;h77>5<<a<h1<75f5g83>>i6080;66sm29;94?5=83:p(<6n:03:?M20>2B?:n5+cg800>od;3:17dm;:188k41f2900qo<70;290?6=8r.:4l4>239K020<@=<h7d;7:188m37=831b=5=50;9l52g=831vn?7<:180>5<7s-;3m7:85:J733=O<?i0e8650;9j542=831d=:o50;9~f7>f29086=4?{%3;e?7612B?;;5G47a8 f`=;=1bo>4?::k`0?6=3f;<m7>5;|`1<4<72=0;6=u+19c9574<@===7E:9c:k6<?6=3`<:6=44i0:0>5<<g8=j6=44}c0:0?6=;3:1<v*>8`8730=O<><0D98l;h7;>5<<a8;?6=44o05b>5<<uk83n7>53;294~"60h0:=45G4648L10d3-im6>:4ib194?=nk=0;66a>7`83>>{e:181<7:50;2x 4>f28897E:86:J72f=n=10;66g91;29?l7?;3:17b?8a;29?xd51<0;6>4?:1y'5=g=<>?0D999;I65g>o203:17d?>4;29?j70i3:17pl=8b83>6<729q/=5o510;8L1113A>=o6*lf;17?le42900en:50;9l52g=831vn?6<:187>5<7s-;3m7?=2:J733=O<?i0e8650;9j24<722c:4>4?::m23d<722wi>4850;194?6|,82j699:;I642>N3>j1b954?::k251<722e:;l4?::a6=b=8391<7>t$0:b>47>3A><:6F;6b9'gc<4<2ch?7>5;ha7>5<<g8=j6=44}c0;0?6=<3:1<v*>8`8267=O<><0D98l;h7;>5<<a?;1<75f19194?=h9>k1<75rb3;4>5<4290;w)?7a;641>N3??1C8;m4i4:94?=n98>1<75`16c94?=zj;2n6=4<:183!7?i3;:56F;779K03e<,jl1?95fc283>>od<3:17b?8a;29?xd50<0;694?:1y'5=g=9;80D999;I65g>o203:17d8>:188m4>42900c<9n:188yg4>03:1?7>50z&2<d<3?<1C8:84H54`?l3?2900e<?;:188k41f2900qo<7f;297?6=8r.:4l4>189K020<@=<h7)mi:268mf5=831bo94?::m23d<722wi>5850;694?6|,82j6<<=;I642>N3>j1b954?::k55?6=3`;3?7>5;n34e?6=3th9544?:283>5}#91k18:;4H555?M21k2c>47>5;h320?6=3f;<m7>5;|`1=5<72:0;6=u+19c954?<@===7E:9c:&`b?533`i86=44ib694?=h9>k1<75rb3:4>5<3290;w)?7a;316>N3??1C8;m4i4:94?=n>80;66g>8283>>i6?h0;66sm28c94?5=83:p(<6n:556?M20>2B?:n5f5983>>o69=0;66a>7`83>>{e:0;1<7=50;2x 4>f28;27E:86:J72f=#ko0886gl3;29?le32900c<9n:188yg4?03:187>50z&2<d<6:;1C8:84H54`?l3?2900e;?50;9j5=5=831d=:o50;9~f7?e29086=4?{%3;e?20=2B?;;5G47a8m0>=831b=<:50;9l52g=831vn?7=:180>5<7s-;3m7?>9:J733=O<?i0(nh5359jg6<722ch87>5;n34e?6=3th95n4?:283>5}#91k18:;4H555?M21k2c>47>5;h320?6=3f;<m7>5;|`0=g<72:0;6=u+19c954?<@===7E:9c:&`b?533`i86=44ib694?=h9>k1<75rb2;1>5<3290;w)?7a;316>N3??1C8;m4i4:94?=n>80;66g>8283>>i6?h0;66sm3`794?5=83:p(<6n:556?M20>2B?:n5f5983>>o69=0;66a>7`83>>{e;0i1<7=50;2x 4>f28;27E:86:J72f=#ko0886gl3;29?le32900c<9n:188yg5>;3:187>50z&2<d<6:;1C8:84H54`?l3?2900e;?50;9j5=5=831d=:o50;9~f6g129086=4?{%3;e?20=2B?;;5G47a8m0>=831b=<:50;9l52g=831vn>7k:180>5<7s-;3m7?>9:J733=O<?i0(nh5359jg6<722ch87>5;n34e?6=3th8594?:583>5}#91k1=?<4H555?M21k2c>47>5;h42>5<<a8286=44o05b>5<<uk9j;7>53;294~"60h0?;85G4648L10d3`?36=44i037>5<<g8=j6=44}c1:a?6=;3:1<v*>8`825<=O<><0D98l;%ae>62<aj91<75fc583>>i6?h0;66sm38794?2=83:p(<6n:001?M20>2B?:n5f5983>>o193:17d?73;29?j70i3:17pl<a983>6<729q/=5o54678L1113A>=o6g:8;29?l76<3:17b?8a;29?xd41o0;6>4?:1y'5=g=9830D999;I65g>"dn39?7dm<:188mf2=831d=:o50;9~f6?1290?6=4?{%3;e?75:2B?;;5G47a8m0>=831b:<4?::k2<6<722e:;l4?::a7d?=8391<7>t$0:b>1123A><:6F;6b9j1=<722c:=94?::m23d<722wi?l>50;194?6|,82j6<?6;I642>N3>j1/ok4<4:k`7?6=3`i?6=44o05b>5<<uk92;7>54;294~"60h0:>?5G4648L10d3`?36=44i7394?=n9191<75`16c94?=zj:kj6=4<:183!7?i3><96F;779K03e<a<21<75f10694?=h9>k1<75rb2c2>5<4290;w)?7a;32=>N3??1C8;m4$bd971=nk:0;66gl4;29?j70i3:17pl<9983>1<729q/=5o51308L1113A>=o6g:8;29?l062900e<6<:188k41f2900qo=nb;297?6=8r.:4l4;749K020<@=<h7d;7:188m4732900c<9n:188yg5f:3:1?7>50z&2<d<6901C8:84H54`?!ea2:>0en=50;9jg1<722e:;l4?::a7<?=83>1<7>t$0:b>4453A><:6F;6b9j1=<722c==7>5;h3;7?6=3f;<m7>5;|`0ef<72:0;6=u+19c9023<@===7E:9c:k6<?6=3`;:87>5;n34e?6=3th8m>4?:283>5}#91k1=<74H555?M21k2.hj7=;;ha0>5<<aj>1<75`16c94?=zj:3j6=4;:183!7?i3;9>6F;779K03e<a<21<75f6083>>o60:0;66a>7`83>>{e;hn1<7=50;2x 4>f2==>7E:86:J72f=n=10;66g>1583>>i6?h0;66sm3`694?5=83:p(<6n:03:?M20>2B?:n5+cg800>od;3:17dm;:188k41f2900qo=ne;297?6=8r.:4l4;749K020<@=<h7d;7:188m4732900c<9n:188yg4b:3:187>50z&2<d<6:;1C8:84H54`?l3?2900e;?50;9j5=5=831d=:o50;9~f7c6290?6=4?{%3;e?75:2B?;;5G47a8m0>=831b:<4?::k2<6<722e:;l4?::a6`6=83>1<7>t$0:b>4453A><:6F;6b9j1=<722c==7>5;h3;7?6=3f;<m7>5;|`1`c<72=0;6=u+19c9574<@===7E:9c:k6<?6=3`<:6=44i0:0>5<<g8=j6=44}c0ga?6=<3:1<v*>8`8267=O<><0D98l;h7;>5<<a?;1<75f19194?=h9>k1<75rb3d6>5<3290;w)?7a;316>N3??1C8;m4i4:94?=n>80;66g>8283>>i6?h0;66sm2g694?2=83:p(<6n:001?M20>2B?:n5f5983>>o193:17d?73;29?j70i3:17pl=f283>1<729q/=5o51308L1113A>=o6g:8;29?l062900e<6<:188k41f2900qo<i2;290?6=8r.:4l4>239K020<@=<h7d;7:188m37=831b=5=50;9l52g=831vn?h>:187>5<7s-;3m7?=2:J733=O<?i0e8650;9j24<722c:4>4?::m23d<722wi?8j50;694?6|,82j6<<=;I642>N3>j1b954?::k55?6=3`;3?7>5;n34e?6=3th89n4?:583>5}#91k1=?<4H555?M21k2c>47>5;h42>5<<a8286=44o05b>5<<uk9>n7>54;294~"60h0:>?5G4648L10d3`?36=44i7394?=n9191<75`16c94?=zj:?j6=4;:183!7?i3;9>6F;779K03e<a<21<75f6083>>o60:0;66a>7`83>>{e;<31<7:50;2x 4>f28897E:86:J72f=n=10;66g91;29?l7?;3:17b?8a;29?xd4?90;694?:1y'5=g=9;80D999;I65g>o203:17d8>:188m4>42900c<9n:188yg51n3:187>50z&2<d<6:;1C8:84H54`?l3?2900e;?50;9j5=5=831d=:o50;9~f60b290?6=4?{%3;e?75:2B?;;5G47a8m0>=831b:<4?::k2<6<722e:;l4?::a73b=83>1<7>t$0:b>4453A><:6F;6b9j1=<722c==7>5;h3;7?6=3f;<m7>5;|`02f<72=0;6=u+19c9574<@===7E:9c:k6<?6=3`<:6=44i0:0>5<<g8=j6=44}c3a4?6=<3:1<v*>8`8a=>N3??1C8;m4$bd96>o2<3:17d;m:188m0`=831d=5?50;9~f4ga290?6=4?{%3;e?d>3A><:6F;6b9'gc<53`??6=44i4`94?=n=o0;66a>8083>>{e9ho1<7:50;2x 4>f2k30D999;I65g>"dn380e8:50;9j1g<722c>j7>5;n3;5?6=3th:mi4?:583>5}#91k1n45G4648L10d3-im6?5f5583>>o2j3:17d;i:188k4>62900qo?nc;290?6=8r.:4l4m9:J733=O<?i0(nh52:k60?6=3`?i6=44i4d94?=h91;1<75rb0ca>5<3290;w)?7a;`:?M20>2B?:n5+cg81?l332900e8l50;9j1c<722e:4<4?::a5dg=83>1<7>t$0:b>g?<@===7E:9c:&`b?4<a<>1<75f5c83>>o2n3:17b?71;29?xd6i00;694?:1y'5=g=j01C8:84H54`?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;j47>54;294~"60h0i56F;779K03e<,jl1>6g:4;29?l3e2900e8h50;9l5=7=831vn<o8:187>5<7s-;3m7l6;I642>N3>j1/ok4=;h77>5<<a<h1<75f5g83>>i6080;66sm20f94?2=83:p(<6n:c;8L1113A>=o6*lf;08m02=831b9o4?::k6b?6=3f;3=7>5;|`15f<72=0;6=u+19c9f<=O<><0D98l;%ae>7=n==0;66g:b;29?l3a2900c<6>:188yg46j3:187>50z&2<d<e12B?;;5G47a8 f`=:2c>87>5;h7a>5<<a<l1<75`19394?=zj;;j6=4;:183!7?i3h27E:86:J72f=#ko097d;;:188m0d=831b9k4?::m2<4<722wi><750;694?6|,82j6o74H555?M21k2.hj7<4i4694?=n=k0;66g:f;29?j7?93:17pl=1983>1<729q/=5o5b89K020<@=<h7)mi:39j11<722c>n7>5;h7e>5<<g82:6=44}c023?6=<3:1<v*>8`8a=>N3??1C8;m4$bd96>o2<3:17d;m:188m0`=831d=5?50;9~f771290?6=4?{%3;e?d>3A><:6F;6b9'gc<53`??6=44i4`94?=n=o0;66a>8083>>{e:8?1<7:50;2x 4>f2k30D999;I65g>"dn380e8:50;9j1g<722c>j7>5;n3;5?6=3th9=94?:583>5}#91k1n45G4648L10d3-im6?5f5583>>o2j3:17d;i:188k4>62900qo<9d;290?6=8r.:4l4m9:J733=O<?i0(nh52:k60?6=3`?i6=44i4d94?=h91;1<75rb34`>5<3290;w)?7a;`:?M20>2B?:n5+cg81?l332900e8l50;9j1c<722e:4<4?::a63d=83>1<7>t$0:b>g?<@===7E:9c:&`b?4<a<>1<75f5c83>>o2n3:17b?71;29?xd5>h0;694?:1y'5=g=j01C8:84H54`?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8=57>54;294~"60h0i56F;779K03e<,jl1>6g:4;29?l3e2900e8h50;9l5=7=831vn?87:187>5<7s-;3m7l6;I642>N3>j1/ok4=;h77>5<<a<h1<75f5g83>>i6080;66sm27594?2=83:p(<6n:c;8L1113A>=o6*lf;08m02=831b9o4?::k6b?6=3f;3=7>5;|`123<72=0;6=u+19c9f<=O<><0D98l;%ae>7=n==0;66g:b;29?l3a2900c<6>:188yg41=3:187>50z&2<d<e12B?;;5G47a8 f`=:2c>87>5;h7a>5<<a<l1<75`19394?=zj;<?6=4;:183!7?i3h27E:86:J72f=#ko097d;;:188m0d=831b9k4?::m2<4<722wi>=>50;694?6|,82j6o74H555?M21k2.hj7<4i4694?=n=k0;66g:f;29?j7?93:17pl>fg83>1<729q/=5o5b89K020<@=<h7)mi:39j11<722c>n7>5;h7e>5<<g82:6=44}c3ea?6=<3:1<v*>8`8a=>N3??1C8;m4$bd96>o2<3:17d;m:188m0`=831d=5?50;9~f4`c290?6=4?{%3;e?d>3A><:6F;6b9'gc<53`??6=44i4`94?=n=o0;66a>8083>>{e9oi1<7:50;2x 4>f2k30D999;I65g>"dn380e8:50;9j1g<722c>j7>5;n3;5?6=3th:jo4?:583>5}#91k1n45G4648L10d3-im6?5f5583>>o2j3:17d;i:188k4>62900qo?ia;290?6=8r.:4l4m9:J733=O<?i0(nh52:k60?6=3`?i6=44i4d94?=h91;1<75rb0d:>5<3290;w)?7a;`:?M20>2B?:n5+cg81?l332900e8l50;9j1c<722e:4<4?::a5c>=83>1<7>t$0:b>g?<@===7E:9c:&`b?4<a<>1<75f5c83>>o2n3:17b?71;29?xd6n>0;694?:1y'5=g=j01C8:84H54`?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>57>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>47>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>;7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>:7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>97>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>87>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>?7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>>7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8>=7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk8><7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;no7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;nn7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;nm7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;n57>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;n47>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;n;7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;n:7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;n97>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;n87>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;n?7>54;294~"60h0i56F;779K03e<@<:0(<<>:464?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk;o47>54;294~"60h0i56F;779K03e<,jl1>6g:4;29?l3e2900e8h50;9l5=7=831vn<j8:187>5<7s-;3m7l6;I642>N3>j1/ok4=;h77>5<<a<h1<75f5g83>>i6080;66sm1e494?2=83:p(<6n:c;8L1113A>=o6*lf;08m02=831b9o4?::k6b?6=3f;3=7>5;|`2`0<72=0;6=u+19c9f<=O<><0D98l;%ae>7=n==0;66g:b;29?l3a2900c<6>:188yg7c<3:187>50z&2<d<e12B?;;5G47a8 f`=:2c>87>5;h7a>5<<a<l1<75`19394?=zj8n86=4;:183!7?i3h27E:86:J72f=#ko097d;;:188m0d=831b9k4?::m2<4<722wi=i<50;694?6|,82j6o74H555?M21k2.hj7<4i4694?=n=k0;66g:f;29?j7?93:17pl>d083>1<729q/=5o5b89K020<@=<h7)mi:39j11<722c>n7>5;h7e>5<<g82:6=44}c3g4?6=<3:1<v*>8`8a=>N3??1C8;m4$bd96>o2<3:17d;m:188m0`=831d=5?50;9~f4ea290?6=4?{%3;e?d>3A><:6F;6b9'gc<53`??6=44i4`94?=n=o0;66a>8083>>{e:=?1<7:50;2x 4>f2k30D999;I65g>"dn380e8:50;9j1g<722c>j7>5;n3;5?6=3th9894?:583>5}#91k1n45G4648L10d3-im6?5f5583>>o2j3:17d;i:188k4>62900qo<;3;290?6=8r.:4l4m9:J733=O<?i0(nh52:k60?6=3`?i6=44i4d94?=h91;1<75rb361>5<3290;w)?7a;`:?M20>2B?:n5+cg81?l332900e8l50;9j1c<722e:4<4?::a617=83>1<7>t$0:b>g?<@===7E:9c:&`b?4<a<>1<75f5c83>>o2n3:17b?71;29?xd5<90;694?:1y'5=g=j01C8:84H54`?!ea2;1b994?::k6f?6=3`?m6=44o0:2>5<<uk88j7>54;294~"60h0i56F;779K03e<,jl1>6g:4;29?l3e2900e8h50;9l5=7=831vn?=j:187>5<7s-;3m7l6;I642>N3>j1/ok4=;h77>5<<a<h1<75f5g83>>i6080;66sm22f94?2=83:p(<6n:c;8L1113A>=o6*lf;08m02=831b9o4?::k6b?6=3f;3=7>5;|`17f<72=0;6=u+19c9f<=O<><0D98l;%ae>7=n==0;66g:b;29?l3a2900c<6>:188yg5383:197>50z&2<d<ei2B?;;5G47a8 f`=:2c>87>5;h75>5<<a<h1<75f5g83>>i6080;66sm32d94?3=83:p(<6n:cc8L1113A>=o6*lf;08m02=831b9;4?::k6f?6=3`?m6=44o0:2>5<<uk98h7>55;294~"60h0im6F;779K03e<,jl1>6g:4;29?l312900e8l50;9j1c<722e:4<4?::a76e=83?1<7>t$0:b>gg<@===7E:9c:&`b?4<a<>1<75f5783>>o2j3:17d;i:188k4>62900qo=<e;291?6=8r.:4l4ma:J733=O<?i0(nh52:k60?6=3`?=6=44i4`94?=n=o0;66a>8083>>{e;:h1<7;50;2x 4>f2kk0D999;I65g>"dn380e8:50;9j13<722c>n7>5;h7e>5<<g82:6=44}c10e?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi?>650;794?6|,82j6oo4H555?M21k2.hj7<4i4694?=n=?0;66g:b;29?l3a2900c<6>:188yg54?3:197>50z&2<d<el2B?;;5G47a8 f`=?2c>87>5;h75>5<<a<l1<75f19294?=h91;1<75rb21:>5<2290;w)?7a;`b?M20>2B?:n5+cg81?l332900e8850;9j1g<722c>j7>5;n3;5?6=3th8>o4?:283>5}#91k18:;4H555?M21k2c>47>5;h320?6=3f;<m7>5;|`06d<72:0;6=u+19c9023<@===7E:9c:k6<?6=3`;:87>5;n34e?6=3th8>=4?:583>5}#91k1=?<4H555?M21k2c>47>5;h42>5<<a8286=44o05b>5<<uk9957>53;294~"60h0?;85G4648L10d3`?36=44i037>5<<g8=j6=44}c12a?6=<3:1<v*>8`8267=O<><0D98l;h7;>5<<a?;1<75f19194?=h9>k1<75rb20;>5<4290;w)?7a;641>N3??1C8;m4i4:94?=n98>1<75`16c94?=zj:;h6=4;:183!7?i3;9>6F;779K03e<a<21<75f6083>>o60:0;66a>7`83>>{e;;=1<7=50;2x 4>f2==>7E:86:J72f=n=10;66g>1583>>i6?h0;66sm30c94?2=83:p(<6n:001?M20>2B?:n5f5983>>o193:17d?73;29?j70i3:17pl<2783>6<729q/=5o54678L1113A>=o6g:8;29?l76<3:17b?8a;29?xd4910;694?:1y'5=g=9;80D999;I65g>o203:17d8>:188m4>42900c<9n:188yg55=3:1?7>50z&2<d<3?<1C8:84H54`?l3?2900e<?;:188k41f2900qo=>6;290?6=8r.:4l4>239K020<@=<h7d;7:188m37=831b=5=50;9l52g=831vn><;:180>5<7s-;3m7:85:J733=O<?i0e8650;9j542=831d=:o50;9~f673290?6=4?{%3;e?75:2B?;;5G47a8m0>=831b:<4?::k2<6<722e:;l4?::a775=8391<7>t$0:b>1123A><:6F;6b9j1=<722c:=94?::m23d<722wi?<<50;694?6|,82j6<<=;I642>N3>j1b954?::k55?6=3`;3?7>5;n34e?6=3th8>?4?:283>5}#91k18:;4H555?M21k2c>47>5;h320?6=3f;<m7>5;|`055<72=0;6=u+19c9574<@===7E:9c:k6<?6=3`<:6=44i0:0>5<<g8=j6=44}c160?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi?8=50;794?6|,82j6oo4H555?M21k2.hj7<4i4694?=n=?0;66g:b;29?l3a2900c<6>:188yg52:3:197>50z&2<d<ei2B?;;5G47a8 f`=:2c>87>5;h75>5<<a<h1<75f5g83>>i6080;66sm34394?3=83:p(<6n:cc8L1113A>=o6*lf;08m02=831b9;4?::k6f?6=3`?m6=44o0:2>5<<uk9><7>55;294~"60h0im6F;779K03e<,jl1>6g:4;29?l312900e8l50;9j1c<722e:4<4?::a71`=83?1<7>t$0:b>gg<@===7E:9c:&`b?4<a<>1<75f5783>>o2j3:17d;i:188k4>62900qo=;e;291?6=8r.:4l4ma:J733=O<?i0(nh52:k60?6=3`?=6=44i4`94?=n=o0;66a>8083>>{e;=n1<7;50;2x 4>f2kk0D999;I65g>"dn380e8:50;9j13<722c>n7>5;h7e>5<<g82:6=44}c17g?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi?9l50;794?6|,82j6oo4H555?M21k2.hj7<4i4694?=n=?0;66g:b;29?l3a2900c<6>:188yg4c:3:187>50z&2<d<e12B?;;5G47a8 f`=:2c>87>5;h7a>5<<a<l1<75`19394?=zj;im6=4;:183!7?i3h27E:86:J72f=#ko097d;;:188m0d=831b9k4?::m2<4<722wi>i750;694?6|,82j6o74H555?M21k2.hj7<4i4694?=n=k0;66g:f;29?j7?93:17pl=d783>1<729q/=5o5bb9K020<@=<h7)mi:69j11<722c>j7>5;h3;4?6=3f;3=7>5;|`1`0<72=0;6=u+19c9ff=O<><0D98l;%ae>2=n==0;66g:f;29?l7?83:17b?71;29?xd38=0;684?:1y'5=g=jh1C8:84H54`?!ea2;1b994?::k62?6=3`?i6=44i4d94?=h91;1<75rb520>5<2290;w)?7a;`b?M20>2B?:n5+cg81?l332900e8850;9j1g<722c>j7>5;n3;5?6=3th?<<4?:483>5}#91k1nl5G4648L10d3-im6?5f5583>>o2>3:17d;m:188m0`=831d=5?50;9~f167290>6=4?{%3;e?df3A><:6F;6b9'gc<53`??6=44i4494?=n=k0;66g:f;29?j7?93:17pl;0383>0<729q/=5o5b`9K020<@=<h7)mi:39j11<722c>:7>5;h7a>5<<a<l1<75`19394?=zj:lm6=4::183!7?i3hj7E:86:J72f=#ko097d;;:188m00=831b9o4?::k6b?6=3f;3=7>5;|`0b`<72<0;6=u+19c9fd=O<><0D98l;%ae>7=n==0;66g:6;29?l3e2900e8h50;9l5=7=831vn>hl:186>5<7s-;3m7lk;I642>N3>j1/ok48;h77>5<<a<<1<75f5g83>>o6090;66a>8083>>{e;oh1<7;50;2x 4>f2kk0D999;I65g>"dn380e8:50;9j13<722c>n7>5;h7e>5<<g82:6=44}c1e`?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi?hh50;194?6|,82j699:;I642>N3>j1b954?::k251<722e:;l4?::a7`c=8391<7>t$0:b>1123A><:6F;6b9j1=<722c:=94?::m23d<722wi?h:50;694?6|,82j6<<=;I642>N3>j1b954?::k55?6=3`;3?7>5;n34e?6=3th8ii4?:283>5}#91k18:;4H555?M21k2c>47>5;h320?6=3f;<m7>5;|`0a7<72=0;6=u+19c9574<@===7E:9c:k6<?6=3`<:6=44i0:0>5<<g8=j6=44}c1fg?6=;3:1<v*>8`8730=O<><0D98l;h7;>5<<a8;?6=44o05b>5<<uk9n<7>54;294~"60h0:>?5G4648L10d3`?36=44i7394?=n9191<75`16c94?=zj:oi6=4<:183!7?i3><96F;779K03e<a<21<75f10694?=h9>k1<75rb2ff>5<3290;w)?7a;316>N3??1C8;m4i4:94?=n>80;66g>8283>>i6?h0;66sm3dc94?5=83:p(<6n:556?M20>2B?:n5f5983>>o69=0;66a>7`83>>{e;mi1<7:50;2x 4>f28897E:86:J72f=n=10;66g91;29?l7?;3:17b?8a;29?xd4m00;6>4?:1y'5=g=<>?0D999;I65g>o203:17d?>4;29?j70i3:17pl<d`83>1<729q/=5o51308L1113A>=o6g:8;29?l062900e<6<:188k41f2900qo=j8;297?6=8r.:4l4;749K020<@=<h7d;7:188m4732900c<9n:188yg5c03:187>50z&2<d<6:;1C8:84H54`?l3?2900e;?50;9j5=5=831d=:o50;9~f6c029086=4?{%3;e?20=2B?;;5G47a8m0>=831b=<:50;9l52g=831vn>j9:187>5<7s-;3m7?=2:J733=O<?i0e8650;9j24<722c:4>4?::m23d<722wi?h850;194?6|,82j699:;I642>N3>j1b954?::k251<722e:;l4?::a7a2=83>1<7>t$0:b>4453A><:6F;6b9j1=<722c==7>5;h3;7?6=3f;<m7>5;|`754<72<0;6=u+19c9fd=O<><0D98l;%ae>7=n==0;66g:6;29?l3e2900e8h50;9l5=7=831vn9>i:186>5<7s-;3m7lk;I642>N3>j1/ok48;h77>5<<a<<1<75f5g83>>o6090;66a>8083>>{e<8:1<7;50;2x 4>f2kk0D999;I65g>"dn380e8:50;9j13<722c>n7>5;h7e>5<<g82:6=44}c626?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi8<=50;794?6|,82j6oo4H555?M21k2.hj7<4i4694?=n=?0;66g:b;29?l3a2900c<6>:188yg26>3:197>50z&2<d<ei2B?;;5G47a8 f`=:2c>87>5;h75>5<<a<h1<75f5g83>>i6080;66sm40694?3=83:p(<6n:cc8L1113A>=o6*lf;08m02=831b9;4?::k6f?6=3`?m6=44o0:2>5<<uk>:97>55;294~"60h0im6F;779K03e<,jl1>6g:4;29?l312900e8l50;9j1c<722e:4<4?::a041=83?1<7>t$0:b>gg<@===7E:9c:&`b?4<a<>1<75f5783>>o2j3:17d;i:188k4>62900qo:>8;291?6=8r.:4l4ma:J733=O<?i0(nh52:k60?6=3`?=6=44i4`94?=n=o0;66a>8083>>{e<;i1<7;50;2x 4>f2kk0D999;I65g>"dn380e8:50;9j13<722c>n7>5;h7e>5<<g82:6=44}c61f?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi8?o50;794?6|,82j6oo4H555?M21k2.hj7<4i4694?=n=?0;66g:b;29?l3a2900c<6>:188yg2513:197>50z&2<d<ei2B?;;5G47a8 f`=:2c>87>5;h75>5<<a<h1<75f5g83>>i6080;66sm43:94?3=83:p(<6n:cc8L1113A>=o6*lf;08m02=831b9;4?::k6f?6=3`?m6=44o0:2>5<<uk>9;7>55;294~"60h0im6F;779K03e<,jl1>6g:4;29?l312900e8l50;9j1c<722e:4<4?::a070=83?1<7>t$0:b>gg<@===7E:9c:&`b?4<a<>1<75f5783>>o2j3:17d;i:188k4>62900qo:=5;291?6=8r.:4l4ma:J733=O<?i0(nh52:k60?6=3`?=6=44i4`94?=n=o0;66a>8083>>{e<;>1<7;50;2x 4>f2kk0D999;I65g>"dn380e8:50;9j13<722c>n7>5;h7e>5<<g82:6=44}c617?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi8>850;794?6|,82j6oo4H555?M21k2.hj7<4i4694?=n=?0;66g:b;29?l3a2900c<6>:188yg24=3:197>50z&2<d<ei2B?;;5G47a8 f`=:2c>87>5;h75>5<<a<h1<75f5g83>>i6080;66sm42694?3=83:p(<6n:cc8L1113A>=o6*lf;08m02=831b9;4?::k6f?6=3`?m6=44o0:2>5<<uk>8?7>55;294~"60h0im6F;779K03e<,jl1>6g:4;29?l312900e8l50;9j1c<722e:4<4?::a064=83?1<7>t$0:b>gg<@===7E:9c:&`b?4<a<>1<75f5783>>o2j3:17d;i:188k4>62900qo:<1;291?6=8r.:4l4ma:J733=O<?i0(nh52:k60?6=3`?=6=44i4`94?=n=o0;66a>8083>>{e<::1<7;50;2x 4>f2kk0D999;I65g>"dn380e8:50;9j13<722c>n7>5;h7e>5<<g82:6=44}c61b?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi8>k50;794?6|,82j6oo4H555?M21k2.hj7<4i4694?=n=?0;66g:b;29?l3a2900c<6>:188yg24l3:197>50z&2<d<ei2B?;;5G47a8 f`=:2c>87>5;h75>5<<a<h1<75f5g83>>i6080;66sm42a94?3=83:p(<6n:cc8L1113A>=o6*lf;08m02=831b9;4?::k6f?6=3`?m6=44o0:2>5<<uk>8n7>55;294~"60h0im6F;779K03e<,jl1>6g:4;29?l312900e8l50;9j1c<722e:4<4?::a06g=83?1<7>t$0:b>gg<@===7E:9c:&`b?4<a<>1<75f5783>>o2j3:17d;i:188k4>62900qo:<9;291?6=8r.:4l4ma:J733=O<?i0(nh52:k60?6=3`?=6=44i4`94?=n=o0;66a>8083>>{e<:21<7;50;2x 4>f2kk0D999;I65g>"dn380e8:50;9j13<722c>n7>5;h7e>5<<g82:6=44}c603?6==3:1<v*>8`8ae>N3??1C8;m4$bd96>o2<3:17d;9:188m0d=831b9k4?::m2<4<722wi8?k50;794?6|,82j6oo4H555?M21k2.hj7<4i4694?=n=?0;66g:b;29?l3a2900c<6>:188yg25l3:197>50z&2<d<ei2B?;;5G47a8 f`=:2c>87>5;h75>5<<a<h1<75f5g83>>i6080;66sm47494?5=83:p(<6n:03:?M20>2B?:n5+cg817>od;3:17dm;:188k41f2900qo::b;297?6=8r.:4l4>189K020<@=<h7)mi:318mf5=831bo94?::m23d<722wi><h50;194?6|,82j6<?6;I642>N3>j1/ok4=5:k`7?6=3`i?6=44o05b>5<<uk;i>7>53;294~"60h0:=45G4648L10d3-im6?;4ib194?=nk=0;66a>7`83>>{e90i1<7=50;2x 4>f28;27E:86:J72f=#ko0996gl3;29?le32900c<9n:188yg7>j3:1?7>50z&2<d<6901C8:84H54`?!ea2;?0en=50;9jg1<722e:;l4?::a5<g=8391<7>t$0:b>47>3A><:6F;6b9'gc<5=2ch?7>5;ha7>5<<g8=j6=44}c3:=?6=;3:1<v*>8`825<=O<><0D98l;%ae>73<aj91<75fc583>>i6?h0;66sm18:94?5=83:p(<6n:03:?M20>2B?:n5+cg811>od;3:17dm;:188k41f2900qo?67;297?6=8r.:4l4>189K020<@=<h7)mi:378mf5=831bo94?::m23d<722wi=4850;194?6|,82j6<?6;I642>N3>j1/ok4=5:k`7?6=3`i?6=44o05b>5<<uk;297>53;294~"60h0:=45G4648L10d3-im6?;4ib194?=nk=0;66a>7`83>>{e90>1<7=50;2x 4>f28;27E:86:J72f=#ko0996gl3;29?le32900c<9n:188yg7>;3:1?7>50z&2<d<6901C8:84H54`?!ea2;?0en=50;9jg1<722e:;l4?::a5<4=8391<7>t$0:b>47>3A><:6F;6b9'gc<5=2ch?7>5;ha7>5<<g8=j6=44}c3:5?6=;3:1<v*>8`825<=O<><0D98l;%ae>73<aj91<75fc583>>i6?h0;66sm18294?5=83:p(<6n:03:?M20>2B?:n5+cg811>od;3:17dm;:188k41f2900qo?7f;297?6=8r.:4l4>189K020<@=<h7)mi:378mf5=831bo94?::m23d<722wi=5k50;194?6|,82j6<?6;I642>N3>j1/ok4=5:k`7?6=3`i?6=44o05b>5<<uk;3h7>53;294~"60h0:=45G4648L10d3-im6?;4ib194?=nk=0;66a>7`83>>{e91i1<7=50;2x 4>f28;27E:86:J72f=#ko0996gl3;29?le32900c<9n:188yg7?j3:1?7>50z&2<d<6901C8:84H54`?!ea2;?0en=50;9jg1<722e:;l4?::a677=83>1<7>t$0:b>47e3A><:6F;6b9'gc<4>2ch?7>5;ha7>5<<aj?1<75`16c94?=zj8h?6=4;:183!7?i3;:n6F;779K03e<,jl1?;5fc283>>od<3:17dm::188k41f2900qo<k1;290?6=8r.:4l4>1c9K020<@=<h7)mi:3f8mf5=831bo94?::k`1?6=3f;<m7>5;|`166<72<0;6=u+19c954c<@===7E:9c:&`b?4>3`i86=44ib694?=nk<0;66gl6;29?j70i3:17pl>b783>0<729q/=5o510g8L1113A>=o6*lf;0:?le42900en:50;9jg0<722ch:7>5;n34e?6=3th9h54?:483>5}#91k1=<k4H555?M21k2.hj7;:;ha0>5<<aj>1<75fc483>>od>3:17b?8a;29?xd5l=0;684?:1y'5=g=98o0D999;I65g>"dn38j7dm<:188mf2=831bo84?::k`2?6=3f;<m7>5;|`0g<<72:0;6=u+19c954?<@===7E:9c:&`b?443`i86=44ib694?=h9>k1<75rb3ag>5<3290;w)?7a;32f>N3??1C8;m4$bd962=nk:0;66gl4;29?le22900c<9n:188yg45=3:1?7>50z&2<d<6901C8:84H54`?!ea2;?0en=50;9jg1<722e:;l4?::a5g>=8391<7>t$0:b>47>3A><:6F;6b9'gc<5=2ch?7>5;ha7>5<<g8=j6=44}c013?6=<3:1<v*>8`825g=O<><0D98l;%ae>60<aj91<75fc583>>od=3:17b?8a;29?xd6jh0;694?:1y'5=g=98h0D999;I65g>"dn39=7dm<:188mf2=831bo84?::m23d<722wi>?750;794?6|,82j6<?j;I642>N3>j1/ok4=9:k`7?6=3`i?6=44ib794?=nk?0;66a>7`83>>{e9ki1<7;50;2x 4>f28;n7E:86:J72f=#ko0956gl3;29?le32900en;50;9jg3<722e:;l4?::a6fe=83?1<7>t$0:b>47b3A><:6F;6b9'gc<5<2ch?7>5;ha7>5<<aj?1<75fc783>>i6?h0;66sm44194?5=83:p(<6n:03:?M20>2B?:n5+cg8a6>od;3:17dm;:188k41f2900qo=8a;291?6=8r.:4l4>1d9K020<@=<h7)mi:278mf5=831bo94?::k`1?6=3`i=6=44o05b>5<<uk9=;7>55;294~"60h0:=h5G4648L10d3-im6>;4ib194?=nk=0;66gl5;29?le12900c<9n:188yg4an3:197>50z&2<d<69l1C8:84H54`?!ea2:?0en=50;9jg1<722ch97>5;ha5>5<<g8=j6=44}c0fg?6==3:1<v*>8`825`=O<><0D98l;%ae>63<aj91<75fc583>>od=3:17dm9:188k41f2900qo=89;291?6=8r.:4l4>1d9K020<@=<h7)mi:278mf5=831bo94?::k`1?6=3`i=6=44o05b>5<<uk9=:7>55;294~"60h0:=h5G4648L10d3-im6>;4ib194?=nk=0;66gl5;29?le12900c<9n:188yg4am3:197>50z&2<d<69l1C8:84H54`?!ea2:?0en=50;9jg1<722ch97>5;ha5>5<<g8=j6=44}c0ff?6==3:1<v*>8`825`=O<><0D98l;%ae>63<aj91<75fc583>>od=3:17dm9:188k41f2900qo<na;291?6=8r.:4l4>1d9K020<@=<h7)mi:338mf5=831bo94?::k`1?6=3`i=6=44o05b>5<<uk9<47>55;294~"60h0:=h5G4648L10d3-im6>;4ib194?=nk=0;66gl5;29?le12900c<9n:188yg51=3:197>50z&2<d<69l1C8:84H54`?!ea2:?0en=50;9jg1<722ch97>5;ha5>5<<g8=j6=44}c0e`?6==3:1<v*>8`825`=O<><0D98l;%ae>63<aj91<75fc583>>od=3:17dm9:188k41f2900qo<ja;291?6=8r.:4l4>1d9K020<@=<h7)mi:278mf5=831bo94?::k`1?6=3`i=6=44o05b>5<<uk9<;7>55;294~"60h0:=h5G4648L10d3-im6>;4ib194?=nk=0;66gl5;29?le12900c<9n:188yg51<3:197>50z&2<d<69l1C8:84H54`?!ea2:?0en=50;9jg1<722ch97>5;ha5>5<<g8=j6=44}c0eg?6==3:1<v*>8`825`=O<><0D98l;%ae>63<aj91<75fc583>>od=3:17dm9:188k41f2900qo<j9;291?6=8r.:4l4>1d9K020<@=<h7)mi:278mf5=831bo94?::k`1?6=3`i=6=44o05b>5<<uk9;87>54;294~"60h0:=o5G4648L10d3-im6o94ib194?=nk=0;66gl5;29?j70i3:17pl<8183>0<729q/=5o510g8L1113A>=o6*lf;72?le42900en:50;9jg0<722ch:7>5;n34e?6=3th8;;4?:483>5}#91k1=<k4H555?M21k2.hj7=:;ha0>5<<aj>1<75fc483>>od>3:17b?8a;29?xd4>:0;684?:1y'5=g=98o0D999;I65g>"dn39>7dm<:188mf2=831bo84?::k`2?6=3f;<m7>5;|`1bg<72<0;6=u+19c954c<@===7E:9c:&`b?523`i86=44ib694?=nk<0;66gl6;29?j70i3:17pl=e983>0<729q/=5o510g8L1113A>=o6*lf;16?le42900en:50;9jg0<722ch:7>5;n34e?6=3th9>n4?:283>5}#91k1=<74H555?M21k2.hj7=;;ha0>5<<aj>1<75`16c94?=zj8hm6=4<:183!7?i3;:56F;779K03e<,jl1?95fc283>>od<3:17b?8a;29?xd5:o0;694?:1y'5=g=98h0D999;I65g>"dn3837dm<:188mf2=831bo84?::m23d<722wi=n<50;694?6|,82j6<?m;I642>N3>j1/ok4=8:k`7?6=3`i?6=44ib794?=h9>k1<75rb312>5<2290;w)?7a;32a>N3??1C8;m4$bd972=nk:0;66gl4;29?le22900en850;9l52g=831vn?<m:186>5<7s-;3m7?>e:J733=O<?i0(nh5369jg6<722ch87>5;ha6>5<<aj<1<75`16c94?=zj8i?6=4::183!7?i3;:i6F;779K03e<,jl1?:5fc283>>od<3:17dm::188mf0=831d=:o50;9~f4db290>6=4?{%3;e?76m2B?;;5G47a8 f`=;>1bo>4?::k`0?6=3`i>6=44ib494?=h9>k1<75rb3cf>5<4290;w)?7a;32=>N3??1C8;m4$bd966=nk:0;66gl4;29?j70i3:17pl<8g83>6<729q/=5o510;8L1113A>=o6*lf;06?le42900en:50;9l52g=831vn?l?:187>5<7s-;3m7?>b:J733=O<?i0(nh51b9jg6<722ch87>5;ha6>5<<g8=j6=44}c1:4?6=<3:1<v*>8`825g=O<><0D98l;%ae>7d<aj91<75fc583>>od=3:17b?8a;29?xd5j;0;684?:1y'5=g=98o0D999;I65g>"dn38=7dm<:188mf2=831bo84?::k`2?6=3f;<m7>5;|`0=4<72<0;6=u+19c954c<@===7E:9c:&`b?4d3`i86=44ib694?=nk<0;66gl6;29?j70i3:17pl=b583>1<729q/=5o510`8L1113A>=o6*lf;10?le42900en:50;9jg0<722e:;l4?::a7f6=8391<7>t$0:b>47>3A><:6F;6b9'gc<5=2ch?7>5;ha7>5<<g8=j6=44}c1`6?6=<3:1<v*>8`825g=O<><0D98l;%ae>7d<aj91<75fc583>>od=3:17b?8a;29?xd4k=0;684?:1y'5=g=98o0D999;I65g>"dn38h7dm<:188mf2=831bo84?::k`2?6=3f;<m7>5;|`1f<<72<0;6=u+19c954c<@===7E:9c:&`b?073`i86=44ib694?=nk<0;66gl6;29?j70i3:17pl=bc83>0<729q/=5o510g8L1113A>=o6*lf;1:?le42900en:50;9jg0<722ch:7>5;n34e?6=3th9nl4?:483>5}#91k1=<k4H555?M21k2.hj7l<;ha0>5<<aj>1<75fc483>>od>3:17b?8a;29?xd5jj0;684?:1y'5=g=98o0D999;I65g>"dn3<;7dm<:188mf2=831bo84?::k`2?6=3f;<m7>5;|`1f`<72<0;6=u+19c954c<@===7E:9c:&`b?073`i86=44ib694?=nk<0;66gl6;29?j70i3:17pl=c883>1<729q/=5o510`8L1113A>=o6*lf;48mf5=831bo94?::k`1?6=3f;<m7>5;|`0<f<72<0;6=u+19c954c<@===7E:9c:&`b?553`i86=44ib694?=nk<0;66gl6;29?j70i3:17pl<2083>7<729q/=5o510:8L1113A>=o6*lf;3b?le42900c<9n:188yg56n3:1>7>50z&2<d<6911C8:84H54`?!ea28k0en=50;9l52g=831vn>?k:181>5<7s-;3m7?>8:J733=O<?i0(nh51`9jg6<722e:;l4?::a74d=8381<7>t$0:b>47?3A><:6F;6b9'gc<6i2ch?7>5;n34e?6=3th8=44?:383>5}#91k1=<64H555?M21k2.hj7?n;ha0>5<<g8=j6=44}c123?6=:3:1<v*>8`825==O<><0D98l;%ae>4g<aj91<75`16c94?=zj:;>6=4=:183!7?i3;:46F;779K03e<,jl1=l5fc283>>i6?h0;66sm30194?4=83:p(<6n:03;?M20>2B?:n5+cg82e>od;3:17b?8a;29?xd4980;6?4?:1y'5=g=9820D999;I65g>"dn3;j7dm<:188k41f2900qo=j5;296?6=8r.:4l4>199K020<@=<h7)mi:0c8mf5=831d=:o50;9~f6c429096=4?{%3;e?7602B?;;5G47a8 f`=9h1bo>4?::m23d<722wi?h?50;094?6|,82j6<?7;I642>N3>j1/ok4>a:k`7?6=3f;<m7>5;|`0`c<72;0;6=u+19c954><@===7E:9c:&`b?7f3`i86=44o05b>5<<uk9oh7>52;294~"60h0:=55G4648L10d3-im6<o4ib194?=h9>k1<75rb2fa>5<5290;w)?7a;32<>N3??1C8;m4$bd95d=nk:0;66a>7`83>>{e;m31<7<50;2x 4>f28;37E:86:J72f=#ko0:m6gl3;29?j70i3:17pl<d683>7<729q/=5o510:8L1113A>=o6*lf;3b?le42900c<9n:188yg5c=3:1>7>50z&2<d<6911C8:84H54`?!ea28k0en=50;9l52g=831vn><l:181>5<7s-;3m7?>8:J733=O<?i0(nh51`9jg6<722e:;l4?::a7c6=8381<7>t$0:b>47?3A><:6F;6b9'gc<6i2ch?7>5;n34e?6=3th9o>4?:483>5}#91k1=<k4H555?M21k2.hj7==;ha0>5<<aj>1<75fc483>>od>3:17b?8a;29?xd5jm0;684?:1y'5=g=98o0D999;I65g>"dn3hn7dm<:188mf2=831bo84?::k`2?6=3f;<m7>5;|`1ef<72<0;6=u+19c954c<@===7E:9c:&`b?553`i86=44ib694?=nk<0;66gl6;29?j70i3:17pl=b983>0<729q/=5o510g8L1113A>=o6*lf;0e?le42900en:50;9jg0<722ch:7>5;n34e?6=3th9ol4?:483>5}#91k1=<k4H555?M21k2.hj7==;ha0>5<<aj>1<75fc483>>od>3:17b?8a;29?xd5jo0;684?:1y'5=g=98o0D999;I65g>"dn3997dm<:188mf2=831bo84?::k`2?6=3f;<m7>5;|`1g=<72<0;6=u+19c954c<@===7E:9c:&`b?d33`i86=44ib694?=nk<0;66gl6;29?j70i3:17pl<8c83>6<729q/=5o510;8L1113A>=o6*lf;13?le42900en:50;9l52g=831vn>m9:186>5<7s-;3m7?>e:J733=O<?i0(nh52b9jg6<722ch87>5;ha6>5<<aj<1<75`16c94?=zj:i<6=4::183!7?i3;:i6F;779K03e<,jl1>n5fc283>>od<3:17dm::188mf0=831d=:o50;9~f7e1290>6=4?{%3;e?76m2B?;;5G47a8 f`=;11bo>4?::k`0?6=3`i>6=44ib494?=h9>k1<75rb3a3>5<2290;w)?7a;32a>N3??1C8;m4$bd96c=nk:0;66gl4;29?le22900en850;9l52g=831vn>6n:186>5<7s-;3m7?>e:J733=O<?i0(nh5339jg6<722ch87>5;ha6>5<<aj<1<75`16c94?=zj:2n6=4=:183!7?i3;:>6F;779K03e<aj81<75`16c94?=zj=?:6=494;294~"60h0:4?5G4648L10d3S?86lu6:`820?7228n1=h4>6;3e>41=:90v(<>j:59'55`=<2.h;7:4$b:90>"d13>0(no54:&`f?2<,ji186*>8780?!7??390(i>54:&g5?2<,m8186*k3;68 a2=<2.o97:4$e490>"c?3>0(i654:&g=?2<,mk186*kb;68 ae=<2.oh7:4$eg90>"cn3>0(h>54:&f5?2<,l8186*j3;68 `2=<2.n97:4$d490>"b?3>0(h654:&f=?2<,lk186*jb;68 `e=<2.nh7:4$dg90>"bn3>0(k>54:&e5?2<,o8186*i3;68 c2=<2.m97:4$g490>"a?3>0(k654:&e=?2<,ok186*ib;68 ce=<2.mh7:4$gg90>"an3>0(<>?:59'557=<2.:<?4;;%337?2<,8:?695+11790>"68?0?7)??7;68 46?2=1/==754:&24d<33-;;n7:4$02`>1=#99n186*;728734=#km0?7)?74;34=>"699087)?>1;18 1152==:7)mj:59j1<<722c>m7>5;h`6>5<<ak<1<75f19:94?=n9131<75f47d94?=n<>:1<75f4583>!70n3>87c?8e;28?l25290/=:h5429m52c=921b8<4?:%34b?243g;<i7<4;h63>5<#9>l18>5a16g97>=n;o0;6)?8f;60?k70m3>07d=j:18'52`=<:1e=:k55:9j7a<72-;<j7:<;o34a?0<3`9h6=4+16d906=i9>o1;65f3c83>!70n3>87c?8e;:8?l5f290/=:h5429m52c=121b8k4?:%34b?2b3g;<i7>4;h6g>5<#9>l18h5a16g95>=n<j0;6)?8f;6f?k70m3807d:m:18'52`=<l1e=:k53:9j0d<72-;<j7:j;o34a?2<3`>26=4+16d90`=i9>o1965f4983>!70n3>n7c?8e;48?l20290/=:h54d9m52c=?21b8;4?:%34b?2b3g;<i764;h66>5<#9>l18h5a16g9=>=n>00;6)?8f;4;?k70m3:07d88:18'52`=>11e=:k51:9j23<72-;<j787;o34a?4<3`<>6=4+16d92==i9>o1?65f6583>!70n3<37c?8e;68?l04290/=:h5699m52c==21b;?4?:%34b?0?3g;<i784;h52>5<#9>l1:55a16g93>=n?90;6)?8f;4;?k70m3207d8i:18'52`=>11e=:k59:9j2`<72-;<j787;o34a?g<3`<o6=4+16d92==i9>o1n65f6b83>!70n3<37c?8e;a8?l0e290/=:h5699m52c=l21b:l4?:%34b?0?3g;<i7k4;h41>5<#9>l1:55a16g9b>=n?h0;6)?8f;5:?k70m3:07d97:18'52`=?01e=:k51:9j32<72-;<j796;o34a?4<3`==6=4+16d93<=i9>o1?65f7483>!70n3=27c?8e;68?l13290/=:h5789m52c==21b4>4?:%34b?1>3g;<i784;h:1>5<#9>l1;45a16g93>=n080;6)?8f;5:?k70m3207d6?:18'52`=?01e=:k59:9j3c<72-;<j796;o34a?g<3`=n6=4+16d93<=i9>o1n65f7e83>!70n3=27c?8e;a8?l1d290/=:h5789m52c=l21b;o4?:%34b?1>3g;<i7k4;h50>5<#9>l1;45a16g9b>=n0?0;6)?8f;:6?k70m3:07d6;:18'52`=0<1e=:k51:9j<<<72-;<j767;o34a?6<3`2<6=4+16d9<==i9>o1=65`9083>!70n33;7c?8e;28?j>a290/=:h5919m52c=921d4h4?:%34b??73g;<i7<4;n:g>5<#9>l15=5a16g97>=h0j0;6)?8f;;3?k70m3>07b6m:18'52`=191e=:k55:9l=d<72-;<j77?;o34a?0<3f326=4+16d9=5=i9>o1;65`9983>!70n33;7c?8e;:8?j?0290/=:h5919m52c=121d5;4?:%34b??73g;<i7o4;n;6>5<#9>l15=5a16g9f>=h1=0;6)?8f;;3?k70m3i07b7<:18'52`=191e=:k5d:9l=7<72-;<j77?;o34a?c<3f2j6=4+16d9=5=i9>o1j65`ad83>!70n3ko7c?8e;28?jgd290/=:h5ae9m52c=921dm?4?:%34b?g63g;<i7>4;nc3>5<#9>l1m<5a16g95>=h1o0;6)?8f;c2?k70m3807b7j:18'52`=i81e=:k53:9l=a<72-;<j7o>;o34a?2<3f3h6=4+16d9e4=i9>o1965`ac83>!70n3k:7c?8e;48?jgf290/=:h5a09m52c=?21dm44?:%34b?g63g;<i764;nc;>5<#9>l1m<5a16g9=>=hi>0;6)?8f;c2?k70m3k07bo9:18'52`=i81e=:k5b:9le0<72-;<j7o>;o34a?e<3fk?6=4+16d9e4=i9>o1h65`a283>!70n3k:7c?8e;g8?j?e290/=:h5a09m52c=n21dn<4?:%34b?d73g;<i7>4;nce>5<#9>l1n=5a16g95>=zj;in6=4;:183!7?i3;:m6F;779K03e<,jl1>85fc283>>od<3:17b?>5;29?j70i3:17pl=b483>0<729q/=5o510a8L1113A>=o6*lf;0f?le42900en:50;9jg0<722e:=84?::m23d<722wi>nl50;794?6|,82j6<?l;I642>N3>j1/ok4<1:k`7?6=3`i?6=44ib794?=h98?1<75`16c94?=zj;h=6=49:183!7?i3;:j6F;779K03e<,jl1=o5fc283>>od<3:17dm::188mf0=831d=<;50;9l52g=831vn?m;:187>5<7s-;3m7?>d:J733=O<?i0(nh5309jg6<722ch87>5;ha6>5<<g8;>6=44}c0`1?6==3:1<v*>8`8265=O<><0D98l;%ae>64<aj91<75fc583>>od=3:17dm9:188k4722900qo=l8;291?6=8r.:4l4>1b9K020<@=<h7)mi:238mf5=831bo94?::k`1?6=3f;:97>5;n34e?6=3th9o<4?:483>5}#91k1=?>4H555?M21k2.hj7==;ha0>5<<aj>1<75fc483>>od>3:17b?>5;29?xd5k>0;6;4?:1y'5=g=98l0D999;I65g>"dn3?0en=50;9jg1<722ch97>5;ha5>5<<g8;>6=44o05b>5<<uz??>7>56z\607=::m;1o8522e:9g3=::m>1o;522bf9g0=::ji1o85rs5:f>5<1:rT?5=5Q46d8Z02f3W??46P;7d9]113<V=o>7S;;9:\7a3=Y=920R96:;_6;`>X30j1U85l4^5:b?[2?12T?455Q4958Z1>13W>386P;829>021=k9168;<55g9>001==o168;?55g9>036==o1688h55g9>03g==o168;755g9>6<c=91:01?7i:0:3?84f93;3<63=a382<5=::h91=5>4=3c7>4>7348j97?70:?1e3<60916>l95192897g?282;70<n0;3;4>;5m;0==63=e0855>;5m90==63=dg855>;5ll0==63=f4855>;5n=0==63=f2855>;5n;0==63=f0855>;4=m0==63<5b855>;4=k0==63<5`855>;4=00==63<71855>;4>o0==63<6d855>;4>m0==63<6b855>;4:90==63<1d855>;49j0==63<1`855>;4910==63<17855>;49=0==63<13855>;4990==63<e5855>;4m;0==63<e1855>;4ll0==63<db855>;4lh0==63<d9855>;4l?0==63<d5855>;3=80:45524439026<5=?:6:o4=572>2><5=?:6:94=572>20<5=?:6:;4=572>22<5=?:65=4=572>=4<5=?:65?4=572>=6<5=?:6:h4=572>2c<5=?:6:j4=572>2e<5=?:6:l4=572>25<5=?:6574=572>=1<uz??87>53z\601=:<?81=5>4=574>4>73ty?hn4?:3y]0ae<5;n=6<6>;|q626<72:qU9;=4=2a:>f2<5:2;6n;4}r71e?6=>>qU9?o4=57:>02<5=?368:4=574>02<5=<:68:4=543>02<5=?m68:4=221>02<5;3n68:4=3;e>02<5;k:68:4=3c1>02<5;k868:4=3c7>02<5;k>68:4=3c5>02<5;k<68:4=3c;>02<5;k;68:4=33g>02<5;;h68:4=33a>02<5;;j68:4=33:>02<5;;368:4=334>02<5;;=68:4=336>02<5;;?68:4=34g>02<5;<h68:4=34a>02<5;<j68:4=34:>02<5;<368:4=344>02<5;<=68:4=346>02<5;<?68:4=37:>02<5;?368:4=374>02<5;?=68:4=376>02<5;??68:4=370>02<5;?968:4=372>02<5;?;68:4=0f;>02<58n<68:4=0f5>02<58n>68:4=0f7>02<58n868:4=0f1>02<58n:68:4=0f3>02<58im68:4=263>02<5:9m68:4=21g>02<5:9h68:4=21f>02<5:9i68:4=21b>02<5:9368:4=214>02<5:9268:4=277>02<5:?868:4=271>02<5:?:68:4=273>02<5:>m68:4=26f>02<5:>o68:4=26`>02<5:>i68:4=3f1>02<5;im68:4=3f:>02<5;n=68:4=3f6>02<5=9=68:4=516>02<5=9?68:4=510>02<5=9968:4=512>02<5=9;68:4=50e>02<5=9n68:4=51g>02<5=9h68:4=51a>02<5=9j68:4=51:>02<5=9368:4=514>02<5=8n68:4=50g>02<5=?:68o4}r6f6?6=:rT?i?5236g95=7<uz??n7>55`y]11d<5=<?68:4=541>02<5=<868:4=54b>02<5=<268:4=25f>02<5:=o68:4=2`3>02<5:h:68:4=2`0>02<5:h?68:4=2`6>02<5:h=68:4=2`4>02<5:h368:4=2`:>02<5:hj68:4=2`1>02<58h;68:4=0ce>02<58kn68:4=0cg>02<58kh68:4=0ca>02<58kj68:4=0c:>02<58k368:4=0c4>02<5;:;68:4=0de>02<58ln68:4=0dg>02<58lh68:4=0da>02<58lj68:4=0d:>02<58l368:4=0d4>02<58oh68:4=0ga>02<58oj68:4=0g:>02<58o368:4=0g4>02<58o=68:4=0g6>02<58o?68:4=0g0>02<5;>>68:4=367>02<5;>868:4=361>02<5;>:68:4=363>02<5;9m68:4=31f>02<5;9o68:4=31`>02<5=:?68:4=520>02<5=::68:4=523>02<5=:968:4=2de>02<5:ln68:4=2d`>02<5:li68:4=2dg>02<5=;:68:4=52e>02<5=;;68:4=531>02<5=;868:4=535>02<5=;?68:4=536>02<5=;<68:4=53;>02<5=8h68:4=50a>02<5=8j68:4=50:>02<5=8368:4=504>02<5=8=68:4=506>02<5=8?68:4=500>02<5=?:6874}r76=?6=:rT>8h523c095=7<uz?=>7>52z\613=:;kk1=5?4}r755?6=:rT>98523c;95=7<uz?=<7>52z\611=:;k21=5?4}r76b?6=:rT>9>523c595=7<uz?>i7>52z\617=:;k<1=5?4}r76`?6=:rT>9<523c795=7<uz?>o7>52z\615=:;k>1=5?4}r76f?6=:rT>8k523c195=7<uz?>m7>52z\60a=:;k;1=5?4}r763?6=:rT>8n523c295=7<uz>o=7>52z\7fc=:<:<1=5?4}r6`b?6=:rT?nh5242795=7<uz>hi7>52z\7fa=:<:>1=5?4}r6``?6=:rT?nn5242195=7<uz>ho7>52z\7fg=:<:81=5?4}r6`f?6=:rT?nl5242395=7<uz>hm7>52z\7f<=:<::1=5?4}r6`=?6=:rT?n55243d95=7<uz>om7>52z\7g2=:<:o1=5?4}r6g=?6=:rT?o;5242f95=7<uz>o47>52z\7g0=:<:i1=5?4}r6g3?6=:rT?o95242`95=7<uz>o:7>52z\7g6=:<:k1=5?4}r6g1?6=:rT?o?5242;95=7<uz>o87>52z\7g4=:<:21=5?4}r6g7?6=:rT?o=5242595=7<uz>o>7>52z\7f2=:<;o1=5?4}r6`<?6=:rT?n;5243f95=7<uz?847>52z\66a=::h:1=5?4}r775?6=:rT>?8522`:95=7<uz??<7>52z\671=::h=1=5?4}r70b?6=:rT>?>522`495=7<uz?8i7>52z\677=::h?1=5?4}r70`?6=:rT>?<522`695=7<uz?8o7>52z\675=::h91=5?4}r70f?6=:rT>>k522`095=7<uz?8m7>52z\66`=::h;1=5?4}r70=?6=:rT>>n5228d95=7<uz?8:7>52z\66g=::0o1=5?4}r6bg?6=:rT?5l524439<3=z{=kj6=4={_6:=>;3=80=56s|4`;94?4|V=3370::1;44?xu3i10;6?uQ485891362?<0q~:n7;296~X31?1688?5649~w1g12909wS:65:?714<1<2wx8l;50;0xZ1?334>>=78<;|q7e1<72;qU84=4=572>24<uz>i97>52z\7e7=:<<;1;<5rs5`7>5<5sW>j=63;508;0>{t<k91<7<t^5c3?82293=;7p};b383>7}Y<0l019;>:7d8yv2e93:1>vP;9d9>007=>l1v9l?:181[2>l27?9<49d:p0d`=838pR97l;<665?0d3ty?mh4?:3y]0<d<5=?:6;l4}r6b`?6=:rT?5?5244392d=z{=k86=4={_6:5>;3=80=>6s|13794?c|5==36<9l;<0;4?3?3482?7;7;<1:6?3?349j97;7;<0ga?3?348m=7;7;<16=?3?349=o7;7;<116?3?349:<7;7;<1f2?3?349o87;7;<665?d23ty?954?:2y>00?==o168865193891302<<0q~::9;296~;3=00:4<5244`9g6=z{=<86=4<{<650?3a34>=>7;9;<657?7?92wx8;:50;0x9103282:70:96;a0?xu3=>0;6>u244:91c=:<<=1=5?4=57a>f2<uz>=>7>53z?727<608168;=55g9>030=k=1v9;n:18782193;3<63;6182<5=:<<l1=5>4=57a>41f3ty?9h4?:3;x9106282:70=?2;3;4>;51l0>n63=9g86f>;5i80>n63=a386f>;5i:0>n63=a586f>;5i<0>n63=a786f>;5i>0>n63=a986f>;5i90>n63<4186f>;4;o0>n63<3e86f>;4;j0>n63<3d86f>;4;k0>n63<3`86f>;4;10>n63<3682<5=:;:319o5234691g=:;<919o5234091g=:;<;19o5234291g=:;=l19o5235g91g=:;=n19o5235a91g=:;=h19o522e091g=::jl19o522e;91g=::m<1=5>4=3f6>4>7348jm7m;;<0a2?e3348h;7m<;|q71a<72;3p198?:0:2?846l3?i70<>c;7a?846j3?i70<>a;7a?84613?i70<>8;7a?846?3?i70<>6;7a?846=3?i70<>4;7a?841l3?i70<9c;7a?841j3?i70<9a;7a?84113?i70<98;7a?841?3?i70<96;7a?841=3?i70<94;7a?84213?i70<:8;7a?842?3?i70<:6;7a?842=3?i70<:4;7a?842;3?i70<:2;7a?84293?i70<:0;7a?87c03?i70?k7;7a?87c>3?i70?k5;7a?87c<3?i70?k3;7a?87c:3?i70?k1;7a?87c83?i70?lf;7a?xu3=j0;6<;t=57e>4>634>8:7;m;<601?3e34>887;m;<607?3e34>8>7;m;<605?3e34>8<7;m;<61b?3e34>8i7;m;<60`?3e34>8o7;m;<60f?3e34>8m7;m;<60=?3e34>847;m;<603?3e34>9i7;m;<61`?3e34>>?7m;;<665?7?12wx8;;50;1x910f282;70:99;3;4>;3>?0:;l5rs54;>5<5kr7?:l4>809>72c=91:01>9k:0:3?85e83?i70=m1;7a?85e;3?i70=m4;7a?85e=3?i70=m6;7a?85e?3?i70=m8;7a?85e13?i70=ma;7a?85e:3?i70:?4;7a?827;3?i70:?1;7a?82783?i70:?2;7a?85an3?i70=ie;7a?85ak3;3<63<fc86f>;4nm0>n63;1086f>;38o0:4=5240291g=:<8819o5240191g=:<8<19o5240691g=:<8?19o5240591g=:<8219o5243a91g=:<;h19o5243c91g=:<;319o5243:91g=:<;=19o5243491g=:<;?19o5243691g=:<;919o5rs544>5<51r7?:44>809>5g6==k16=lh55c9>5dc==k16=lj55c9>5de==k16=ll55c9>5dg==k16=l755c9>5d>==k16=l955c9>656==k16=kh55c9>5cc==k16=kj55c9>5ce==k16=kl55c9>5cg==k16=k755c9>5c>==k16=k955c9>5`e==k16=hl55c9>5`g==k16=h755c9>5`>==k16=h955c9>5`0==k16=h;55c9>5`2==k16=h=55c9>613==k16>9:55c9>615==k16>9<55c9>617==k16>9>55c9>66`==k16>>k55c9>66b==k16>>m55c9~w6642909w0=?2;7e?857<3;<m6s|31094?5|5::96<6>;<0g0?e4348ho7m<;|q1e<<72;q6>4k55g9>6dg=9>k0q~<nd;296~;51o0>j63=ad823d=z{;km6=4={<0b5?3a348i<7?8a:p6g7=838p1?o=:4d897d528=j7p}=b283>7}::h919k522c6952g<uz8i;7>52z?1e1<2n279n44>7`9~w7df2909w0<n5;7e?84ei3;<m6s|2ca94?4|5;k=68h4=3``>41f3ty9nh4?:3y>6d1==o16>ok516c8yv4d:3:1>v3=a986b>;5k10:;l5rs3ca>5<5s48j<7;i;<0bg?70i2wx?:h50;1x961b2<l01>9k:4d896>728=j7p}<7e83>6}:;>n1=5?4=2a:>f5<5:2;6n:4}r1bb?6=:r78n=4:f:?0e0<6?h1v>lm:18185e93?m70=7e;34e>{t;ki1<7<t=2`0>0`<5:2m6<9n;|q0fa<72;q6?o:55g9>7<6=9>k0q~=me;296~;4j<0>j63<90823d=z{:hm6=4={<1a2?3a349h<7?8a:p7f7=838p1>l8:4d896e528=j7p}<c283>7}:;k219k523b6952g<uz9h97>52z?0f<<2n278o;4>7`9~w6e02909w0=ma;7e?85d?3;<m6s|39c94?4|5:h968h4=2:b>41f3ty9<l4?:4y>6=?=k:16>5>5609>642=91;01?hm:b4897c?2j<0q~=;1;291~;5000h863<4c82<4=:9091o9522d:9g0=:<<;1885rs3::>5<4s48357?8a:?1<5<60:16>4=51068yv4?83:1?v3=81823d=::1;1955228691==z{;3o6=4={<0:7?70i279ml4l6:p65d=83?p1?6n:b1897>62?;01??::0:2?84aj3i?70<j8;a7?xu4<;0;6;u229c9g1=:;=i1=5?4=0;0>f5<58396n:4=3g;>f5<5=?:6984}r0;e?6=;r794l4>7`9>6=7=91901?7;:037?xu5080;6>u2293952g<5;296864=3;6>0><uz8<j7>58z?1=1<6?h16>lk5c29>6g6=k<16>o<5c79>6g>=k:16>o;5c29>6g0=k?16>n?5c29~w76d290>w0<7b;a0?84?:3<:70<>6;3;5>;5nj0h:63=e88`2>{t;=91<78t=3:a>f2<5:>o6<6>;<3:6?e434;2=7m;;<0f=?e234>>=7:8;|q1<g<72:q6>5l516c897>5282870<65;320>{t:181<7=t=3:1>41f3483?7;7;<0:2?3?3ty9;o4?:8y>6<3=9>k01?l?:b6897d52j901?m<:b7897d?2j>01?l::b6897e32j901?m::b1897e62j>0q~<?d;291~;50j0h?63=82855>;59>0:4<522ga9g1=::l31o95rs267>5<1s483o7m;;<17a?7?927:5<4l3:?2=5<d<279i44l3:?714<302wx>5m50;1x97>d28=j70<73;3;7>;51?0:=95rs3:0>5<4s483?7?8a:?1<1<202795:4:8:p62e=832p1?79:05b?84e:3i?70<l3;a7?84e03i>70<m5;a6?84d<3i?70<l5;a7?84d93i>7p}=0d83>0}::1n1o>52296924=::821=5?4=3dg>f0<5;oj6n84}r171?6=>r794i4l4:?00c<60816=4>5c29>5=`=k=16>ho5c49>007=<01v?6k:18084?l3;<m63=8582<6=::0=1=<:4}r0;0?6=;r79494>7`9>6=3==116>465599~w71c2902w0<67;34e>;5j=0h863=bc8`1>;5k:0h?63=be8`1>;5j10h:63=c58`1>;5k<0h963=c08`2>{t:9l1<7;t=3:f>f5<5;2>6;?4=33:>4>6348mh7m;;<0fe?e33ty88;4?:7y>6=c=k=16?8>5193894>a2j901<6j:b6897cf2j9019;>:5c8yv4?m3:1?v3=8d823d=::1?1=5=4=3;;>4733ty9484?:2y>6=3=9>k01?69:4:897?>2<20q~<8e;29=~;5110:;l522c;9g6=::kh1o9522cc9g1=::kn1o9522bc9g1=::j:1o8522b`9g0=::j?1o;5rs333>5<2s483j7m<;<0;2?06348:m7?71:?1b`<d>279io4l6:p711=83<p1?6i:b689636282:70?7e;a0?87?l3i?70<jb;a6?82293>i7p}=8g83>6}::1l1=:o4=3:5>4>4348257?>4:p6=0=839p1?69:05b?84??3?370<6a;7;?xu5?>0;6:u228;952g<5;hj6n=4=3`g>f5<5;ij6n=4=3`e>f2<5;i;6n:4=3aa>f2<uz8:=7>55z?1=5<d;2794:491:?15g<60816>kk5c59>6`d=k=1v>:7:18584>83i?70=:2;3;5>;60m0h?63>8b8`0>;5mk0h?63;5087g>{t:0:1<7=t=3;3>41f3483;7?73:?1=d<69=1v?68:18084??3;<m63=8986<>;51k0>46s|26:94?0|5;3j6<9n;<0ag?e4348h57m<;<0ab?e4348h<7m<;<0`f?e43ty9=?4?:4y>6<7=k:16>565609>64e=91;01?hi:b4897cd2j<0q~=;9;292~;5180h863<5282<4=:91i1o>5219`9g1=::li1o85244390a=z{;3:6=4<{<0:5?70i279454>829>6<d=98>0q~<78;296~;5010:;l5228a91==z{;=26=4:{<0:f?70i279nh4l3:?1g<<d<279mn4l3:?1g3<d<2wx><=50;6x97?52j901??k:0:2?84an3i?70<jc;a7?xu4<h0;6;u22809g1=:9m219k5234695=7<582i6n=4=3g`>f5<5=?:69h4}r0:6?6=:r795?4>7`9>6<e=98>0q~<8a;290~;51j0:;l522b;9g0=::hi1o9522b:9g6=z{=;26=4:{<1:f?e43492>78>;<617?7?927:5n4l4:?714<4i2wx=4j50;6x96?e2j>01<o8:0:2?850>3i=70=93;a5?xu41k0;6>u238`952g<5:396<6<;<1b1?76<2wx?4<50;1x96?528=j70=63;7;?85f>3?37p}>9d83>1}:;0i1o>521`:95=7<5:==6n:4=240>f2<uz>:m7>56z?0=f<d<2785>491:?761<60816=4m5c29>5<d=k=1688?53c9~w6?d2908w0=6c;34e>;41:0:4>523`49542<uz92?7>53z?0=6<6?h16?4:5599>7d1==11v>66:18585f>3;<m63<8g8`0>;4190h963<908`2>;40j0h?63<8d8`6>{t90l1<7:t=2;g>f5<58k26<6>;<143?e1349=87m9;|q75g<72?q6?4j5c59>7<2=>8168?;5193894?e2j901<7n:b6891362:i0q~=6d;297~;41m0:;l5238695=5<5:k<6<?;;|q0=1<72:q6?4:516c896?22<201>o7:4:8yv5?=3:19v3<a6823d=:;1l1o>523829g6=:;0;1o>5239a9g1=z{8k;6=4;{<1:a?e434;jm7?71:?032<d<278:94l4:p04e=83<p1>7j:b6896?22?;019<9:0:2?87>i3i870?69;a7?822939o7p}<9d83>6}:;0o1=:o4=2;6>4>4349j47?>4:p7<3=839p1>7::05b?85>>3?370=n9;7;?xu40?0;69u23`:952g<5:3;6n:4=2;2>f3<5:2h6n;4}r3b5?6=<r785k4l3:?2eg<60816?:65c79>733=k?1v9?k:18585>n3i?70=66;42?825?3;3=63>988`7>;6110h863;5080a>{t;0l1<7=t=2;e>41f3492:7?73:?0e<<69=1v>79:18085>>3;<m63<9686<>;4ih0>46s|39594?5|5:k26<9n;<1:5?e33493o7m9;|q75`<72?q6?l>5c29>7<1=>8168?65193894??2j901<78:b6891362:l0q~?n2;290~;4i90h863>ab82<4=:;>21o9523779g1=z{:k;6=4<{<1b4?70i2785:4>829>7dg=98>0q~=67;297~;41>0:;l5238:91==:;hh1955rs2:;>5<1s49jm7?8a:?0g5<d;278o?4l3:?0g1<d;2784o4l3:?0g=<d;2wx8<h50;4x96g62j901>77:738914>282:70?67;a0?87>>3i?70::1;63?xu6i:0;69u23`39g1=:9hn1=5?4=25:>f0<5:<=6n84}r1b5?6=;r78m<4>7`9>7<>=91901>om:037?xu4110;6>u238:952g<5:326864=2c`>0><uz93=7>55z?0eg<6?h16?n<5c59>7f2=k<16?5l5c59>7f>=k=1v9<?:18585f:3i870=69;42?825i3;3=63>978`7>;61<0h863;50875>{t9h>1<7:t=2c1>f2<58kn6<6>;<14=?e3349=:7m;;|q0e7<72:q6?l<516c896?>282870=nc;320>{t;031<7=t=2;:>41f3492m7;7;<1b`?3?3ty84?4?:5y>7de=9>k01>m;:b6896e12j901>m7:b78yv2593:1:v3<a28`7>;41h0==63;2c82<4=:90?1o>521869g1=:<<;18?5rs0c6>5<3s49j?7m;;<3bb?7?9278;l4l6:?022<d>2wx?l=50;1x96g428=j70=6a;3;7>;4im0:=95rs2;b>5<5s492m7?8a:?0e`<202wx?5=50;6x96gc28=j70=l6;a7?85d?3i870=7a;a0?xu3:;0;68u23`69g6=::=?19k5243a95=7<583?6n=4=572>12<uz;j:7>54z?0e1<d<27:n=4>809>72g=k=16?;95c59~w6g32909w0=n4;34e>;4il0:=95rs2:7>5<4s49ji7?8a:?0g2<d<2784l4l4:p6ab=838p1?k=:4:897c628=j7p}=e683>7}::l81=5=4=3g`>41f3ty8<=4?:3y>6`4=9>k01>>;:b78yv4ck3:1>v3=e086<>;5m90:;l5rs3g5>5<5s48n=7?73:?1ag<6?h1v?jm:18184b83?370<kf;34e>{t:l?1<7<t=3g3>4>4348nm7?8a:p6ag=838p1?ji:4:897bb28=j7p}=e583>7}::ml1=5=4=3g:>41f3ty9i>4?:3y>6ac=91901?k7:05b?xu5n90;6?u22g791==::o>1=:o4}r0ee?6=:r79j84>829>6c`=9>k0q~=?1;296~;5n<0:;l523169g6=z{;om6=4={<0e0?3?348m?7?8a:p6c?=838p1?h;:0:0?84am3;<m6s|2dg94?4|5;l86864=3d1>41f3ty9j54?:3y>6c5=91901?hk:05b?xu5mm0;6?u22g091==::o;1=:o4}r0e3?6=:r79j?4>829>6ce=9>k0q~<i6;296~;5n80:4>522g`952g<uz9>47>52z?01a<202789n4>7`9~w6052909w0=:d;3;7>;4>>0:;l5rs25a>5<5s49>h7?8a:?0<5<d;2wx?8950;0x963d2<201>;m:05b?xu4>80;6?u234a95=5<5:<=6<9n;|q013<72;q6?8l5599>70g=9>k0q~=90;296~;4=k0:4>52377952g<uz9>97>52z?01d<20278944>7`9~w63a2909w0=:a;3;7>;4>=0:;l5rs27f>5<5s49>57?73:?026<6?h1v>8m:18185083?370=9f;34e>{t;>?1<7<t=253>4>4349<m7?8a:p72e=838p1>9?:05b?85?83i=7p}<6`83>7}:;?l1955237g952g<uz9<87>52z?02c<60:16?:7516c8yv5113:1>v3<6d86<>;4>m0:;l5rs250>5<5s49=i7?73:?03=<6?h1v>87:181851l3?370=9c;34e>{t;>81<7<t=24g>4>4349<;7?8a:p727=838p1>8l:0:0?850>3;<m6s|1g494?3|58h;68h4=323>4>634;i>7m;;<3a0?e434;i:7m:;|q2f4<72;q6=lh55g9>5g4=9>k0q~?m3;296~;6il0>j63>b5823d=z{8h>6=49{<3b`?3a34;i:7?8a:?2f=<d<27:nl4l3:?2ff<d=27:nh4l6:p5g1=838p1<ol:4d894d?28=j7p}>b883>7}:9hh19k521cc952g<uz;in7>52z?2ed<2n27:nn4>7`9~w4dc2909w0?n9;7e?87en3;<m6s|1b394?4|58k368h4=0a1>41f3ty:o>4?:3y>5d1==o16=n:516c8yv41;3:19v3=1e86b>;5>m0:4<5220d9g1=::;;1o>522319g0=z{;;n6=4={<02g?3a348:j7?8a:p676=838p1??m:4d8974628=j7p}=2383>3}::8k19k52231952g<5;8>6n:4=304>f5<5;826n;4=30a>f0<uz8987>52z?15<<2n279>84>7`9~w7412909w0<>8;7e?845?3;<m6s|23:94?4|5;;<68h4=30:>41f3ty9>l4?:3y>640==o16>?m516c8yv45m3:1>v3=1486b>;5:o0:;l5rs313>5<5s48:87;i;<005?70i2wx>9h50;0x970c2<l01?;6:0:2?xu5<l0;6?u227a91c=::<21=5?4}r056?6=<r79:n4>809>64`=k:16>??5c59>675=k?1v?:k:181841j3?m70<:7;3;5>{t:?;1<7=t=34a>4>63489=7m:;<017?e43ty98n4?:3y>63g==o16>8851938yv4183:1>v3=6`82<4=::;91o95rs36a>5<5s48=57;i;<061?7?92wx>8h50;7x970>282:70<=5;a0?845?3i?70<=9;a5?845j3i>7p}=4`83>7}::?219k5224695=7<uz8>i7>54z?12=<60816>?95c49>67?=k:16>?l5c59~w72>2909w0<97;7e?842;3;3=6s|24f94?5|5;<<6<6>;<01=?e33489n7m<;|q10=<72;q6>;855g9>604=91;0q~<:c;290~;5>?0:4<5223a9g6=::;l1o9522239g0=z{;><6=4={<051?3a348>=7?71:p60d=839p1?8::0:2?845n3i870<<1;a7?xu5<?0;6?u227691c=::<:1=5?4}r06e?6=:r79:94>809>667=k:1v<k=:18184783?m70?jc;3;5>{t9l;1<7<t=0de>0`<58oi6<6>;|q2b0<72=q6=kh5193894d52j901<l;:b6894d12j<0q~?j0;296~;6nl0>j63>e`82<4=z{8l?6=4<{<3ea?7?927:n94l5:?2f3<d;2wx=ih50;0x94`c2<l01<k6:0:2?xu6n:0;6?u21gf95=7<58h=6n:4}r3ga?6=:r7:jn4:f:?2a=<6081v<h=:18687ak3;3=63>b98`7>;6jh0h863>bb8`2>;6jl0h96s|1ef94?4|58li68h4=0g4>4>63ty:j<4?:5y>5cd=91;01<ln:b7894dd2j901<lj:b68yv7ck3:1>v3>f`86b>;6m?0:4<5rs0d3>5<4s4;mm7?71:?2ff<d<27:nh4l3:p5ad=838p1<h6:4d894c2282:7p}>eg83>1}:9o31=5?4=0`e>f5<58i96n:4=0a7>f3<uz;om7>52z?2b=<2n27:i94>809~w4cb2908w0?i8;3;5>;6k;0h?63>c58`0>{t9m31<7<t=0d4>0`<58o86<6>;|q2aa<72;q6=k95193894e32j90q~<<b;296~;5=00>j63=4482<4=z{;9j6=4={<06<?3a348?87?71:p66?=838p1?;8:4d89724282:7p}=3983>7}::<<19k5225095=7<uz88;7>52z?110<2n2798<4>809~w7512909w0<:4;7e?84383;3=6s|22794?4|5;?868h4=31e>4>63ty9?94?:3y>604==o16>>k51938yv44;3:1>v3=5086b>;5;m0:4<5rs311>5<5s48><7;i;<00g?7?92wx=nk50;0x94cd2<l01<j7:0:2?xu6km0;6?u21d`91c=:9m=1=5?4}r3`g?6=:r7:il4:f:?2`3<6081v<mm:18187b13?m70?k5;3;5>{t9jk1<7<t=0g;>0`<58n?6<6>;|q2g<<72;q6=h955g9>5a5=91;0q~?l8;296~;6m?0>j63>d382<4=z{8i<6=4={<3f1?3a34;o=7?71:p5f0=838p1<k;:4d894b7282:7p}>c483>7}:9l919k521bd95=7<uz8;=7>52z?2`2<2n27:4o4>7`9~w7652909w0?k6;7e?87?k3;<m6s|21194?4|58n>68h4=0:g>41f3ty9<94?:3y>5a2==o16=5k516c8yv47=3:1>v3>d286b>;60o0:;l5rs325>5<5s4;o>7;i;<3:4?70i2wx>=950;0x94b62<l01<7>:05b?xu5810;6?u21e291c=:9081=:o4}r03=?6=:r7:ok4:f:?2=6<6?h1v?8j:181843<3?m70?64;34e>{t:?l1<7<t=360>0`<583>6<9n;|q135<72;q6>9<55g9>5<0=9>k0q~<81;296~;5<80>j63>96823d=z{;=96=4={<074?3a34;247?8a:p625=838p1?=i:4d894?>28=j7p}=7583>7}:::o19k5218c952g<uz8<97>52z?17a<2n27:5o4>7`9~w7112909w0<<c;7e?87>k3;<m6s|44694?70s49?<7;9;<10b?313498h7;9;<10g?313498i7;9;<10f?313498m7;9;<10<?313498;7;9;<10=?31349>87;9;<167?31349>>7;9;<165?31349><7;9;<17b?31349?i7;9;<17`?31349?o7;9;<17f?31348ho7?8a:?716<d;278<94l4:p75`=838p1>:?:4d8964e28=j7p}<3783>1}:;=:1=5?4=277>0`<5;lm6n=4=20`>f5<uz9;i7>52z?07c<2n278>l4>7`9~w652290?w0=<f;3;5>;4=:0>j63=fg8`1>;4:80h?6s|31a94?4|5:9o68h4=20;>41f3ty8?>4?:5y>76b=91;01>;>:4d897`b2j?01>?k:b18yv57j3:1>v3<3b86b>;4:>0:;l5rs211>5<3s498o7?71:?015<2n279ji4l3:?05g<d;2wx?=j50;0x965b2<l01><6:05b?xu4;=0;69u232g95=7<5:?968h4=3df>f5<5:;m6n=4}r13e?6=:r78?o4:f:?063<6?h1v>=>:187854j3;3=63<4g86b>;5nm0h963<188`7>{t;931<7<t=21b>0`<5:8>6<9n;|q075<72=q6?>o51938962b2<l01?hl:b1896702j90q~=?7;296~;4;10>j63<22823d=z{:8n6=4;{<10<?7?92788n4:f:?1bg<d;278=>4l3:p750=838p1>=8:4d8964528=j7p}<2e83>1}:;:=1=5?4=26a>0`<5;li6n;4=232>f5<uz9;47>52z?07<<2n278>94>7`9~w64a290?w0=<9;3;5>;4<m0>j63=fb8`1>;49<0h?6s|33294?4|5:8i6864=203>41f3ty8>n4?:3y>77d=98>01><l:05b?xu49l0;6>u233c91==:;;:1955230g952g<uz99=7>53z?06d<69=16??>51918964628=j7p}<1b83>6}:;;31955230g91==:;8i1=:o4}r12b?6=;r78>44>159>74c=91901>?i:05b?xu49h0;6>u233:91==:;8i1955230c952g<uz9:h7>53z?06=<69=16?<m51918967c28=j7p}<1983>6}:;;=1955230c91==:;821=:o4}r12f?6=;r78>:4>159>74g=91901>?m:05b?xu49?0;6>u233491==:;8219552304952g<uz9:57>53z?063<69=16?<651918967>28=j7p}<1583>6}:;;?1955230491==:;8>1=:o4}r123?6=;r78>84>159>740=91901>?8:05b?xu49;0;6>u233691==:;8>19552300952g<uz9:97>53z?061<69=16?<:51918967228=j7p}<1183>6}:;;91955230091==:;8:1=:o4}r127?6=;r78>>4>159>744=91901>?<:05b?xu4980;6>u23309542<5:;;6<6<;<125?70i2wx>i=50;0x97b52<l01?j;:05b?xu5l;0;65u22e095=7<5;n:6n:4=3f;>f3<5;n?6n;4=3ag>f5<5;ih6n:4=3af>f2<5;i<6n84}r0g4?6=;r79ok4:f:?1`<<2n279h<4>7`9~w7ea2903w0<lf;3;5>;5l80h?63=d98`0>;5l=0h863=ce8`0>;5kj0h:63=cd8`7>;5k>0h96s|2e;94?2|5;n26<6>;<0be?e2348i:7m<;<0`3?e33ty9h:4?:2y>6a0==o16>i;55g9>6a>=9>k0q~<k5;296~;5l<0:4<522e:9g6=z{=?=6=4=0z?741<2>27?<>4:6:?744<2>27?<=4:6:?747<2>278jk4:6:?0b`<2>278jn4:6:?0bg<2>278ji4:6:?754<2>27?<k4:6:?755<2>27?=?4:6:?756<2>27?=;4:6:?751<2>27?=84:6:?752<2>27?=54:6:?76f<2>27?>o4:6:?76d<2>27?>44:6:?76=<2>27?>:4:6:?763<2>27?>84:6:?761<2>27?>>4:6:?0g<<6?h1688?547d8yv5c;3:1>v3;0586b>;4mo0:;l5rs2db>5<3s4>;87?71:?75=<2n278;l4l3:?0b5<d;2wx?i<50;0x91642<l01>kj:05b?xu4n00;69u241195=7<5=;<68h4=25b>f3<5:o>6n=4}r1g4?6=:r7?<<4:f:?0af<6?h1v>h8:18782793;3=63;1486b>;4?00h963<e08`7>{t;jl1<7<t=523>0`<5:oi6<9n;|q0b3<72=q68=>5193891732<l01>97:b1896ba2j90q~=k1;296~;38;0>j63<ee823d=z{:l36=4;{<636?7?927?=;4:f:?03<<d;278i>4l3:p7fc=838p1>hi:4d896cf28=j7p}<f483>1}:;ol1=5?4=530>0`<5:=36n;4=2fg>f5<uz9hh7>52z?0b`<2n278i44>7`9~w6`3290?w0=ie;3;5>;39;0>j63<768`7>;4lk0h?6s|3b`94?4|5:lh68h4=2g4>41f3ty8j?4?:5y>7ce=91;019??:4d896112j901>j8:b18yv5di3:1>v3<fc86b>;4m?0:;l5rs2d2>5<3s49mn7?71:?74c<2n278;;4l5:?0`0<d;2wx?nm50;0x96`c2<l01>k7:05b?xu4n:0;69u23gf95=7<5=;:68h4=254>f3<5:n26n=4}r1f0?6=:r78ik4:8:?0a1<6?h1v>h?:18185bn3;:863<f1823d=z{:o96=4<{<1fa?3?349n87;7;<1f6?70i2wx?h;50;1x96cb28;?70=j4;3;7>;4m<0:;l5rs2g3>5<4s49nh7;7;<1f6?3?349n<7?8a:p7`5=839p1>kk:037?85b:3;3?63<e2823d=z{:nn6=4<{<1fg?3?349n<7;7;<1ga?70i2wx?h?50;1x96cd28;?70=j0;3;7>;4m80:;l5rs2f`>5<4s49nn7;7;<1ga?3?349oo7?8a:p7a`=839p1>km:037?85cm3;3?63<dg823d=z{:nj6=4<{<1fe?3?349oo7;7;<1ge?70i2wx?ij50;1x96cf28;?70=kc;3;7>;4lm0:;l5rs2f;>5<4s49n57;7;<1ge?3?349o47?8a:p7ad=839p1>k6:037?85ci3;3?63<dc823d=z{:n=6=4<{<1f<?3?349o47;7;<1g2?70i2wx?i750;1x96c?28;?70=k8;3;7>;4l00:;l5rs2f7>5<4s49n;7;7;<1g2?3?349o87?8a:p7a1=839p1>k8:037?85c>3;3?63<d6823d=z{:n>6=4<{<1f2?76<278h94>829>7a3=9>k0q~:?7;297~;3980:4<5243791c=:;?>1o85rs526>5<4s4>;j7?71:?766<2n278:>4l5:p050=839p19??:0:2?825<3?m70=93;a0?xu3810;6>u240095=7<5=8=68h4=247>f5<uz>;57>53z?756<608168?955g9>733=k<1v9>l:180826>3;3=63;2`86b>;4>?0h?6s|41c94?5|5=;?6<6>;<61<?3a349=97m<;|q74g<72:q68<;51938914>2<l01>89:b78yv27l3:1?v3;1682<4=:<;h19k523759g0=z{=:n6=4<{<62<?7?927?>n4:f:?022<d;2wx88;50;30824>3?=70:<5;75?824<3?=70:<3;75?824:3?=70:<1;75?82483?=70:=f;75?824m3?=70:<d;75?824k3?=70:<b;75?824i3?=70:<9;75?82403?=70:<7;75?825m3?=70:=d;75?84dl3;<m6s|45594?4|5=9=68h4=572>g7<uz>?:7>52z?770<2n27?9<4n2:p013=838p19=;:4d891362h:0q~:;4;296~;3;:0>j63;508:b>{t<=91<7<t=511>0`<5=?:64k4}r676?6=:r7??<4:f:?714<>l2wx89?50;0x91572<l019;>:8a8yv2383:1>v3;2g86b>;3=80jn6s|44294?4|5=9n68h4=572>dg<uz>?j7>52z?77a<2n27?9<4nf:p01c=838p19=l:4d891362h30q~:;d;296~;3;k0>j63;508b<>{t<=i1<7<t=51b>0`<5=?:6l94}r67f?6=:r7??44:f:?714<f>2wx89o50;0x915?2<l019;>:`78yv2313:1>v3;3686b>;3=80j86s|45:94?4|5=8n68h4=572>d5<uz>8j7>52z?76a<2n27?9<46b:p004=838p19;<:05b?82293h=7p}>6483>7}::hk1o>522bg9543<uz89h7>54z?16f<d<279>k4l5:?174<d>279>o4>7`9~w4e7290?w0?mf;a7?87d:3i>70?l4;a5?87em3;<m6s|17194??|5;kn6n:4=3`3>f5<5;h96n;4=3`7>f5<5;h26n;4=3``>f2<5;hn6n:4=3a5>f5<5;i<6<9n;|q22=<72:q6>o:5c49>6gd=k?16>o;516c8yv5?l3:1;v3<c18`0>;4k;0h963<c58`2>;40j0:;l523b49g0=:;j=1o85239c9g0=z{8<i6=4<{<0a=?e3348i47?8a:?1g3<d=2wx=;?50;6x97d>2j<01?ln:b7897e428=j70<nc;a5?xu6>j0;6?u22c`9g6=::j=1=<;4}r36e?6=:r79no4>7`9>6gg=k?1v<8k:18184ek3i>70<md;34e>{t9?>1<7=t=3``>f0<5;ij6<9n;<0`<?e23ty::k4?:3y>6gc=k<16>n>516c8yv71m3:1>v3=bd8`2>;5jo0:;l5rs3a:>5<5s48h57?8a:?1g=<d<2wx=;750;0x97e42j<01?l9:036?xu6>?0;6?u22cf9g3=::k?1=<;4}r30a?6=:r79mn4l5:?1gg<6?h1v<<l:18084di3i>70<mf;a6?84e>3;<m6s|14594?4|5;ij6n84=3a7>4723ty:944?:3y>6g`=k?16>n;51078yv72k3:1>v3=c98`2>;5k?0:;l5rs07e>5<5s493n7?8a:?0g3<d>2wx=;>50;0x96e02j<01>m7:05b?xu6>>0;6?u22b49g3=::jh1=<;4}r356?6=:r79o=4l6:?1g4<69<1v<8n:18185?i3i=70=l8;321>{t;9?1<7<t=3af>41f348i:7m:;|p0de=838pR97n;<71>1?f3->=n7?9e:p0dg=838pR976;<71>1?>3->=n7?9f:p0d?=838pR977;<71>1??3->=n7?80:p0d>=838pR978;<71>1?03->=n7?85:p0d1=838pR979;<71>1?13->=n7?=6:p0d0=838pR97:;<71>1?23->=n7?=c:p0d3=838pR97;;<71>1?33->=n7?<7:p0d2=838pR97<;<71>1?43->=n7?<e:p0g3=838pR9o=;<71>1g53->=n7?;9:p0g2=838pR9o>;<71>1g63->=n7?:2:p0g5=838pR9o?;<71>1g73->=n7?:6:p0g4=838pR97i;<71>1?a3->=n7?:7:p0g7=838pR97j;<71>1?b3->=n7?:8:p0g6=838pR97k;<71>1?c3->=n7?:9:p0d`=838pR97l;<71>1?d3->=n7?:b:p0dc=838pR97m;<71>1?e3->=n7?:c:p0db=838pR97=;<71>1?53->=n7?:d:p0d5=838pR97>;<71>1?63->=n7?:e:p17g=838pR8<n;<71>04f3->=n7?81:p114=838pR8:=;<71>0253->=n7?82:p112=838pR8:;;<71>0233->=n7?83:p11d=838pR8:m;<71>02e3->=n7?84:p135=838pR88<;<71>0043->=n7?86:p0a7=838pR9li;<71>1da3->=n7?=7:p0f`=838pR9lj;<71>1db3->=n7?=8:p0fc=838pR9lk;<71>1dc3->=n7?=9:p0fb=838pR9ll;<71>1dd3->=n7?=a:p0fe=838pR9lm;<71>1de3->=n7?=b:p0fd=838pR9ln;<71>1df3->=n7?=d:p0fg=838pR9l6;<71>1d>3->=n7?=e:p0f?=838pR9l7;<71>1d?3->=n7?=f:p0ag=838pR9m8;<71>1e03->=n7?<0:p0a?=838pR9m9;<71>1e13->=n7?<1:p0a>=838pR9m:;<71>1e23->=n7?<2:p0a1=838pR9m;;<71>1e33->=n7?<3:p0a0=838pR9m<;<71>1e43->=n7?<4:p0a3=838pR9m=;<71>1e53->=n7?<5:p0a2=838pR9m>;<71>1e63->=n7?<6:p0a5=838pR9m?;<71>1e73->=n7?<8:p0a4=838pR9l8;<71>1d03->=n7?<9:p0f>=838pR9l9;<71>1d13->=n7?<a:p0ae=838pR9jl;<71>1bd3->=n7?<b:p0`4=838pR9k=;<71>1c53->=n7?<c:p16>=838pR8<k;<71>04c3->=n7?<d:p117=838pR8=:;<71>0523->=n7?<f:p116=838pR8=;;<71>0533->=n7?;0:p16`=838pR8=<;<71>0543->=n7?;1:p16c=838pR8==;<71>0553->=n7?;2:p16b=838pR8=>;<71>0563->=n7?;3:p16e=838pR8=?;<71>0573->=n7?;4:p16d=838pR8<i;<71>04a3->=n7?;5:p16g=838pR8<j;<71>04b3->=n7?;6:p16?=838pR8<l;<71>04d3->=n7?;7:p160=838pR8<m;<71>04e3->=n7?;8:p10?=838pR8:j;<71>02b3->=n7?;a:p134=838pR8;9;<71>0313->=n7?;b:p137=838pR8;:;<71>0323->=n7?;c:p136=838pR8;;;<71>0333->=n7?;d:p10`=838pR8;<;<71>0343->=n7?;e:p10c=838pR8;=;<71>0353->=n7?;f:p10b=838pR8;>;<71>0363->=n7?:0:p10e=838pR8;?;<71>0373->=n7?:1:p10d=838pR8:i;<71>02a3->=n7?:3:p10g=838pR8:k;<71>02c3->=n7?:4:p101=838pR8:l;<71>02d3->=n7?:5:~jgdd2909wE:9c:mfgb=838pD98l;|laf`<72;qC8;m4}o`ab?6=:rB?:n5rnca3>5<5sA>=o6sabb394?4|@=<h7p`mc383>7}O<?i0qcll3;296~N3>j1vbom;:181M21k2wenn;50;0xL10d3tdio;4?:3yK03e<ughh;7>52zJ72f=zfki36=4={I65g>{ijj31<7<tH54`?xhekh0;6?uG47a8ykddj3:1>vF;6b9~jged2909wE:9c:mffb=838pD98l;|lag`<72;qC8;m4}o``b?6=:rB?:n5rncf3>5<5sA>=o6sabe394?4|@=<h7p`md383>7}O<?i0qclk3;296~N3>j1vboj;:181M21k2weni;50;0xL10d3tdih;4?:3yK03e<ugho;7>52zJ72f=zfkn36=4={I65g>{ijm31<7<tH54`?xhelh0;6?uG47a8ykdcj3:1>vF;6b9~jgbd2909wE:9c:mfab=838pD98l;|la``<72;qC8;m4}o`gb?6=:rB?:n5rncg3>5<5sA>=o6sabd394?4|@=<h7p`me383>7}O<?i0qclj3;296~N3>j1vbok;:181M21k2wenh;50;0xL10d3tdii;4?:3yK03e<ughn;7>52zJ72f=zfko36=4={I65g>{ijl31<7<tH54`?xhemh0;6?uG47a8ykdbj3:1>vF;6b9~jgcd2909wE:9c:mf`b=838pD98l;|laa`<72;qC8;m4}o`fb?6=:rB?:n5rncd3>5<5sA>=o6sabg394?4|@=<h7p`mf383>7}O<?i0qcli3;296~N3>j1vboh;:181M21k2wenk;50;0xL10d3tdij;4?:3yK03e<ughm;7>52zJ72f=zfkl36=4={I65g>{ijo31<7<tH54`?xhenh0;6?uG47a8ykdaj3:1>vF;6b9~jg`d2909wE:9c:m=a?=83;pD98l;|lb5d<728qC8;m4}oc2f?6=9rB?:n5rn`3`>5<6sA>=o6saa0f94?7|@=<h7p`n1d83>4}O<?i0qco>f;295~N3>j1vbl<?:182M21k2wem??50;3xL10d3tdj>?4?:0yK03e<ugk9?7>51zJ72f=zfh8?6=4>{I65g>{ii;?1<7?tH54`?xhf:?0;6<uG47a8ykg5?3:1=vF;6b9~jd4?290:wE:9c:me7?=83;pD98l;|lb6d<728qC8;m4}oc1f?6=9rB?:n5rn`0`>5<6sA>=o6saa3f94?7|@=<h7p`n2d83>4}O<?i0qco=f;295~N3>j1vbl=?:182M21k2wem>?50;3xL10d3tdj??4?:0yK03e<ugk8?7>51zJ72f=zfh9?6=4>{I65g>{ii:?1<7?tH54`?xhf;?0;6<uG47a8ykg4?3:1=vF;6b9~jd5?290:wE:9c:me6?=83;pD98l;|lb7d<728qC8;m4}oc0f?6=9rB?:n5rn`1`>5<6sA>=o6saa2f94?7|@=<h7p`n3d83>4}O<?i0qco<f;295~N3>j1vbl:?:182M21k2wem9?50;3xL10d3tdj8?4?:0yK03e<ugk??7>51zJ72f=zfh>?6=4>{I65g>{ii=?1<7?tH54`?xhf<?0;6<uG47a8ykg3?3:1=vF;6b9~jd2?290:wE:9c:me1?=83;pD98l;|lb0d<728qC8;m4}oc7f?6=9rB?:n5rn`6`>5<6sA>=o6saa5f94?7|@=<h7p`n4d83>4}O<?i0qco;f;295~N3>j1vbl;?:182M21k2wem8?50;3xL10d3tdj9?4?:0yK03e<ugk>?7>51zJ72f=zfh??6=4>{I65g>{ii<?1<7?tH54`?xhf=?0;6<uG47a8ykg2?3:1=vF;6b9~jd3?290:wE:9c:me0?=83;pD98l;|lb1d<728qC8;m4}oc6f?6=9rB?:n5rn`7`>5<6sA>=o6saa4f94?7|@=<h7p`n5d83>4}O<?i0qco:f;295~N3>j1vbl8?:182M21k2wem;?50;3xL10d3tdj:?4?:0yK03e<ugk=?7>51zJ72f=zfh<?6=4>{I65g>{ii??1<7?tH54`?xhf>?0;6<uG47a8ykg1?3:1=vF;6b9~jd0?290:wE:9c:me3?=83;pD98l;|lb2d<728qC8;m4}oc5f?6=9rB?:n5rn`4`>5<6sA>=o6saa7f94?7|@=<h7p`n6d83>4}O<?i0qco9f;295~N3>j1vbl9?:182M21k2wem:?50;3xL10d3tdj;?4?:0yK03e<ugk<?7>51zJ72f=zfh=?6=4>{I65g>{ii>?1<7?tH54`?xhf??0;6<uG47a8ykg0?3:1=vF;6b9~jd1?290:wE:9c:me2?=83;pD98l;|lb3d<728qC8;m4}oc4f?6=9rB?:n5rn`5`>5<6sA>=o6saa6f94?7|@=<h7p`n7d83>4}O<?i0qco8f;295~N3>j1vbl6?:182M21k2wem5?50;3xL10d3tdj4?4?:0yK03e<ugk3?7>51zJ72f=zfh2?6=4>{I65g>{ii1?1<7?tH54`?xhf0?0;6<uG47a8ykg??3:1=vF;6b9~jd>?290:wE:9c:me=?=83;pD98l;|lb<d<728qC8;m4}oc;f?6=9rB?:n5rn`:`>5<6sA>=o6saa9f94?7|@=<h7p`n8d83>4}O<?i0qco7f;295~N3>j1vbl7?:182M21k2wem4?50;3xL10d3tdj5?4?:0yK03e<ugk2?7>51zJ72f=zfh3?6=4>{I65g>{ii0?1<7?tH54`?xhf1?0;6<uG47a8ykg>?3:1=vF;6b9~jd??290:wE:9c:me<?=83;pD98l;|lb=d<728qC8;m4}oc:f?6=9rB?:n5rn`;`>5<6sA>=o6saa8f94?7|@=<h7p`n9d83>4}O<?i0qco6f;295~N3>j1vblo?:182M21k2weml?50;3xL10d3tdjm?4?:0yK03e<ugkj?7>51zJ72f=zfhk?6=4>{I65g>{iih?1<7?tH54`?xhfi?0;6<uG47a8ykgf?3:1=vF;6b9~jdg?290:wE:9c:med?=83;pD98l;|lbed<728qC8;m4}ocbf?6=9rB?:n5rn`c`>5<6sA>=o6saa`f94?7|@=<h7p`nad83>4}O<?i0qconf;295~N3>j1vbll?:182M21k2wemo?50;3xL10d3tdjn?4?:0yK03e<ugki?7>51zJ72f=zfhh?6=4>{I65g>{iik?1<7?tH54`?xhfj?0;6<uG47a8ykge?3:1=vF;6b9~jdd?290:wE:9c:meg?=83;pD98l;|lbfd<728qC8;m4}ocaf?6=9rB?:n5rn```>5<6sA>=o6saacf94?7|@=<h7p`nbd83>4}O<?i0qcomf;295~N3>j1vblm?:182M21k2wemn?50;3xL10d3tdjo?4?:0yK03e<ugkh?7>51zJ72f=zfhi?6=4>{I65g>{iij?1<7?tH54`?xhfk?0;6<uG47a8ykgd?3:1=vF;6b9~jde?290:wE:9c:mef?=83;pD98l;|lbgd<728qC8;m4}oc`f?6=9rB?:n5rn`a`>5<6sA>=o6saabf94?7|@=<h7p`ncd83>4}O<?i0qcolf;295~N3>j1vblj?:182M21k2wemi?50;3xL10d3tdjh?4?:0yK03e<ugko?7>51zJ72f=zfhn?6=4>{I65g>{iim?1<7?tH54`?xhfl?0;6<uG47a8ykgc?3:1=vF;6b9~jdb?290:wE:9c:mea?=83;pD98l;|lb`d<728qC8;m4}ocgf?6=9rB?:n5rn`f`>5<6sA>=o6saaef94?7|@=<h7p`ndd83>4}O<?i0qcokf;295~N3>j1vblk?:182M21k2wemh?50;3xL10d3tdji?4?:0yK03e<ugkn?7>51zJ72f=zfho?6=4>{I65g>{iil?1<7?tH54`?xhfm?0;6<uG47a8ykgb?3:1=vF;6b9~jdc?290:wE:9c:me`?=83;pD98l;|lbad<728qC8;m4}ocff?6=9rB?:n5rn`g`>5<6sA>=o6saadf94?7|@=<h7p`ned83>4}O<?i0qcojf;295~N3>j1vblh?:182M21k2wemk?50;3xL10d3tdjj?4?:0yK03e<ugkm?7>51zJ72f=zfhl?6=4>{I65g>{iio?1<7?tH54`?xhfn?0;6<uG47a8ykga?3:1=vF;6b9~jd`?290:wE:9c:mec?=83;pD98l;|lbbd<728qC8;m4}ocef?6=9rB?:n5rn`d`>5<6sA>=o6saagf94?7|@=<h7p`nfd83>4}O<?i0qcoif;295~N3>j1vbo>?:182M21k2wen=?50;3xL10d3tdi<?4?:0yK03e<ugh;?7>51zJ72f=zfk:?6=4>{I65g>{ij9?1<7?tH54`?xhe8?0;6<uG47a8ykd7?3:1=vF;6b9~jg6?290:wE:9c:mf5?=83;pD98l;|la4d<728qC8;m4}o`3f?6=9rB?:n5rnc2`>5<6sA>=o6sab1f94?7|@=<h7p`m0d83>4}O<?i0qcl?f;295~N3>j1vbo??:182M21k2wen<?50;3xL10d3tdi=?4?:0yK03e<ugh:?7>51zJ72f=zfk;?6=4>{I65g>{ij8?1<7?tH54`?xhe9?0;6<uG47a8ykd6?3:1=vF;6b9~jg7?290:wE:9c:mf4?=83;pD98l;|la5d<728qC8;m4}o`2f?6=9rB?:n5rnc3`>5<6sA>=o6sab0f94?7|@=<h7p`m1d83>4}O<?i0qcl>f;295~N3>j1vbo<?:182M21k2wen??50;3xL10d3tdi>?4?:0yK03e<ugh9?7>51zJ72f=zfk8?6=4>{I65g>{ij;?1<7?tH54`?xhe:?0;6<uG47a8ykd5?3:1=vF;6b9~jg4?290:wE:9c:mf7?=83;pD98l;|la6d<728qC8;m4}o`1f?6=9rB?:n5rnc0`>5<6sA>=o6sab3f94?7|@=<h7p`m2d83>4}O<?i0qcl=f;295~N3>j1vbo=?:182M21k2wen>?50;3xL10d3tdi??4?:0yK03e<ugh8?7>51zJ72f=zfk9?6=4>{I65g>{ij:?1<7?tH54`?xhe;?0;6<uG47a8ykd4?3:1=vF;6b9~jg5?290:wE:9c:mf6?=83;pD98l;|la7d<728qC8;m4}o`0f?6=9rB?:n5rnc1`>5<6sA>=o6sab2f94?7|@=<h7p`m3d83>4}O<?i0qcl<f;295~N3>j1vbo:?:182M21k2wen9?50;3xL10d3tdi8?4?:0yK03e<ugh??7>51zJ72f=zfk>?6=4>{I65g>{ij=?1<7?tH54`?xhe<?0;6<uG47a8ykd3?3:1=vF;6b9~jg2?290:wE:9c:mf1?=83;pD98l;|la0d<728qC8;m4}o`7f?6=9rB?:n5rnc6`>5<6sA>=o6sab5f94?7|@=<h7p`m4d83>4}O<?i0qcl;f;295~N3>j1vbo;?:182M21k2wen8?50;3xL10d3tdi9?4?:0yK03e<ugh>?7>51zJ72f=zfk??6=4>{I65g>{ij<?1<7?tH54`?xhe=?0;6<uG47a8ykd2?3:1=vF;6b9~jg3?290:wE:9c:mf0?=83;pD98l;|la1d<728qC8;m4}o`6f?6=9rB?:n5rnc7`>5<6sA>=o6sab4f94?7|@=<h7p`m5d83>4}O<?i0qcl:f;295~N3>j1vbo8?:182M21k2wen;?50;3xL10d3tdi:?4?:0yK03e<ugh=?7>51zJ72f=zfk<?6=4>{I65g>{ij??1<7?tH54`?xhe>?0;6<uG47a8ykd1?3:1=vF;6b9~jg0?290:wE:9c:mf3?=83;pD98l;|la2d<728qC8;m4}o`5f?6=9rB?:n5rnc4`>5<6sA>=o6sab7f94?7|@=<h7p`m6d83>4}O<?i0qcl9f;295~N3>j1vbo9?:182M21k2wen:?50;3xL10d3tdi;?4?:0yK03e<ugh<?7>51zJ72f=zfk=?6=4>{I65g>{ij>?1<7?tH54`?xhe??0;6<uG47a8ykd0?3:1=vF;6b9~jg1?290:wE:9c:mf2?=83;pD98l;|la3d<728qC8;m4}o`4f?6=9rB?:n5rnc5`>5<6sA>=o6sab6f94?7|@=<h7p`m7d83>4}O<?i0qcl8f;295~N3>j1vbo6?:182M21k2wen5?50;3xL10d3tdi4?4?:0yK03e<ugh3?7>51zJ72f=zfk2?6=4>{I65g>{ij1?1<7?tH54`?xhe0?0;6<uG47a8ykd??3:1=vF;6b9~jg>?290:wE:9c:mf=?=83;pD98l;|la<d<728qC8;m4}o`;f?6=9rB?:n5rnc:`>5<6sA>=o6sab9f94?7|@=<h7p`m8d83>4}O<?i0qcl7f;295~N3>j1vbo7?:182M21k2wen4?50;3xL10d3tdi5?4?:0yK03e<ugh2?7>51zJ72f=zfk3?6=4>{I65g>{ij0?1<7?tH54`?xhe1?0;6<uG47a8ykd>?3:1=vF;6b9~jg??290:wE:9c:mf<?=83;pD98l;|la=d<728qC8;m4}o`:f?6=9rB?:n5rnc;`>5<6sA>=o6sab8f94?7|@=<h7p`m9d83>4}O<?i0qcl6f;295~N3>j1vboo?:182M21k2wenl?50;3xL10d3tdim?4?:0yK03e<ughj?7>51zJ72f=zfkk?6=4>{I65g>{ijh?1<7?tH54`?xhei?0;6<uG47a8ykdf?3:1=vF;6b9~jgg?290:wE:9c:mfd?=83;pD98l;|laed<728qC8;m4}o`bf?6=9rB?:n5rncc`>5<6sA>=o6sab`f94?7|@=<h7p`mad83>4}O<?i0qclnf;295~N3>j1vbol?:182M21k2weno?50;3xL10d3tdin?4?:0yK03e<ughi?7>51zJ72f=zfkh?6=4>{I65g>{ijk?1<7?tH54`?xhej?0;6<uG47a8ykde?3:1=vF;6b9~jgd?290:wE:9c:mfg?=83;pD98l;|lafd<728qC8;m4}o`af?6=9rB?:n5r}|CDF}cm8028>><e6c~DED|8tJK\vsO@
\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.v new file mode 100644 index 000000000..4737fb1bf --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.v @@ -0,0 +1,3819 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: K.39 +// \ \ Application: netgen +// / / Filename: fifo_xlnx_1Kx18_2clk.v +// /___/ /\ Timestamp: Fri Jun 10 16:12:12 2011 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog /tmp/_cg/fifo_xlnx_1Kx18_2clk.ngc /tmp/_cg/fifo_xlnx_1Kx18_2clk.v +// Device : 3s2000fg456-5 +// Input file : /tmp/_cg/fifo_xlnx_1Kx18_2clk.ngc +// Output file : /tmp/_cg/fifo_xlnx_1Kx18_2clk.v +// # of Modules : 1 +// Design Name : fifo_xlnx_1Kx18_2clk +// Xilinx : /opt/Xilinx/10.1/ISE +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module fifo_xlnx_1Kx18_2clk ( + rd_en, wr_en, full, empty, wr_clk, rst, rd_clk, wr_data_count, rd_data_count, dout, din +); + input rd_en; + input wr_en; + output full; + output empty; + input wr_clk; + input rst; + input rd_clk; + output [10 : 0] wr_data_count; + output [10 : 0] rd_data_count; + output [17 : 0] dout; + input [17 : 0] din; + + // synthesis translate_off + + wire \BU2/U0/grf.rf/gl0.rd/ram_valid_fwft ; + wire \BU2/N39 ; + wire \BU2/N31 ; + wire \BU2/N37 ; + wire \BU2/N27 ; + wire \BU2/N25 ; + wire \BU2/N21 ; + wire \BU2/N19 ; + wire \BU2/N17 ; + wire \BU2/N11 ; + wire \BU2/N13 ; + wire \BU2/N36 ; + wire \BU2/N381 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>4_470 ; + wire \BU2/N6 ; + wire \BU2/N7 ; + wire \BU2/N35 ; + wire \BU2/N41 ; + wire \BU2/N2 ; + wire \BU2/N40 ; + wire \BU2/N30 ; + wire \BU2/N4 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ; + wire \BU2/N38 ; + wire \BU2/N33 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ; + wire \BU2/N351 ; + wire \BU2/U0/grf.rf/mem/tmp_ram_rd_en ; + wire \BU2/U0/grf.rf/ram_regout_en ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt_425 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt_424 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt_422 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt_420 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt_418 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt_416 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt_414 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt_412 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt_410 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9>_rt_408 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count7 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count5 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count6 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count8 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count9 ; + wire \BU2/U0/grf.rf/ram_wr_en ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_385 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt_378 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt_377 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt_375 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt_373 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt_371 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt_369 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt_367 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt_365 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt_363 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9>_rt_361 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count7 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count5 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count6 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count8 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count9 ; + wire \BU2/U0/grf.rf/ram_rd_en ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0008 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0007 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0006 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0005 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0004 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0008 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0007 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0006 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0005 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0004 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0008 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0007 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0005 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0004 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0008 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0007 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0005 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0004 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp1 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/comp1 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/comp0 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000016 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00006 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ; + wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[9] ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_94 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or0000 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_81 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ; + wire \BU2/U0/grf.rf/rstblk/wr_rst_comb ; + wire \BU2/U0/grf.rf/rstblk/rd_rst_comb ; + wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_72 ; + wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_71 ; + wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_70 ; + wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_69 ; + wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_68 ; + wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_67 ; + wire \BU2/N1 ; + wire NLW_VCC_P_UNCONNECTED; + wire NLW_GND_G_UNCONNECTED; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<15>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<14>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<13>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<12>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<11>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<10>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<9>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<8>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<7>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<6>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<5>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<4>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<3>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<2>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<1>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<0>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOPA<1>_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOPA<0>_UNCONNECTED ; + wire [17 : 0] din_2; + wire [17 : 0] dout_3; + wire [10 : 0] rd_data_count_4; + wire [10 : 0] wr_data_count_5; + wire [17 : 0] \BU2/U0/grf.rf/mem/dout_mem ; + wire [9 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 ; + wire [8 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy ; + wire [9 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count ; + wire [8 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy ; + wire [9 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count ; + wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc ; + wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc ; + wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 ; + wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg ; + wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 ; + wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 ; + wire [3 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 ; + wire [3 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 ; + wire [3 : 0] \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 ; + wire [3 : 0] \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet ; + wire [9 : 0] \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut ; + wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin ; + wire [9 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 ; + wire [8 : 0] \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy ; + wire [9 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut ; + wire [9 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 ; + wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin ; + wire [8 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy ; + wire [1 : 1] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy ; + wire [0 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/diff_wr_rd_tmp ; + wire [9 : 1] \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 ; + wire [0 : 0] \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/diff_wr_rd_tmp ; + wire [10 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 ; + wire [1 : 0] \BU2/U0/grf.rf/rstblk/wr_rst_reg ; + wire [2 : 0] \BU2/U0/grf.rf/rstblk/rd_rst_reg ; + wire [0 : 0] \BU2/data_count ; + assign + wr_data_count[10] = wr_data_count_5[10], + wr_data_count[9] = wr_data_count_5[9], + wr_data_count[8] = wr_data_count_5[8], + wr_data_count[7] = wr_data_count_5[7], + wr_data_count[6] = wr_data_count_5[6], + wr_data_count[5] = wr_data_count_5[5], + wr_data_count[4] = wr_data_count_5[4], + wr_data_count[3] = wr_data_count_5[3], + wr_data_count[2] = wr_data_count_5[2], + wr_data_count[1] = wr_data_count_5[1], + wr_data_count[0] = wr_data_count_5[0], + rd_data_count[10] = rd_data_count_4[10], + rd_data_count[9] = rd_data_count_4[9], + rd_data_count[8] = rd_data_count_4[8], + rd_data_count[7] = rd_data_count_4[7], + rd_data_count[6] = rd_data_count_4[6], + rd_data_count[5] = rd_data_count_4[5], + rd_data_count[4] = rd_data_count_4[4], + rd_data_count[3] = rd_data_count_4[3], + rd_data_count[2] = rd_data_count_4[2], + rd_data_count[1] = rd_data_count_4[1], + rd_data_count[0] = rd_data_count_4[0], + dout[17] = dout_3[17], + dout[16] = dout_3[16], + dout[15] = dout_3[15], + dout[14] = dout_3[14], + dout[13] = dout_3[13], + dout[12] = dout_3[12], + dout[11] = dout_3[11], + dout[10] = dout_3[10], + dout[9] = dout_3[9], + dout[8] = dout_3[8], + dout[7] = dout_3[7], + dout[6] = dout_3[6], + dout[5] = dout_3[5], + dout[4] = dout_3[4], + dout[3] = dout_3[3], + dout[2] = dout_3[2], + dout[1] = dout_3[1], + dout[0] = dout_3[0], + din_2[17] = din[17], + din_2[16] = din[16], + din_2[15] = din[15], + din_2[14] = din[14], + din_2[13] = din[13], + din_2[12] = din[12], + din_2[11] = din[11], + din_2[10] = din[10], + din_2[9] = din[9], + din_2[8] = din[8], + din_2[7] = din[7], + din_2[6] = din[6], + din_2[5] = din[5], + din_2[4] = din[4], + din_2[3] = din[3], + din_2[2] = din[2], + din_2[1] = din[1], + din_2[0] = din[0]; + VCC VCC_0 ( + .P(NLW_VCC_P_UNCONNECTED) + ); + GND GND_1 ( + .G(NLW_GND_G_UNCONNECTED) + ); + LUT4_D #( + .INIT ( 16'h0440 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>31 ( + .I0(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ), + .LO(\BU2/N40 ), + .O(\BU2/N33 ) + ); + LUT4_L #( + .INIT ( 16'h8000 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<8>_SW1_SW0 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ), + .LO(\BU2/N31 ) + ); + LUT3_D #( + .INIT ( 8'h80 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<9>_SW0_SW0 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ), + .LO(\BU2/N39 ), + .O(\BU2/N27 ) + ); + LUT4_L #( + .INIT ( 16'h8000 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>21_SW1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ), + .LO(\BU2/N19 ) + ); + LUT3_L #( + .INIT ( 8'h80 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>21_SW0 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ), + .LO(\BU2/N17 ) + ); + LUT4_D #( + .INIT ( 16'h2000 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<4>111_SW0 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ), + .I1(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .I2(\BU2/U0/grf.rf/gl0.rd/ram_valid_fwft ), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]), + .LO(\BU2/N381 ), + .O(\BU2/N11 ) + ); + LUT3_D #( + .INIT ( 8'h80 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>41_SW0 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ), + .LO(\BU2/N37 ), + .O(\BU2/N13 ) + ); + LUT3_D #( + .INIT ( 8'h7F )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<4>111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ), + .LO(\BU2/N36 ), + .O(\BU2/N38 ) + ); + LUT2_D #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/RAM_VALID_FWFT11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ), + .LO(\BU2/N351 ), + .O(\BU2/U0/grf.rf/gl0.rd/ram_valid_fwft ) + ); + RAMB16_S18_S18 #( + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .SRVAL_A ( 18'h00000 ), + .SRVAL_B ( 18'h00000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_B ( "WRITE_FIRST" ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .SIM_COLLISION_CHECK ( "NONE" ), + .INIT_A ( 18'h00000 ), + .INIT_B ( 18'h00000 ), + .WRITE_MODE_A ( "WRITE_FIRST" ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 )) + \BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram ( + .CLKA(wr_clk), + .CLKB(rd_clk), + .ENA(\BU2/N1 ), + .ENB(\BU2/U0/grf.rf/mem/tmp_ram_rd_en ), + .SSRA(\BU2/data_count [0]), + .SSRB(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .WEA(\BU2/U0/grf.rf/ram_wr_en ), + .WEB(\BU2/data_count [0]), + .ADDRA({\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7], +\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4], +\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1], +\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]}), + .ADDRB({\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7], +\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4], +\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1], +\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]}), + .DIA({din_2[16], din_2[15], din_2[14], din_2[13], din_2[12], din_2[11], din_2[10], din_2[9], din_2[7], din_2[6], din_2[5], din_2[4], din_2[3], +din_2[2], din_2[1], din_2[0]}), + .DIB({\BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], +\BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], +\BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0]}), + .DIPA({din_2[17], din_2[8]}), + .DIPB({\BU2/data_count [0], \BU2/data_count [0]}), + .DOA({\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<15>_UNCONNECTED +, \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<14>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<13>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<12>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<11>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<10>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<9>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<8>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<7>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<6>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<5>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<4>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<3>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<2>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<1>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<0>_UNCONNECTED }), + .DOPA({ +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOPA<1>_UNCONNECTED , +\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOPA<0>_UNCONNECTED }), + .DOB({\BU2/U0/grf.rf/mem/dout_mem [16], \BU2/U0/grf.rf/mem/dout_mem [15], \BU2/U0/grf.rf/mem/dout_mem [14], \BU2/U0/grf.rf/mem/dout_mem [13], +\BU2/U0/grf.rf/mem/dout_mem [12], \BU2/U0/grf.rf/mem/dout_mem [11], \BU2/U0/grf.rf/mem/dout_mem [10], \BU2/U0/grf.rf/mem/dout_mem [9], +\BU2/U0/grf.rf/mem/dout_mem [7], \BU2/U0/grf.rf/mem/dout_mem [6], \BU2/U0/grf.rf/mem/dout_mem [5], \BU2/U0/grf.rf/mem/dout_mem [4], +\BU2/U0/grf.rf/mem/dout_mem [3], \BU2/U0/grf.rf/mem/dout_mem [2], \BU2/U0/grf.rf/mem/dout_mem [1], \BU2/U0/grf.rf/mem/dout_mem [0]}), + .DOPB({\BU2/U0/grf.rf/mem/dout_mem [17], \BU2/U0/grf.rf/mem/dout_mem [8]}) + ); + INV \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_xor<1>11_INV_0 ( + .I(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [1]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9> ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000016 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ), + .I3(\BU2/N39 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[9] ) + ); + LUT4 #( + .INIT ( 16'h7FFF )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<8>_SW1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ), + .I3(\BU2/N31 ), + .O(\BU2/N7 ) + ); + LUT4 #( + .INIT ( 16'hA2AA )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>30_SW0 ( + .I0(\BU2/N33 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ), + .I2(\BU2/N4 ), + .I3(\BU2/N37 ), + .O(\BU2/N21 ) + ); + LUT4 #( + .INIT ( 16'h6CCC )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<9> ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000016 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ), + .I3(\BU2/N27 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [9]) + ); + LUT4 #( + .INIT ( 16'h6CCC )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<8>1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ), + .I3(\BU2/N25 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [8]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>31_SW1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ), + .O(\BU2/N25 ) + ); + LUT4 #( + .INIT ( 16'hEAC0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>38 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>4_470 ), + .I2(\BU2/N35 ), + .I3(\BU2/N21 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [9]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<8>_SW0 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ), + .I2(\BU2/N11 ), + .I3(\BU2/N19 ), + .O(\BU2/N6 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>41 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ), + .I2(\BU2/N11 ), + .I3(\BU2/N17 ), + .O(\BU2/N35 ) + ); + LUT4 #( + .INIT ( 16'h7FFF )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<5>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ), + .O(\BU2/N4 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<10>1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ), + .I2(\BU2/N13 ), + .I3(\BU2/N30 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [10]) + ); + LUT4 #( + .INIT ( 16'hFF7F )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<7>_SW0 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ), + .I3(\BU2/N36 ), + .O(\BU2/N41 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>21 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ), + .I3(\BU2/N381 ), + .O(\BU2/N30 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [9]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9>_rt_408 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [9]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9>_rt_361 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt_425 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt_424 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt_422 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt_420 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt_418 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [5]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt_416 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [6]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt_414 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [7]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt_412 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [8]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt_410 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt_378 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt_377 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt_375 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt_373 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt_371 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [5]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt_369 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [6]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt_367 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [7]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt_365 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [8]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt_363 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>41 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00006 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>4 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>4_470 ) + ); + LUT4 #( + .INIT ( 16'hD580 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<8> ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ), + .I1(\BU2/N33 ), + .I2(\BU2/N7 ), + .I3(\BU2/N6 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [8]) + ); + LUT4 #( + .INIT ( 16'hD580 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<7> ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ), + .I1(\BU2/N33 ), + .I2(\BU2/N41 ), + .I3(\BU2/N35 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [7]) + ); + LUT4 #( + .INIT ( 16'hEA40 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<6> ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ), + .I2(\BU2/N30 ), + .I3(\BU2/N2 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [6]) + ); + LUT4 #( + .INIT ( 16'hAA2A )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<6>_SW0 ( + .I0(\BU2/N40 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ), + .I3(\BU2/N38 ), + .O(\BU2/N2 ) + ); + LUT4 #( + .INIT ( 16'hD580 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<5>2 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ), + .I1(\BU2/N4 ), + .I2(\BU2/N33 ), + .I3(\BU2/N30 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [5]) + ); + LUT4 #( + .INIT ( 16'h6CCC )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<7>1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [7]) + ); + LUT3 #( + .INIT ( 8'h6C )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<6>1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [6]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<5>1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [5]) + ); + LUT3 #( + .INIT ( 8'h82 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<4>1 ( + .I0(\BU2/N33 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ), + .I2(\BU2/N38 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [4]) + ); + LUT4 #( + .INIT ( 16'h6CCC )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_xor<4>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00006 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [4]) + ); + LUT4 #( + .INIT ( 16'h60C0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<3>1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ), + .I2(\BU2/N33 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [3]) + ); + LUT3 #( + .INIT ( 8'h6C )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_xor<3>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [3]) + ); + LUT3 #( + .INIT ( 8'h28 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<2>1 ( + .I0(\BU2/N33 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [2]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_xor<2>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [2]) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<1>1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]), + .I1(\BU2/N33 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [1]) + ); + LUT4 #( + .INIT ( 16'h9669 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor000611 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ) + ); + LUT4 #( + .INIT ( 16'h9669 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00081 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0008 ) + ); + LUT4 #( + .INIT ( 16'h9669 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor000611 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ) + ); + LUT4 #( + .INIT ( 16'h9669 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00081 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0008 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00071 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0007 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00071 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0007 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00062 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00062 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_0_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [0]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_0_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [0]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_0_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [0]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_0_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [0]) + ); + LUT4 #( + .INIT ( 16'hBAAA )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp1 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_94 ), + .I2(wr_en), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or0000 ) + ); + LUT3 #( + .INIT ( 8'hF8 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/comp1 ), + .I1(\BU2/U0/grf.rf/ram_rd_en ), + .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/comp0 ), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_1_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [1]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_1_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [1]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_1_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [1]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_1_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [1]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_2_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [2]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_2_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [5]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [2]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_2_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [5]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [5]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [2]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_2_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [5]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [5]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [2]) + ); + LUT4 #( + .INIT ( 16'h3010 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<0>1 ( + .I0(\BU2/N351 ), + .I1(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/diff_wr_rd_tmp [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [0]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_3_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [3]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_3_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [7]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [6]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [3]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_3_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [7]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [7]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [6]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [6]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [3]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_3_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [7]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [7]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [6]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [6]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [3]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_4_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [9]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [4]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_4_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [9]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [9]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [8]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [4]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_4_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [9]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [9]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [8]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [8]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [4]) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_4_and00001 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [9]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [9]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [8]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [8]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [4]) + ); + LUT2 #( + .INIT ( 4'hE )) + \BU2/U0/grf.rf/mem/tmp_ram_rd_en1 ( + .I0(\BU2/U0/grf.rf/ram_rd_en ), + .I1(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .O(\BU2/U0/grf.rf/mem/tmp_ram_rd_en ) + ); + LUT4 #( + .INIT ( 16'h5455 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/RAM_RD_EN_FWFT1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_81 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ), + .I2(rd_en), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ), + .O(\BU2/U0/grf.rf/ram_rd_en ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00051 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0005 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00051 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0005 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00041 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0004 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00041 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0004 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00032 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00032 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ) + ); + LUT3 #( + .INIT ( 8'h62 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/RAM_REGOUT_EN1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ), + .I2(rd_en), + .O(\BU2/U0/grf.rf/ram_regout_en ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_94 ), + .I1(wr_en), + .O(\BU2/U0/grf.rf/ram_wr_en ) + ); + LUT4 #( + .INIT ( 16'h69A1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_81 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ), + .I3(rd_en), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ) + ); + LUT4 #( + .INIT ( 16'hCA8A )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_385 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ), + .I3(rd_en), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [7]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [6]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [8]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [7]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [6]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [8]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ) + ); + LUT3 #( + .INIT ( 8'h6E )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ), + .I2(rd_en), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [8]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [7]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [8]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [7]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0004_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0004 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0005_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0005 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0006_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0006 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0007_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0007 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0008_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0008 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0004_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0004 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0005_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0005 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0006_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0006 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0007_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0007 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0008_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0008 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [8]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [8]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/rstblk/rd_rst_comb1 ( + .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_68 ), + .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_71 ), + .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/rstblk/wr_rst_comb1 ( + .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_70 ), + .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_72 ), + .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [0]), + .Q(dout_3[0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [1]), + .Q(dout_3[1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [2]), + .Q(dout_3[2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [3]), + .Q(dout_3[3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [4]), + .Q(dout_3[4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [5]), + .Q(dout_3[5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [6]), + .Q(dout_3[6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [7]), + .Q(dout_3[7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [8]), + .Q(dout_3[8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [9]), + .Q(dout_3[9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_10 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [10]), + .Q(dout_3[10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_11 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [11]), + .Q(dout_3[11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_12 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [12]), + .Q(dout_3[12]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_13 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [13]), + .Q(dout_3[13]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_14 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [14]), + .Q(dout_3[14]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_15 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [15]), + .Q(dout_3[15]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_16 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [16]), + .Q(dout_3[16]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_17 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_regout_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/dout_mem [17]), + .Q(dout_3[17]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_5 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [5]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_6 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [6]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_7 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [7]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_8 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [8]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_9 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [9]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_9 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [9]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_8 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [8]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_6 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [6]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_5 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [5]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_7 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [7]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0> ( + .CI(\BU2/N1 ), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt_425 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [0]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0> ( + .CI(\BU2/N1 ), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt_425 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [0]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt_424 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [1]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [0]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt_424 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [1]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt_422 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [2]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [1]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt_422 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [2]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt_420 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [3]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [2]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt_420 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [3]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt_418 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [3]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt_418 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [4]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt_416 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [5]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<5> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [4]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt_416 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count5 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [5]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt_414 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [6]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<6> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [5]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt_414 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count6 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [6]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt_412 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [7]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<7> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [6]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt_412 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count7 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [7]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt_410 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [8]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<8> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [7]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt_410 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count8 ) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9> ( + .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [8]), + .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9>_rt_408 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count9 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_7 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count7 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_5 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count5 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_6 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count6 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_8 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count8 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_9 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/ram_wr_en ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count9 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [9]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_385 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(empty) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [5]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [6]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [7]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [8]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [9]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0> ( + .CI(\BU2/N1 ), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt_378 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [0]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0> ( + .CI(\BU2/N1 ), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt_378 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [0]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt_377 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [1]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [0]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt_377 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [1]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt_375 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [2]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [1]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt_375 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [2]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt_373 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [3]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [2]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt_373 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [3]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt_371 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [3]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt_371 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [4]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt_369 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [5]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<5> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [4]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt_369 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count5 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [5]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt_367 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [6]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<6> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [5]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt_367 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count6 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [6]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt_365 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [7]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<7> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [6]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt_365 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count7 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [7]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt_363 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [8]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<8> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [7]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt_363 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count8 ) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9> ( + .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [8]), + .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9>_rt_361 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count9 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count7 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count5 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count6 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count8 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/ram_rd_en ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count9 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0008 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0007 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0006 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0005 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0004 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_5 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_6 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_7 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_8 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_9 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0008 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0007 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0006 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0005 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0004 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_5 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_6 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_7 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_8 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_9 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_5 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [5]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_6 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [6]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_7 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [7]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_8 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [8]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_9 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [9]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [5]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_6 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [6]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_7 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [7]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_8 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [8]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [9]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_5 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [5]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_6 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [6]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_7 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [7]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_8 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [8]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_9 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [9]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [5]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [6]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_7 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [7]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_8 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [8]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_9 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [9]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0008 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0007 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0005 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0004 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_5 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_6 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_7 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_8 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_9 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0008 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0007 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0005 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0004 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_5 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_6 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_7 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_8 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_9 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [9]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[0].gm1.m1 ( + .CI(\BU2/N1 ), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[1].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [0]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [1]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[2].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [1]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [2]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[3].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [2]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [3]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[4].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [3]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[0].gm1.m1 ( + .CI(\BU2/N1 ), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[1].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [0]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [1]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[2].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [1]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [2]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[3].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [2]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [3]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[4].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [3]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp1 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[0].gm1.m1 ( + .CI(\BU2/N1 ), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[1].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [0]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [1]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[2].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [1]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [2]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [2]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[3].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [2]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [3]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[4].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [3]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [4]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/comp1 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[0].gm1.m1 ( + .CI(\BU2/N1 ), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[1].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [0]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [1]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[2].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [1]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [2]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [2]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[3].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [2]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [3]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[4].gms.ms ( + .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [3]), + .DI(\BU2/data_count [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [4]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/comp0 ) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<9> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [8]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [9]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000016 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<9> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [9]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [9]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<8> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [7]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [8]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<8> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [7]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [8]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [8]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<8> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [8]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [8]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<7> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [6]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [7]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<7> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [6]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [7]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [7]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<7> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [7]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [7]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<6> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [5]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [6]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<6> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [5]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [6]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [6]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<6> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [6]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [6]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<5> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [4]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [5]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<5> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [4]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [5]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [5]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<5> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [5]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [5]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [3]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00006 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [3]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [4]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<4> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<3> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [2]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<3> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [2]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [3]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<3> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [3]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<2> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [1]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<2> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [1]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [2]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<2> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [2]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<1> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [0]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<1> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [0]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [1]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<1> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [1]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<0> ( + .CI(\BU2/N1 ), + .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/diff_wr_rd_tmp [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<0> ( + .CI(\BU2/N1 ), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [0]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<0> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [0]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<9> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [8]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [9]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<9> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [9]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [9]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<8> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [7]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [8]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<8> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [7]), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [8]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [8]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<8> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [8]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<7> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [6]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [7]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<7> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [6]), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [7]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [7]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<7> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [7]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<6> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [5]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [6]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<6> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [5]), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [6]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [6]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<6> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [6]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<5> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [4]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [5]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<5> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [4]), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [5]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [5]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<5> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [5]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<4> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [3]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [4]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<4> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [3]), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [4]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [4]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<4> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<3> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [2]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<3> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [2]), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [3]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<3> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [3]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<2> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [1]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [2]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<2> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [1]), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [2]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [2]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<2> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [2]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<1> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [0]), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<1> ( + .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [0]), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [1]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<1> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [1]) + ); + XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<0> ( + .CI(\BU2/N1 ), + .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/diff_wr_rd_tmp [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<0> ( + .CI(\BU2/N1 ), + .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), + .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [0]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<0> ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_10 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[9] ), + .Q(wr_data_count_5[10]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_9 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [9]), + .Q(wr_data_count_5[9]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_8 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [8]), + .Q(wr_data_count_5[8]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_7 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [7]), + .Q(wr_data_count_5[7]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_6 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [6]), + .Q(wr_data_count_5[6]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_5 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [5]), + .Q(wr_data_count_5[5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [4]), + .Q(wr_data_count_5[4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [3]), + .Q(wr_data_count_5[3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [2]), + .Q(wr_data_count_5[2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [1]), + .Q(wr_data_count_5[1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/diff_wr_rd_tmp [0]), + .Q(wr_data_count_5[0]) + ); + FDP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_94 ) + ); + FDP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(full) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_10 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [10]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[10]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_9 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [9]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[9]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_8 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [8]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[8]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_7 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [7]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[7]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_6 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [6]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[6]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_5 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [5]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[5]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [4]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[4]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [3]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[3]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [2]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[2]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [1]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[1]) + ); + FDCP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [0]), + .PRE(\BU2/data_count [0]), + .Q(rd_data_count_4[0]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_81 ) + ); + FDP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 ( + .C(wr_clk), + .D(\BU2/data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]) + ); + FDP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 ( + .C(wr_clk), + .D(\BU2/data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]) + ); + FDP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 ( + .C(rd_clk), + .D(\BU2/data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]) + ); + FDP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 ( + .C(rd_clk), + .D(\BU2/data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]) + ); + FDP #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 ( + .C(rd_clk), + .D(\BU2/data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]) + ); + FDPE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_67 ), + .D(\BU2/data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_71 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_72 ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_69 ) + ); + FDPE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_69 ), + .D(\BU2/data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_72 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_71 ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_67 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_69 ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_70 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_67 ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_68 ) + ); + VCC \BU2/XST_VCC ( + .P(\BU2/N1 ) + ); + GND \BU2/XST_GND ( + .G(\BU2/data_count [0]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire PRLD; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +// synthesis translate_on diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.veo new file mode 100644 index 000000000..c98e03c3b --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.veo @@ -0,0 +1,47 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_1Kx18_2clk YourInstanceName ( + .din(din), // Bus [17 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [17 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [10 : 0] + .wr_data_count(wr_data_count)); // Bus [10 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.xco new file mode 100644 index 000000000..082aef22b --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Fri Jun 10 23:12:12 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_1Kx18_2clk +CSET data_count=false +CSET data_count_width=11 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1023 +CSET full_threshold_negate_value=1022 +CSET input_data_width=18 +CSET input_depth=1024 +CSET output_data_width=18 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=11 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=11 +# END Parameters +GENERATE +# CRC: c3fb8408 + diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..be22cb8dc --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,106 @@ +<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> +<document OS="lin64" product="ISE" version="10.1.03"> + + <!--The data in this file is primarily intended for consumption by Xilinx tools. + The structure and the elements are likely to change over the next few releases. + This means code written to parse this file will need to be revisited each subsequent release.--> + + <application stringID="Xst" timeStamp="Fri Jun 10 16:11:52 2011"> + <section stringID="XST_HDL_SYNTHESIS_REPORT"> + <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item> + <item dataType="int" stringID="XST_COUNTERS" value="2"> + <item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/> + </item> + <item dataType="int" stringID="XST_REGISTERS" value="31"> + <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/> + <item dataType="int" stringID="XST_10BIT_REGISTER" value="11"/> + <item dataType="int" stringID="XST_11BIT_REGISTER" value="2"/> + <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/> + <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/> + </item> + <item dataType="int" stringID="XST_XORS" value="76"> + <item dataType="int" stringID="XST_1BIT_XOR2" value="76"/> + </item> + </section> + <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT"> + <item dataType="int" stringID="XST_FSMS" value="1"/> + <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item> + <item dataType="int" stringID="XST_COUNTERS" value="2"> + <item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/> + </item> + <item dataType="int" stringID="XST_REGISTERS" value="159"> + <item dataType="int" stringID="XST_FLIPFLOPS" value="159"/> + </item> + <item dataType="int" stringID="XST_XORS" value="76"> + <item dataType="int" stringID="XST_1BIT_XOR2" value="76"/> + </item> + </section> + <section stringID="XST_FINAL_REGISTER_REPORT"> + <item dataType="int" stringID="XST_REGISTERS" value="189"> + <item dataType="int" stringID="XST_FLIPFLOPS" value="189"/> + </item> + </section> + <section stringID="XST_PARTITION_REPORT"> + <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS"> + <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> + </section> + </section> + <section stringID="XST_FINAL_REPORT"> + <section stringID="XST_FINAL_RESULTS"> + <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/tmp/_cg/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc"/> + <item stringID="XST_OUTPUT_FORMAT" value="NGC"/> + <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/> + <item stringID="XST_KEEP_HIERARCHY" value="no"/> + </section> + <section stringID="XST_DESIGN_STATISTICS"> + <item stringID="XST_IOS" value="153"/> + </section> + <section stringID="XST_CELL_USAGE"> + <item dataType="int" stringID="XST_BELS" value="248"> + <item dataType="int" stringID="XST_GND" value="1"/> + <item dataType="int" stringID="XST_INV" value="1"/> + <item dataType="int" stringID="XST_LUT1" value="20"/> + <item dataType="int" stringID="XST_LUT2" value="52"/> + <item dataType="int" stringID="XST_LUT2D" value="1"/> + <item dataType="int" stringID="XST_LUT3" value="14"/> + <item dataType="int" stringID="XST_LUT3D" value="3"/> + <item dataType="int" stringID="XST_LUT3L" value="1"/> + <item dataType="int" stringID="XST_LUT4" value="54"/> + <item dataType="int" stringID="XST_LUT4D" value="2"/> + <item dataType="int" stringID="XST_LUT4L" value="2"/> + <item dataType="int" stringID="XST_MUXCY" value="56"/> + <item dataType="int" stringID="XST_VCC" value="1"/> + <item dataType="int" stringID="XST_XORCY" value="40"/> + </item> + <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="189"> + <item dataType="int" stringID="XST_FD" value="4"/> + <item dataType="int" stringID="XST_FDC" value="94"/> + <item dataType="int" stringID="XST_FDCE" value="65"/> + <item dataType="int" stringID="XST_FDP" value="10"/> + <item dataType="int" stringID="XST_FDPE" value="5"/> + </item> + <item dataType="int" stringID="XST_RAMS" value="1"> + <item dataType="int" stringID="XST_RAMB16S18S18" value="1"/> + </item> + </section> + </section> + <section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> + <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/> + <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="139"/> + <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="189"/> + <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="150"/> + <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="153"/> + <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/> + <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="1"/> + </section> + <section stringID="XST_PARTITION_RESOURCE_SUMMARY"> + <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> + </section> + <section stringID="XST_ERRORS_STATISTICS"> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="136"/> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="17"/> + </section> + </application> + +</document> diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_flist.txt new file mode 100644 index 000000000..3bd308751 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_flist.txt @@ -0,0 +1,8 @@ +# Output products list for <fifo_xlnx_1Kx18_2clk> +fifo_xlnx_1Kx18_2clk.ngc +fifo_xlnx_1Kx18_2clk.v +fifo_xlnx_1Kx18_2clk.veo +fifo_xlnx_1Kx18_2clk.xco +fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_1Kx18_2clk_flist.txt +fifo_xlnx_1Kx18_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_readme.txt new file mode 100644 index 000000000..72f83d6fb --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_readme.txt @@ -0,0 +1,38 @@ +The following files were generated for 'fifo_xlnx_1Kx18_2clk' in directory +/home/matt/sourcerepo/fpga/usrp2/coregen/: + +fifo_xlnx_1Kx18_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_1Kx18_2clk.v: + Unisim Verilog file containing the information required to simulate + the module. + +fifo_xlnx_1Kx18_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_1Kx18_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_1Kx18_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_1Kx18_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_1Kx18_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_xmdf.tcl new file mode 100644 index 000000000..244d03d85 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_xlnx_1Kx18_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_xlnx_1Kx18_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_1Kx18_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_1Kx18_2clk +} +# ::fifo_xlnx_1Kx18_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_1Kx18_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_1Kx18_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/fifo/fifo_2clock.v b/fpga/usrp2/fifo/fifo_2clock.v index 756ad508f..c6aaf34dc 100644 --- a/fpga/usrp2/fifo/fifo_2clock.v +++ b/fpga/usrp2/fifo/fifo_2clock.v @@ -65,6 +65,11 @@ module fifo_2clock (.rst(arst), .wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if ((WIDTH==18) & (SIZE==10)) + fifo_xlnx_1Kx18_2clk fifo_xlnx_1Kx18_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs index bff6ae3e0..bf0c0ecfd 100644 --- a/fpga/usrp2/gpmc/Makefile.srcs +++ b/fpga/usrp2/gpmc/Makefile.srcs @@ -17,4 +17,6 @@ gpmc_to_fifo_async.v \ gpmc_to_fifo_sync.v \ gpmc_wb.v \ ram_to_fifo.v \ +new_write.v \ +new_read.v \ )) diff --git a/fpga/usrp2/gpmc/fifo_watcher.v b/fpga/usrp2/gpmc/fifo_watcher.v index b139f5143..3971e3c54 100644 --- a/fpga/usrp2/gpmc/fifo_watcher.v +++ b/fpga/usrp2/gpmc/fifo_watcher.v @@ -30,10 +30,11 @@ module fifo_watcher reg [15:0] counter; wire [4:0] pkt_count; assign debug = pkt_count; + wire space; fifo_short #(.WIDTH(16)) frame_lengths (.clk(clk), .reset(reset), .clear(clear), - .datain(counter), .src_rdy_i(write), .dst_rdy_o(), + .datain(counter), .src_rdy_i(write), .dst_rdy_o(space), .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read), .occupied(pkt_count), .space()); @@ -53,7 +54,9 @@ module fifo_watcher bus_error <= 1; else if(read & ~have_packet_int) bus_error <= 1; - + else if(write & ~space) + bus_error <= 1; + reg in_packet; always @(posedge clk) if(reset | clear) diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v index c0bec683a..9972e81b0 100644 --- a/fpga/usrp2/gpmc/gpmc_async.v +++ b/fpga/usrp2/gpmc/gpmc_async.v @@ -22,7 +22,7 @@ module gpmc_async parameter RXFIFOSIZE = 11, parameter BUSDEBUG = 1) (// GPMC signals - input arst, + input arst, input bus_clk, input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, @@ -67,27 +67,21 @@ module gpmc_async // //////////////////////////////////////////// // TX Data Path - wire [17:0] tx18_data, tx18b_data; - wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [17:0] tx18_data; + wire tx18_src_rdy, tx18_dst_rdy; wire [15:0] tx_fifo_space; wire [35:0] tx36_data, tx_data; wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy; - gpmc_to_fifo_async gpmc_to_fifo_async + new_write new_write (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx), + .bus_clk(bus_clk), .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx), .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), - .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), - .bus_error(bus_error_tx) ); + .frame_len(tx_frame_len), .fifo_ready(tx_have_space), .bus_error(bus_error_tx) ); - fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), - .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), - .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); - fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), - .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 @@ -110,31 +104,20 @@ module gpmc_async .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + wire [31:0] pkt_count; + wire throttle = pkt_count == 16; + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); - fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), - .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); - - fifo_to_gpmc_async fifo_to_gpmc_async + new_read new_read (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), - .frame_len(rx_frame_len) ); - - wire [31:0] pkt_count; + .have_packet(rx_have_data), .frame_len(rx_frame_len), .bus_error(bus_error_rx) ); - fifo_watcher fifo_watcher - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), - .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), - .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx), - .debug(pkt_count)); - // //////////////////////////////////////////// // Control path on CS6 @@ -230,16 +213,13 @@ module gpmc_async // FIXME -- make sure packet completes before we shutoff // FIXME -- handle overrun and underrun -wire [0:17] dummy18; - -assign debug = {8'd0, - test_rate, - pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int, - timedrx_src_rdy, timedrx_dst_rdy, - testrx_src_rdy, testrx_dst_rdy, - rx_src_rdy, rx_dst_rdy, - rx36_src_rdy, rx36_dst_rdy, - rx18_src_rdy, rx18_dst_rdy, - rx18b_src_rdy, rx18b_dst_rdy}; + wire [0:17] dummy18; + + assign debug = {rx_overrun, tx_underrun, bus_error_tx, bus_error_rx, tx_have_space, rx_have_data, EM_NCS4, EM_NCS6, + 6'd0, EM_NOE, EM_NWE, + pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int, + timedrx_src_rdy, timedrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy, + rx_src_rdy, rx_dst_rdy, rx36_src_rdy, rx36_dst_rdy, rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy}; endmodule // gpmc_async diff --git a/fpga/usrp2/gpmc/new_read.v b/fpga/usrp2/gpmc/new_read.v new file mode 100644 index 000000000..ae3db23cf --- /dev/null +++ b/fpga/usrp2/gpmc/new_read.v @@ -0,0 +1,62 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module new_read + (input clk, input reset, input clear, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + output reg [15:0] EM_D, input EM_NCS, input EM_NOE, + output have_packet, output [15:0] frame_len, output bus_error); + + wire [17:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); + + fifo_watcher fifo_watcher + (.clk(clk), .reset(reset), .clear(clear), + .src_rdy1(src_rdy_i), .dst_rdy1(dst_rdy_o), .sof1(data_i[16]), .eof1(data_i[17]), + .src_rdy2(src_rdy_int), .dst_rdy2(dst_rdy_int), .sof2(data_int[16]), .eof2(data_int[17]), + .have_packet(have_packet), .length(frame_len), .bus_error(bus_error), + .debug()); + + // Synchronize the async control signals + reg [1:0] cs_del, oe_del; + reg [15:0] counter; + + always @(posedge clk) + if(reset) + begin + cs_del <= 2'b11; + oe_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + oe_del <= { oe_del[0], EM_NOE }; + end + + assign dst_rdy_int = ( ~cs_del[1] & ~oe_del[1] & oe_del[0]); // change output on trailing edge + + //always @(posedge clk) // 3 cycle latency ( OE -> OE_del -> FIFO -> output REG ) + always @* // 2 cycle latency ( OE -> OE_del -> FIFO ) + EM_D <= data_int[15:0]; + +endmodule // new_read diff --git a/fpga/usrp2/gpmc/new_write.v b/fpga/usrp2/gpmc/new_write.v new file mode 100644 index 000000000..df0ce19db --- /dev/null +++ b/fpga/usrp2/gpmc/new_write.v @@ -0,0 +1,82 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module new_write + (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, + + input bus_clk, + input fifo_clk, input fifo_rst, input clear, + output [17:0] data_o, output src_rdy_o, input dst_rdy_i, + + input [15:0] frame_len, output reg fifo_ready, + output reg bus_error ); + + wire [15:0] fifo_space; + reg [15:0] counter; + + // Synchronize the async control signals + reg [1:0] cs_del, we_del; + reg [15:0] data_del[0:1]; + + always @(posedge bus_clk) + if(fifo_rst) + begin + cs_del <= 2'b11; + we_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + data_del[1] <= data_del[0]; + data_del[0] <= EM_D; + end + + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + + wire [17:0] data_int = {last_write,first_write,data_del[1]}; + wire src_rdy_int = (~cs_del[1] & ~we_del[1] & we_del[0]); // rising edge + wire dst_rdy_int; + + always @(posedge bus_clk) + if(fifo_rst | clear) + counter <= 0; + else if(src_rdy_int) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + always @(posedge bus_clk) + if(fifo_rst | clear) + fifo_ready <= 0; + else + fifo_ready <= /* first_write & */ (fifo_space > 16'd1023); + + always @(posedge bus_clk) + if(fifo_rst | clear) + bus_error <= 0; + else if(src_rdy_int & ~dst_rdy_int) + bus_error <= 1; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.wclk(bus_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(fifo_space), + .rclk(fifo_clk), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(fifo_rst)); + +endmodule // new_write diff --git a/fpga/usrp2/sdr_lib/Makefile.srcs b/fpga/usrp2/sdr_lib/Makefile.srcs index 90eede20f..defbced17 100644 --- a/fpga/usrp2/sdr_lib/Makefile.srcs +++ b/fpga/usrp2/sdr_lib/Makefile.srcs @@ -8,6 +8,8 @@ SDR_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../sdr_lib/, \ acc.v \ add2.v \ +add2_and_clip.v \ +add2_and_clip_reg.v \ add2_and_round.v \ add2_and_round_reg.v \ add2_reg.v \ @@ -22,16 +24,16 @@ cordic.v \ cordic_z24.v \ cordic_stage.v \ dsp_core_rx.v \ -dsp_core_rx_old.v \ dsp_core_tx.v \ hb_dec.v \ hb_interp.v \ round.v \ round_reg.v \ -rx_control.v \ +round_sd.v \ rx_dcoffset.v \ +rx_frontend.v \ sign_extend.v \ small_hb_dec.v \ small_hb_int.v \ -tx_control.v \ +tx_frontend.v \ )) diff --git a/fpga/usrp2/sdr_lib/add2_and_clip.v b/fpga/usrp2/sdr_lib/add2_and_clip.v new file mode 100644 index 000000000..663f5d004 --- /dev/null +++ b/fpga/usrp2/sdr_lib/add2_and_clip.v @@ -0,0 +1,12 @@ + +module add2_and_clip + #(parameter WIDTH=16) + (input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output [WIDTH-1:0] sum); + + wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; + clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip + (.in(sum_int),.out(sum)); + +endmodule // add2_and_clip diff --git a/fpga/usrp2/sdr_lib/add2_and_clip_reg.v b/fpga/usrp2/sdr_lib/add2_and_clip_reg.v new file mode 100644 index 000000000..8073b3b54 --- /dev/null +++ b/fpga/usrp2/sdr_lib/add2_and_clip_reg.v @@ -0,0 +1,25 @@ + +module add2_and_clip_reg + #(parameter WIDTH=16) + (input clk, + input rst, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + input strobe_in, + output reg [WIDTH-1:0] sum, + output reg strobe_out); + + wire [WIDTH-1:0] sum_int; + + add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + if(rst) + sum <= 0; + else if(strobe_in) + sum <= sum_int; + + always @(posedge clk) + strobe_out <= strobe_in; + +endmodule // add2_and_clip_reg diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx.v b/fpga/usrp2/sdr_lib/dsp_core_rx.v index 0e69e53f7..639744de7 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_rx.v +++ b/fpga/usrp2/sdr_lib/dsp_core_rx.v @@ -21,8 +21,8 @@ module dsp_core_rx (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, + input [23:0] adc_i, input adc_ovf_i, + input [23:0] adc_q, input adc_ovf_q, output [31:0] sample, input run, @@ -30,70 +30,56 @@ module dsp_core_rx output [31:0] debug ); - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; wire [31:0] phase_inc; reg [31:0] phase; - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic, q_cordic; + wire [24:0] i_cordic, q_cordic; + wire [23:0] i_cordic_clip, q_cordic_clip; wire [23:0] i_cic, q_cic; - wire [17:0] i_cic_scaled, q_cic_scaled; - wire [17:0] i_hb1, q_hb1; - wire [17:0] i_hb2, q_hb2; - wire [15:0] i_out, q_out; - + wire [23:0] i_hb1, q_hb1; + wire [23:0] i_hb2, q_hb2; + wire strobe_cic, strobe_hb1, strobe_hb2; wire enable_hb1, enable_hb2; wire [7:0] cic_decim_rate; + reg [23:0] adc_i_mux, adc_q_mux; + wire realmode; + wire swap_iq; + setting_reg #(.my_addr(BASE+0)) sr_0 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_inc),.changed()); + /* setting_reg #(.my_addr(BASE+1)) sr_1 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({scale_i,scale_q}),.changed()); + */ setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed()); - rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - - wire [7:0] muxctrl; - setting_reg #(.my_addr(BASE+5), .width(8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(BASE+6), .width(2)) sr_9 + setting_reg #(.my_addr(BASE+3), .width(2)) sr_3 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); + .in(set_data),.out({realmode,swap_iq}),.changed()); - always @(posedge clk) - case(muxctrl[3:0]) // The I mapping - 0: adc_i <= adc_a_ofs; - 1: adc_i <= adc_b_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case (muxctrl[3:0]) + // MUX so we can do realmode signals on either input always @(posedge clk) - case(muxctrl[7:4]) // The Q mapping - 0: adc_q <= adc_a_ofs; - 1: adc_q <= adc_b_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case (muxctrl[7:4]) - + if(swap_iq) + begin + adc_i_mux <= adc_q; + adc_q_mux <= realmode ? 24'd0 : adc_i; + end + else + begin + adc_i_mux <= adc_i; + adc_q_mux <= realmode ? 24'd0 : adc_q; + end + + // NCO always @(posedge clk) if(rst) phase <= 0; @@ -102,74 +88,55 @@ module dsp_core_rx else phase <= phase + phase_inc; - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - cordic_z24 #(.bitwidth(24)) + // CORDIC 24-bit I/O + cordic_z24 #(.bitwidth(25)) cordic(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]), + .xi({adc_i_mux[23],adc_i_mux}),. yi({adc_q_mux[23],adc_q_mux}), .zi(phase[31:8]), .xo(i_cordic),.yo(q_cordic),.zo() ); + clip_reg #(.bits_in(25), .bits_out(24)) clip_i (.clk(clk), .in(i_cordic), .out(i_cordic_clip)); + clip_reg #(.bits_in(25), .bits_out(24)) clip_q (.clk(clk), .in(q_cordic), .out(q_cordic_clip)); + + // CIC decimator 24 bit I/O cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate), .strobe_fast(1),.strobe_slow(strobe_cic) ); cic_decim #(.bw(24)) decim_i (.clock(clk),.reset(rst),.enable(run), .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), - .signal_in(i_cordic),.signal_out(i_cic)); + .signal_in(i_cordic_clip),.signal_out(i_cic)); cic_decim #(.bw(24)) decim_q (.clock(clk),.reset(rst),.enable(run), .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), - .signal_in(q_cordic),.signal_out(q_cic)); + .signal_in(q_cordic_clip),.signal_out(q_cic)); - round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled)); - round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled)); - reg strobe_cic_d1; - always @(posedge clk) strobe_cic_d1 <= strobe_cic; - - small_hb_dec #(.WIDTH(18)) small_hb_i + // First (small) halfband 24 bit I/O + small_hb_dec #(.WIDTH(24)) small_hb_i (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), - .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1)); + .stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1)); - small_hb_dec #(.WIDTH(18)) small_hb_q + small_hb_dec #(.WIDTH(24)) small_hb_q (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), - .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1)); + .stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1)); + // Second (large) halfband 24 bit I/O wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate}; - hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i + hb_dec #(.WIDTH(24)) hb_i (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2)); - hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q + hb_dec #(.WIDTH(24)) hb_q (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); - round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); - round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); + // Round final answer to 16 bits + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i + (.clk(clk),.reset(rst), .in(i_hb2),.strobe_in(strobe_hb2), .out(sample[31:16]), .strobe_out(strobe)); - reg [31:0] sample_reg; - always @(posedge clk) - sample_reg <= {i_out,q_out}; + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q + (.clk(clk),.reset(rst), .in(q_hb2),.strobe_in(strobe_hb2), .out(sample[15:0]), .strobe_out()); - assign sample = sample_reg; - assign strobe = strobe_hb2; - assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; + assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2}; endmodule // dsp_core_rx diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v b/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v new file mode 100644 index 000000000..271db8cef --- /dev/null +++ b/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v @@ -0,0 +1,73 @@ + +`timescale 1ns/1ns +module dsp_core_rx_tb(); + + reg clk, rst; + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #5 clk = ~clk; + + initial $dumpfile("dsp_core_rx_tb.vcd"); + initial $dumpvars(0,dsp_core_rx_tb); + + reg signed [23:0] adc_in; + wire signed [15:0] adc_out_i, adc_out_q; + + always @(posedge clk) + begin + $display(adc_in); + $display(adc_out_i); + $display(adc_out_q); + end + + reg run; + reg set_stb; + reg [7:0] set_addr; + reg [31:0] set_data; + + dsp_core_rx #(.BASE(0)) dsp_core_rx + (.clk(clk),.rst(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_i(adc_in), .adc_ovf_i(0), + .adc_q(0), .adc_ovf_q(0), + .sample({adc_out_i,adc_out_q}), + .run(run), .strobe(), .debug()); + + initial + begin + run <= 0; + @(negedge rst); + @(posedge clk); + set_addr <= 1; + set_data <= {16'd64,16'd64}; // set gains + set_stb <= 1; + @(posedge clk); + set_addr <= 2; + set_data <= {16'd0,8'd3,8'd1}; // set decim + set_stb <= 1; + @(posedge clk); + set_addr <= 0; + //set_data <= {32'h0000_0000}; + set_data <= {32'h01CA_C083}; // 700 kHz + set_stb <= 1; + @(posedge clk); + set_stb <= 0; + @(posedge clk); + run <= 1; + end + + always @(posedge clk) + //adc_in <= 24'd1000000; + adc_in <= 24'h80_0000; + + /* + always @(posedge clk) + if(rst) + adc_in <= 0; + else + adc_in <= adc_in + 4; + //adc_in <= (($random % 473) + 23)/4; +*/ +endmodule // dsp_core_rx_tb diff --git a/fpga/usrp2/sdr_lib/dsp_core_tx.v b/fpga/usrp2/sdr_lib/dsp_core_tx.v index 58bd82f6e..f02c63b42 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_tx.v +++ b/fpga/usrp2/sdr_lib/dsp_core_tx.v @@ -21,8 +21,7 @@ module dsp_core_tx (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, - output reg [15:0] dac_a, - output reg [15:0] dac_b, + output [23:0] tx_i, output [23:0] tx_q, // To tx_control input [31:0] sample, @@ -50,10 +49,6 @@ module dsp_core_tx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed()); - setting_reg #(.my_addr(BASE+4), .width(8)) sr_4 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({dacmux_b,dacmux_a}),.changed()); - // Strobes are all now delayed by 1 cycle for timing reasons wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre; reg strobe_cic = 1; @@ -148,20 +143,9 @@ module dsp_core_tx .CE(1), // Clock enable input .R(rst) // Synchronous reset input ); - - always @(posedge clk) - case(dacmux_a) - 0 : dac_a <= prod_i[28:13]; - 1 : dac_a <= prod_q[28:13]; - default : dac_a <= 0; - endcase // case(dacmux_a) - - always @(posedge clk) - case(dacmux_b) - 0 : dac_b <= prod_i[28:13]; - 1 : dac_b <= prod_q[28:13]; - default : dac_b <= 0; - endcase // case(dacmux_b) + + assign tx_i = prod_i[28:5]; + assign tx_q = prod_q[28:5]; assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run}; diff --git a/fpga/usrp2/sdr_lib/hb_dec.v b/fpga/usrp2/sdr_lib/hb_dec.v index 9747f0adb..8d21c21c0 100644 --- a/fpga/usrp2/sdr_lib/hb_dec.v +++ b/fpga/usrp2/sdr_lib/hb_dec.v @@ -22,17 +22,27 @@ // myfilt = round(2^18 * halfgen4(.7/4,8)) module hb_dec - #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=24) + #(parameter WIDTH=24) (input clk, input rst, input bypass, input run, input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block input stb_in, - input [IWIDTH-1:0] data_in, + input [WIDTH-1:0] data_in, output reg stb_out, - output reg [OWIDTH-1:0] data_out); + output reg [WIDTH-1:0] data_out); + localparam INTWIDTH = 17; + localparam ACCWIDTH = WIDTH + 3; + + // Round off inputs to 17 bits because of 18 bit multipliers + wire [INTWIDTH-1:0] data_rnd; + wire stb_rnd; + + round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in + (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd)); + // Control reg [3:0] addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d; wire write_odd, write_even, do_mult; @@ -45,16 +55,16 @@ module hb_dec always @(posedge clk) if(rst | ~run) odd <= 0; - else if(stb_in) + else if(stb_rnd) odd <= ~odd; - assign write_odd = stb_in & odd; - assign write_even = stb_in & ~odd; + assign write_odd = stb_rnd & odd; + assign write_even = stb_rnd & ~odd; always @(posedge clk) if(rst | ~run) phase <= 0; - else if(stb_in & odd) + else if(stb_rnd & odd) phase <= 1; else if(phase == 4) phase <= 0; @@ -69,7 +79,7 @@ module hb_dec if(rst) stb_out_pre <= 0; else - stb_out_pre <= {stb_out_pre[14:0],(stb_in & odd)}; + stb_out_pre <= {stb_out_pre[14:0],(stb_rnd & odd)}; always @* case(phase) @@ -93,11 +103,12 @@ module hb_dec assign clear = stb_out_pre[3]; // Data - wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d; - wire [IWIDTH-1:0] sum1, sum2; - wire [OWIDTH-1:0] final_sum; - reg [CWIDTH-1:0] coeff1, coeff2; - wire [35:0] prod1, prod2; + wire [INTWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d; + reg [INTWIDTH:0] sum1, sum2; // these are 18-bit inputs to mult + reg [WIDTH:0] final_sum; + wire [WIDTH-1:0] final_sum_clip; + reg [17:0] coeff1, coeff2; + wire [35:0] prod1, prod2; always @* // Outer coeffs case(phase_d1) @@ -117,19 +128,19 @@ module hb_dec default : coeff2 = -6107; endcase // case(phase) - srl #(.WIDTH(IWIDTH)) srl_odd_a - (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_a),.out(data_odd_a)); - srl #(.WIDTH(IWIDTH)) srl_odd_b - (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_b),.out(data_odd_b)); - srl #(.WIDTH(IWIDTH)) srl_odd_c - (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_c),.out(data_odd_c)); - srl #(.WIDTH(IWIDTH)) srl_odd_d - (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d)); - - add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1)); - add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2)); - - wire [IWIDTH-1:0] data_even; + srl #(.WIDTH(INTWIDTH)) srl_odd_a + (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_a),.out(data_odd_a)); + srl #(.WIDTH(INTWIDTH)) srl_odd_b + (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_b),.out(data_odd_b)); + srl #(.WIDTH(INTWIDTH)) srl_odd_c + (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_c),.out(data_odd_c)); + srl #(.WIDTH(INTWIDTH)) srl_odd_d + (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_d),.out(data_odd_d)); + + always @(posedge clk) sum1 <= {data_odd_a[INTWIDTH-1],data_odd_a} + {data_odd_b[INTWIDTH-1],data_odd_b}; + always @(posedge clk) sum2 <= {data_odd_c[INTWIDTH-1],data_odd_c} + {data_odd_d[INTWIDTH-1],data_odd_d}; + + wire [INTWIDTH-1:0] data_even; reg [3:0] addr_even; always @(posedge clk) @@ -140,49 +151,39 @@ module hb_dec default : addr_even <= 7; endcase // case(cpi) - srl #(.WIDTH(IWIDTH)) srl_even - (.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even)); - - localparam MWIDTH = ACCWIDTH-2; - wire [MWIDTH-1:0] sum_of_prod; + srl #(.WIDTH(INTWIDTH)) srl_even + (.clk(clk),.write(write_even),.in(data_rnd),.addr(addr_even),.out(data_even)); MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); - add2_and_round_reg #(.WIDTH(MWIDTH)) - add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod)); - wire [ACCWIDTH-1:0] acc_out; + reg [35:0] sum_of_prod; + always @(posedge clk) sum_of_prod <= prod1 + prod2; // Can't overflow - acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) - acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out)); + wire [ACCWIDTH-1:0] acc_out; + acc #(.IWIDTH(ACCWIDTH-2),.OWIDTH(ACCWIDTH)) + acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod[35:38-ACCWIDTH]),.out(acc_out)); - localparam SHIFT_FACTOR = ACCWIDTH-IWIDTH-5; wire [ACCWIDTH-1:0] data_even_signext; - wire [ACCWIDTH:0] final_sum_unrounded; - sign_extend #(.bits_in(IWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) - signext_data_even (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR])); - assign data_even_signext[SHIFT_FACTOR-1:0] = 0; + localparam SHIFT_FACTOR = 6; - add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1)) - final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded)); - - round_reg #(.bits_in(ACCWIDTH-4),.bits_out(OWIDTH)) - final_round (.clk(clk),.in(final_sum_unrounded[ACCWIDTH-5:0]),.out(final_sum)); - - // Output - always @(posedge clk) - if(bypass) - data_out <= data_in; - else if(stb_out_pre[9]) - data_out <= final_sum; + sign_extend #(.bits_in(INTWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) signext_data_even + (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR])); + assign data_even_signext[SHIFT_FACTOR-1:0] = 0; + always @(posedge clk) final_sum <= acc_out + data_even_signext; + + clip #(.bits_in(WIDTH+1), .bits_out(WIDTH)) clip (.in(final_sum), .out(final_sum_clip)); + + // Output MUX to allow for bypass + wire selected_stb = bypass ? stb_in : stb_out_pre[8]; + always @(posedge clk) - if(rst) - stb_out <= 0; - else if(bypass) - stb_out <= stb_in; - else - stb_out <= stb_out_pre[9]; - + begin + stb_out <= selected_stb; + if(selected_stb) + data_out <= bypass ? data_in : final_sum_clip; + end + endmodule // hb_dec diff --git a/fpga/usrp2/sdr_lib/hb_dec_tb.v b/fpga/usrp2/sdr_lib/hb_dec_tb.v index 256f6085d..153cfba76 100644 --- a/fpga/usrp2/sdr_lib/hb_dec_tb.v +++ b/fpga/usrp2/sdr_lib/hb_dec_tb.v @@ -18,7 +18,7 @@ module hb_dec_tb( ) ; // Parameters for instantiation - parameter clocks = 9'd2 ; // Number of clocks per input + parameter clocks = 9'd12 ; // Number of clocks per input parameter decim = 1 ; // Sets the filter to decimate parameter rate = 2 ; // Sets the decimation rate @@ -26,9 +26,9 @@ module hb_dec_tb( ) ; reg reset ; reg enable ; reg strobe_in ; - reg signed [17:0] data_in ; + reg signed [23:0] data_in ; wire strobe_out ; - wire signed [17:0] data_out ; + wire signed [23:0] data_out ; initial begin @@ -65,8 +65,8 @@ module hb_dec_tb( ) ; */ - hb_dec #(.IWIDTH(18),.OWIDTH(18),.CWIDTH(18),.ACCWIDTH(24)) uut - (.clk(clock),.rst(reset),.bypass(0),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in), + hb_dec #(.WIDTH(24)) uut + (.clk(clock),.rst(reset),.bypass(0),.run(1),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in), .stb_out(strobe_out),.data_out(data_out) ); integer i, ri, ro, infile, outfile ; diff --git a/fpga/usrp2/sdr_lib/input.dat b/fpga/usrp2/sdr_lib/input.dat index 1e649ac2e..85b5887e8 100644 --- a/fpga/usrp2/sdr_lib/input.dat +++ b/fpga/usrp2/sdr_lib/input.dat @@ -6,7 +6,6 @@ 0 0 0 --131072 0 0 0 @@ -16,6 +15,7 @@ 0 0 0 +8388607 0 0 0 @@ -38,34 +38,6 @@ 0 0 0 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 0 0 0 @@ -82,6 +54,7 @@ 0 0 0 +8388607 0 0 0 @@ -96,200 +69,6 @@ 0 0 0 -131071 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -100000 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 --131072 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 -0 -0 0 0 0 @@ -313,6 +92,56 @@ 0 0 0 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 +8388607 0 0 0 @@ -339,3 +168,4 @@ 0 0 0 + diff --git a/fpga/usrp2/sdr_lib/round.v b/fpga/usrp2/sdr_lib/round.v index c4f9ec9cd..7a137d702 100644 --- a/fpga/usrp2/sdr_lib/round.v +++ b/fpga/usrp2/sdr_lib/round.v @@ -26,8 +26,10 @@ module round #(parameter bits_in=0, parameter bits_out=0) (input [bits_in-1:0] in, - output [bits_out-1:0] out); + output [bits_out-1:0] out, + output [bits_in-bits_out:0] err); assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]); + assign err = in - {out,{(bits_in-bits_out){1'b0}}}; endmodule // round diff --git a/fpga/usrp2/sdr_lib/round_reg.v b/fpga/usrp2/sdr_lib/round_reg.v index aa0972dab..6f2e974d7 100644 --- a/fpga/usrp2/sdr_lib/round_reg.v +++ b/fpga/usrp2/sdr_lib/round_reg.v @@ -27,13 +27,18 @@ module round_reg parameter bits_out=0) (input clk, input [bits_in-1:0] in, - output reg [bits_out-1:0] out); + output reg [bits_out-1:0] out, + output reg [bits_in-bits_out:0] err); wire [bits_out-1:0] temp; - - round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp)); + wire [bits_in-bits_out:0] err_temp; + + round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp)); always @(posedge clk) out <= temp; + + always @(posedge clk) + err <= err_temp; -endmodule // round +endmodule // round_reg diff --git a/fpga/usrp2/sdr_lib/round_sd.v b/fpga/usrp2/sdr_lib/round_sd.v new file mode 100644 index 000000000..aeeb3502f --- /dev/null +++ b/fpga/usrp2/sdr_lib/round_sd.v @@ -0,0 +1,22 @@ + + +module round_sd + #(parameter WIDTH_IN=18, + parameter WIDTH_OUT=16) + (input clk, input reset, + input [WIDTH_IN-1:0] in, input strobe_in, + output [WIDTH_OUT-1:0] out, output strobe_out); + + localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1; + + wire [ERR_WIDTH-1:0] err; + wire [WIDTH_IN-1:0] err_ext, sum; + + sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext)); + + add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg + (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out)); + + round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err)); + +endmodule // round_sd diff --git a/fpga/usrp2/sdr_lib/round_sd_tb.v b/fpga/usrp2/sdr_lib/round_sd_tb.v new file mode 100644 index 000000000..1e8e9a323 --- /dev/null +++ b/fpga/usrp2/sdr_lib/round_sd_tb.v @@ -0,0 +1,58 @@ + +module round_sd_tb(); + + reg clk, rst; + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #5 clk = ~clk; + + initial $dumpfile("round_sd_tb.vcd"); + initial $dumpvars(0,round_sd_tb); + + localparam WIDTH_IN = 8; + localparam WIDTH_OUT = 5; + + reg [WIDTH_IN-1:0] adc_in, adc_in_del; + wire [WIDTH_OUT-1:0] adc_out; + + integer factor = 1<<(WIDTH_IN-WIDTH_OUT); + + always @(posedge clk) + if(~rst) + begin + if(adc_in_del[WIDTH_IN-1]) + $write("-%d\t",-adc_in_del); + else + $write("%d\t",adc_in_del); + if(adc_out[WIDTH_OUT-1]) + $write("-%d\t",-adc_out); + else + $write("%d\t",adc_out); + $write("\n"); + + //$write("%f\t",adc_in_del/factor); + //$write("%f\n",adc_in_del/factor-adc_out); + end + + round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT)) + round_sd(.clk(clk),.reset(rst), .in(adc_in), .strobe_in(1'b1), .out(adc_out), .strobe_out()); + + reg [5:0] counter = 0; + + always @(posedge clk) + counter <= counter+1; + + always @(posedge clk) + adc_in_del <= adc_in; + + always @(posedge clk) + if(rst) + adc_in <= 0; + else if(counter == 63) + adc_in <= adc_in + 1; + + initial #300000 $finish; + +endmodule // longfifo_tb diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset.v b/fpga/usrp2/sdr_lib/rx_dcoffset.v index 64ff4110d..e43461261 100644 --- a/fpga/usrp2/sdr_lib/rx_dcoffset.v +++ b/fpga/usrp2/sdr_lib/rx_dcoffset.v @@ -18,43 +18,40 @@ module rx_dcoffset - #(parameter WIDTH=14, - parameter ADDR=8'd0) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out); - - // Because of some extra delays to make timing easier, the transfer function is: - // (z-1)/(z^2-z-alpha) where alpha is 1/2^n + #(parameter WIDTH=16, + parameter ADDR=8'd0, + parameter alpha_shift=16) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [WIDTH-1:0] in, output [WIDTH-1:0] out); - wire set_now = set_stb & (ADDR == set_addr); + wire set_now = set_stb & (ADDR == set_addr); - reg fixed; // uses fixed offset - wire signed [WIDTH-1:0] fixed_dco; - reg signed [31:0] integrator; + reg fixed; // uses fixed offset + wire [WIDTH-1:0] fixed_dco; + + localparam int_width = WIDTH + alpha_shift; + reg [int_width-1:0] integrator; + wire [WIDTH-1:0] quantized; always @(posedge clk) if(rst) begin fixed <= 0; - integrator <= 32'd0; + integrator <= {int_width{1'b0}}; end else if(set_now) begin - integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}}; + //integrator <= {set_data[30:0],{(31-int_width){1'b0}}}; fixed <= set_data[31]; end else if(~fixed) - integrator <= integrator + adc_out; - - wire [WIDTH:0] scaled_integrator; - - round #(.bits_in(33),.bits_out(15)) round (.in({integrator[31],integrator}),.out(scaled_integrator)); - - wire [WIDTH:0] adc_out_int = {adc_in[WIDTH-1],adc_in} - scaled_integrator; + integrator <= integrator + {{(alpha_shift){out[WIDTH-1]}},out}; - clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc - (.clk(clk),.in(adc_out_int),.out(adc_out)); + round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd + (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), .strobe_out()); + add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg + (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), .strobe_out()); endmodule // rx_dcoffset diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v index b0dd8cb05..b4fb66ad7 100644 --- a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v +++ b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v @@ -29,14 +29,26 @@ module rx_dcoffset_tb(); initial $dumpfile("rx_dcoffset_tb.vcd"); initial $dumpvars(0,rx_dcoffset_tb); - reg [13:0] adc_in = 7; + reg [13:0] adc_in; wire [13:0] adc_out; always @(posedge clk) - $display("%d\t%d",adc_in,adc_out); + begin + if(adc_in[13]) + $write("-%d,",-adc_in); + else + $write("%d,",adc_in); + if(adc_out[13]) + $write("-%d\n",-adc_out); + else + $write("%d\n",adc_out); + end - rx_dcoffset #(.WIDTH(14),.ADDR(0)) + rx_dcoffset #(.WIDTH(14),.ADDR(0), .alpha_shift(8)) rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0), - .adc_in(adc_in),.adc_out(adc_out)); + .in(adc_in),.out(adc_out)); + + always @(posedge clk) + adc_in <= (($random % 473) + 23)/4; endmodule // longfifo_tb diff --git a/fpga/usrp2/sdr_lib/rx_frontend.v b/fpga/usrp2/sdr_lib/rx_frontend.v new file mode 100644 index 000000000..04b14787e --- /dev/null +++ b/fpga/usrp2/sdr_lib/rx_frontend.v @@ -0,0 +1,73 @@ + +module rx_frontend + #(parameter BASE = 0) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [15:0] adc_a, input adc_ovf_a, + input [15:0] adc_b, input adc_ovf_b, + + output [23:0] i_out, output [23:0] q_out, + input run, + output [31:0] debug + ); + + reg [15:0] adc_i, adc_q; + wire [17:0] adc_i_ofs, adc_q_ofs; + wire [35:0] corr_i, corr_q; wire [17:0] mag_corr,phase_corr; + wire swap_iq; + wire [23:0] i_final, q_final; + + setting_reg #(.my_addr(BASE), .width(1)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(swap_iq),.changed()); + + always @(posedge clk) + if(swap_iq) // Swap + {adc_i,adc_q} <= {adc_b,adc_a}; + else + {adc_i,adc_q} <= {adc_a,adc_b}; + + setting_reg #(.my_addr(BASE+1),.width(18)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(mag_corr),.changed()); + + setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_corr),.changed()); + + rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_i,2'b00}),.out(adc_i_ofs)); + + rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_q,2'b00}),.out(adc_q_ofs)); + + MULT18X18S mult_mag_corr + (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); + + MULT18X18S mult_phase_corr + (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) ); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_i + (.clk(clk), .rst(rst), + .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), + .sum(i_final), .strobe_out()); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_q + (.clk(clk), .rst(rst), + .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), + .sum(q_final), .strobe_out()); + + assign i_out = i_final; + assign q_out = q_final; + + /* + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i + (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out()); + + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q + (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out()); + */ +endmodule // rx_frontend diff --git a/fpga/usrp2/sdr_lib/rx_frontend_tb.v b/fpga/usrp2/sdr_lib/rx_frontend_tb.v new file mode 100644 index 000000000..487b72687 --- /dev/null +++ b/fpga/usrp2/sdr_lib/rx_frontend_tb.v @@ -0,0 +1,45 @@ + +`timescale 1ns/1ns +module rx_frontend_tb(); + + reg clk, rst; + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #5 clk = ~clk; + + initial $dumpfile("rx_frontend_tb.vcd"); + initial $dumpvars(0,rx_frontend_tb); + + reg [15:0] adc_in; + wire [17:0] adc_out; + + always @(posedge clk) + begin + if(adc_in[13]) + $write("-%d,",-adc_in); + else + $write("%d,",adc_in); + if(adc_out[13]) + $write("-%d\n",-adc_out); + else + $write("%d\n",adc_out); + end + + rx_frontend #(.BASE(0)) rx_frontend + (.clk(clk),.rst(rst), + .set_stb(0),.set_addr(0),.set_data(0), + .adc_a(adc_in), .adc_ovf_a(0), + .adc_b(0), .adc_ovf_b(0), + .i_out(adc_out),.q_out(), + .run(), .debug()); + + always @(posedge clk) + if(rst) + adc_in <= 0; + else + adc_in <= adc_in + 4; + //adc_in <= (($random % 473) + 23)/4; + +endmodule // rx_frontend_tb diff --git a/fpga/usrp2/sdr_lib/small_hb_dec.v b/fpga/usrp2/sdr_lib/small_hb_dec.v index 151b8c287..a7f93e056 100644 --- a/fpga/usrp2/sdr_lib/small_hb_dec.v +++ b/fpga/usrp2/sdr_lib/small_hb_dec.v @@ -29,21 +29,30 @@ module small_hb_dec input stb_in, input [WIDTH-1:0] data_in, output reg stb_out, - output [WIDTH-1:0] data_out); + output reg [WIDTH-1:0] data_out); - reg stb_in_d1; - reg [WIDTH-1:0] data_in_d1; - always @(posedge clk) stb_in_d1 <= stb_in; - always @(posedge clk) data_in_d1 <= data_in; + // Round off inputs to 17 bits because of 18 bit multipliers + localparam INTWIDTH = 17; + wire [INTWIDTH-1:0] data_rnd; + wire stb_rnd; + + round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in + (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd)); + + + reg stb_rnd_d1; + reg [INTWIDTH-1:0] data_rnd_d1; + always @(posedge clk) stb_rnd_d1 <= stb_rnd; + always @(posedge clk) data_rnd_d1 <= data_rnd; wire go; reg phase, go_d1, go_d2, go_d3, go_d4; always @(posedge clk) if(rst | ~run) phase <= 0; - else if(stb_in_d1) + else if(stb_rnd_d1) phase <= ~phase; - assign go = stb_in_d1 & phase; + assign go = stb_rnd_d1 & phase; always @(posedge clk) if(rst | ~run) begin @@ -63,11 +72,11 @@ module small_hb_dec wire [17:0] coeff_a = -10690; wire [17:0] coeff_b = 75809; - reg [WIDTH-1:0] d1, d2, d3, d4 , d5, d6; + reg [INTWIDTH-1:0] d1, d2, d3, d4 , d5, d6; always @(posedge clk) - if(stb_in_d1 | rst) + if(stb_rnd_d1 | rst) begin - d1 <= data_in_d1; + d1 <= data_rnd_d1; d2 <= d1; d3 <= d2; d4 <= d3; @@ -76,16 +85,14 @@ module small_hb_dec end reg [17:0] sum_a, sum_b, middle, middle_d1; - wire [17:0] sum_a_unreg, sum_b_unreg; - add2 #(.WIDTH(18)) add2_a (.in1(data_in_d1),.in2(d6),.sum(sum_a_unreg)); - add2 #(.WIDTH(18)) add2_b (.in1(d2),.in2(d4),.sum(sum_b_unreg)); - + always @(posedge clk) if(go) begin - sum_a <= sum_a_unreg; - sum_b <= sum_b_unreg; - middle <= d3; + sum_a <= {data_rnd_d1[INTWIDTH-1],data_rnd_d1} + {d6[INTWIDTH-1],d6}; + sum_b <= {d2[INTWIDTH-1],d2} + {d4[INTWIDTH-1],d4}; + //middle <= {d3[INTWIDTH-1],d3}; + middle <= {d3,1'b0}; end always @(posedge clk) @@ -106,23 +113,22 @@ module small_hb_dec else if(go_d3) accum <= accum + {prod}; - wire [17:0] accum_rnd; - round #(.bits_in(36),.bits_out(18)) round_acc (.in(accum),.out(accum_rnd)); + wire [WIDTH:0] accum_rnd; + wire [WIDTH-1:0] accum_rnd_clip; + + wire stb_round; + + round_sd #(.WIDTH_IN(36),.WIDTH_OUT(WIDTH+1)) round_acc + (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round)); - reg [17:0] final_sum; + clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip (.in(accum_rnd), .out(accum_rnd_clip)); + + // Output always @(posedge clk) - if(bypass) - final_sum <= data_in_d1; - else if(go_d4) - final_sum <= accum_rnd; + begin + stb_out <= bypass ? stb_in : stb_round; + data_out <= bypass ? data_in : accum_rnd_clip; + end - assign data_out = final_sum; - always @(posedge clk) - if(rst) - stb_out <= 0; - else if(bypass) - stb_out <= stb_in_d1; - else - stb_out <= go_d4; endmodule // small_hb_dec diff --git a/fpga/usrp2/sdr_lib/tx_frontend.v b/fpga/usrp2/sdr_lib/tx_frontend.v new file mode 100644 index 000000000..d8525dd25 --- /dev/null +++ b/fpga/usrp2/sdr_lib/tx_frontend.v @@ -0,0 +1,86 @@ + +module tx_frontend + #(parameter BASE=0, + parameter WIDTH_OUT=16) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [23:0] tx_i, input [23:0] tx_q, input run, + output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b + ); + + // IQ balance --> DC offset --> rounding --> mux + + wire [23:0] i_dco, q_dco, i_ofs, q_ofs; + wire [WIDTH_OUT-1:0] i_final, q_final; + wire [7:0] mux_ctrl; + wire [35:0] corr_i, corr_q; + wire [23:0] i_bal, q_bal; + wire [17:0] mag_corr, phase_corr; + + setting_reg #(.my_addr(BASE+0), .width(24)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(i_dco),.changed()); + + setting_reg #(.my_addr(BASE+1), .width(24)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(q_dco),.changed()); + + setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(mag_corr),.changed()); + + setting_reg #(.my_addr(BASE+3),.width(18)) sr_3 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_corr),.changed()); + + setting_reg #(.my_addr(BASE+4), .width(8)) sr_4 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(mux_ctrl),.changed()); + + // IQ Balance + MULT18X18S mult_mag_corr + (.P(corr_i), .A(tx_i[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); + + MULT18X18S mult_phase_corr + (.P(corr_q), .A(tx_i[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) ); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_i + (.clk(clk), .rst(rst), + .in1(tx_i), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), + .sum(i_bal), .strobe_out()); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_q + (.clk(clk), .rst(rst), + .in1(tx_q), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), + .sum(q_bal), .strobe_out()); + + // DC Offset + add2_and_clip_reg #(.WIDTH(24)) add_dco_i + (.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out()); + + add2_and_clip_reg #(.WIDTH(24)) add_dco_q + (.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out()); + + // Rounding + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i + (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out()); + + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q + (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out()); + + // Mux + always @(posedge clk) + case(mux_ctrl[3:0]) + 0 : dac_a <= i_final; + 1 : dac_a <= q_final; + default : dac_a <= 0; + endcase // case (mux_ctrl[3:0]) + + always @(posedge clk) + case(mux_ctrl[7:4]) + 0 : dac_b <= i_final; + 1 : dac_b <= q_final; + default : dac_b <= 0; + endcase // case (mux_ctrl[7:4]) + +endmodule // tx_frontend diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index 8a02f0fb8..3c861fe08 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -30,7 +30,6 @@ module u1plus_core output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - output tx_underrun, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx, output [13:0] tx_i, output [13:0] tx_q, input [11:0] rx_i, input [11:0] rx_q, @@ -41,24 +40,31 @@ module u1plus_core localparam RXFIFOSIZE = 11; // 64 total regs in address space - localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) - localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) - localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) - localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) - localparam SR_TIME64 = 40; // 6 regs (+0 to +5) - localparam SR_CLEAR_RX_FIFO = 48; // 1 reg - localparam SR_CLEAR_TX_FIFO = 49; // 1 reg - localparam SR_GLOBAL_RESET = 50; // 1 reg - localparam SR_REG_TEST32 = 52; // 1 reg - - wire [7:0] COMPAT_NUM = 8'd3; + localparam SR_RX_CTRL0 = 0; // 9 regs (+0 to +8) + localparam SR_RX_DSP0 = 10; // 4 regs (+0 to +3) + localparam SR_RX_CTRL1 = 16; // 9 regs (+0 to +8) + localparam SR_RX_DSP1 = 26; // 4 regs (+0 to +3) + localparam SR_TX_CTRL = 32; // 4 regs (+0 to +3) + localparam SR_TX_DSP = 38; // 3 regs (+0 to +2) + + localparam SR_TIME64 = 42; // 6 regs (+0 to +5) + localparam SR_RX_FRONT = 48; // 5 regs (+0 to +4) + localparam SR_TX_FRONT = 54; // 5 regs (+0 to +4) + + localparam SR_REG_TEST32 = 60; // 1 reg + localparam SR_CLEAR_RX_FIFO = 61; // 1 reg + localparam SR_CLEAR_TX_FIFO = 62; // 1 reg + localparam SR_GLOBAL_RESET = 63; // 1 reg + + wire [7:0] COMPAT_NUM = 8'd5; wire wb_clk = clk_fpga; wire wb_rst, global_reset; wire pps_int; wire [63:0] vita_time, vita_time_pps; - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test; + wire [15:0] xfer_rate = 0; wire [7:0] test_rate; wire [3:0] test_ctrl; @@ -72,11 +78,11 @@ module u1plus_core wire [31:0] debug_vt; wire gpif_rst; - wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; reg [7:0] frames_per_packet; - assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; - assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + wire rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpif, tx_underrun_dsp, tx_underrun_gpif; + wire rx_overrun = rx_overrun_gpif | rx_overrun_dsp0 | rx_overrun_dsp1; + wire tx_underrun = tx_underrun_gpif | tx_underrun_dsp; setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), @@ -97,13 +103,12 @@ module u1plus_core wire [sw-1:0] m0_sel; wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; - wire [31:0] debug_gpmc; + wire [31:0] debug_gpif; wire [35:0] tx_data, rx_data, tx_err_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, tx_err_src_rdy, tx_err_dst_rdy; - wire bus_error; wire clear_tx, clear_rx; setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx @@ -128,36 +133,83 @@ module u1plus_core .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy), - .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + .tx_underrun(tx_underrun_gpif), .rx_overrun(rx_overrun_gpif), .frames_per_packet(frames_per_packet), .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl), .debug0(debug0), .debug1(debug1)); // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx; - wire strobe_rx, run_rx; - wire [31:0] debug_rx_dsp, vr_debug; + // RX ADC Frontend, does IQ Balance, DC Offset, muxing + + wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p + wire run_rx, run_rx0, run_rx1; + + rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,4'b00}),.adc_ovf_a(0), + .adc_b({rx_q,4'b00}),.adc_ovf_b(0), + .i_out(adc_i), .q_out(adc_q), .run(run_rx0 | run_rx1), .debug()); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 0 + + wire [31:0] sample_rx0; + wire strobe_rx0; + wire [35:0] vita_rx_data0; + wire vita_rx_src_rdy0, vita_rx_dst_rdy0; - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); + .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain0 + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun_dsp0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0), + .debug() ); - vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + + wire [31:0] sample_rx1; + wire strobe_rx1; + wire [35:0] vita_rx_data1; + wire vita_rx_src_rdy1, vita_rx_dst_rdy1; + + dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain1 (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun_dsp), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .rx_data_o(rx_data), .rx_dst_rdy_i(rx_dst_rdy), .rx_src_rdy_o(rx_src_rdy), - .debug(vr_debug) ); + .vita_time(vita_time), .overrun(rx_overrun_dsp1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1), + .debug() ); + + // ///////////////////////////////////////////////////////////////////////// + // RX Stream muxing + + fifo36_mux #(.prio(0)) mux_data_streams + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0), + .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); // /////////////////////////////////////////////////////////////////////////////////// // DSP TX - wire [15:0] tx_i_int, tx_q_int; + wire [23:0] tx_i_int, tx_q_int; wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), @@ -170,13 +222,16 @@ module u1plus_core .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(tx_i_int),.dac_b(tx_q_int), + .tx_i(tx_i_int),.tx_q(tx_q_int), .underrun(tx_underrun_dsp), .run(run_tx), .debug(debug_vt)); - - assign tx_i = tx_i_int[15:2]; - assign tx_q = tx_q_int[15:2]; - + + tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend + (.clk(wb_clk), .rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1), + .dac_a(tx_i), .dac_b(tx_q)); + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -277,8 +332,8 @@ module u1plus_core reg_test <= s0_dat_mosi; REG_RX_FRAMELEN : frames_per_packet <= s0_dat_mosi[7:0]; - REG_XFER_RATE : - xfer_rate <= s0_dat_mosi; + //REG_XFER_RATE : + //xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) assign test_ctrl = xfer_rate[11:8]; @@ -300,14 +355,16 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 1, UART // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock - + +/* simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart (.clk_i(wb_clk),.rst_i(wb_rst), .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), .rx_int_o(),.tx_int_o(), .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); - +*/ + // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI @@ -401,9 +458,8 @@ module u1plus_core // Debug circuitry assign debug_clk = { gpif_clk, clk_fpga }; - assign debug = debug0; + assign debug = 0; assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; - //assign {io_tx,io_rx} = {debug1}; endmodule // u1plus_core diff --git a/fpga/usrp2/top/E1x0/Makefile.passthru b/fpga/usrp2/top/E1x0/Makefile.passthru deleted file mode 100644 index f2d835608..000000000 --- a/fpga/usrp2/top/E1x0/Makefile.passthru +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = passthru -BUILD_DIR = $(abspath build$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpmc/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -passthru.v \ -passthru.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \ -$(GPMC_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile index dc0cd081e..02d7f006e 100755 --- a/fpga/usrp2/top/E1x0/core_compile +++ b/fpga/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/fpga/usrp2/top/E1x0/passthru.ucf b/fpga/usrp2/top/E1x0/passthru.ucf deleted file mode 100644 index 64e6f0440..000000000 --- a/fpga/usrp2/top/E1x0/passthru.ucf +++ /dev/null @@ -1,6 +0,0 @@ -NET "overo_gpio145" LOC = "C7" ; -NET "cgen_mosi" LOC = "E22" ; -NET "cgen_sclk" LOC = "J19" ; -NET "cgen_sen_b" LOC = "H20" ; -NET "fpga_cfg_din" LOC = "W17" ; -NET "fpga_cfg_cclk" LOC = "V17" ; diff --git a/fpga/usrp2/top/E1x0/passthru.v b/fpga/usrp2/top/E1x0/passthru.v deleted file mode 100644 index 486257366..000000000 --- a/fpga/usrp2/top/E1x0/passthru.v +++ /dev/null @@ -1,35 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module passthru - (input overo_gpio145, - output cgen_sclk, - output cgen_sen_b, - output cgen_mosi, - input fpga_cfg_din, - input fpga_cfg_cclk - ); - - assign cgen_sclk = fpga_cfg_cclk; - assign cgen_sen_b = overo_gpio145; - assign cgen_mosi = fpga_cfg_din; - - -endmodule // passthru diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v index adf42fd07..4f85b7d6e 100644 --- a/fpga/usrp2/top/E1x0/u1e.v +++ b/fpga/usrp2/top/E1x0/u1e.v @@ -36,11 +36,12 @@ module u1e output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + input overo_gpio65, input overo_gpio128, input overo_gpio145, output overo_gpio147, //aux SPI - output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + output overo_gpio144, output overo_gpio146, // Fifo controls input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO - input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO - input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio127, // Misc GPIO + input overo_gpio176, input overo_gpio163, input overo_gpio170, // Misc GPIO inout [15:0] io_tx, inout [15:0] io_rx, @@ -75,19 +76,29 @@ module u1e clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), .CLKDV(), .CLKFX(), .CLKFX180(), - .CLK2X(), .CLK2X180(), + .CLK2X(clk_2x), .CLK2X180(), .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); - + // ///////////////////////////////////////////////////////////////////////// // SPI wire mosi, sclk, miso; assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; - assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + //assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; //replaced by aux spi assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | - (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + //assign the aux spi to the cgen (bypasses wishbone) + assign cgen_sclk = overo_gpio65; + assign cgen_sen_b = overo_gpio128; + assign cgen_mosi = overo_gpio145; + wire proc_int; //re-purpose gpio for interrupt when we are not using aux spi + assign overo_gpio147 = (cgen_sen_b == 1'b0)? cgen_miso : proc_int; + + wire _cgen_sen_b; + //assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi // ///////////////////////////////////////////////////////////////////////// // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL @@ -130,25 +141,22 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Main U1E Core - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), + u1e_core u1e_core(.clk_fpga(clk_fpga), .bus_clk(clk_2x), .rst_fpga(~debug_pb), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), - .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .sclk(sclk), .sen({_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), - .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .tx_have_space(overo_gpio144), + .rx_have_data(overo_gpio146), .io_tx(io_tx), .io_rx(io_rx), .tx_i(tx_i), .tx_q(tx_q), .rx_i(DA), .rx_q(DB), - .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, - {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, - {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), - .pps_in(PPS_IN) ); + .pps_in(PPS_IN), .proc_int(proc_int) ); // ///////////////////////////////////////////////////////////////////////// // Local Debug diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v index 4c513587b..d481867e3 100644 --- a/fpga/usrp2/top/E1x0/u1e_core.v +++ b/fpga/usrp2/top/E1x0/u1e_core.v @@ -18,7 +18,7 @@ module u1e_core - (input clk_fpga, input rst_fpga, + (input clk_fpga, input bus_clk, input rst_fpga, output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, output debug_txd, input debug_rxd, @@ -31,29 +31,36 @@ module u1e_core output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + output tx_have_space, output rx_have_data, inout [15:0] io_tx, inout [15:0] io_rx, output [13:0] tx_i, output [13:0] tx_q, input [11:0] rx_i, input [11:0] rx_q, - input [11:0] misc_gpio, input pps_in + input pps_in, output proc_int ); localparam TXFIFOSIZE = 13; localparam RXFIFOSIZE = 13; // 64 total regs in address space - localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) - localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) - localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) - localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) - localparam SR_TIME64 = 40; // 6 regs (+0 to +5) - localparam SR_CLEAR_RX_FIFO = 48; // 1 reg - localparam SR_CLEAR_TX_FIFO = 49; // 1 reg - localparam SR_GLOBAL_RESET = 50; // 1 reg - localparam SR_REG_TEST32 = 52; // 1 reg - - wire [7:0] COMPAT_NUM = 8'd4; + localparam SR_RX_CTRL0 = 0; // 9 regs (+0 to +8) + localparam SR_RX_DSP0 = 10; // 4 regs (+0 to +3) + localparam SR_RX_CTRL1 = 16; // 9 regs (+0 to +8) + localparam SR_RX_DSP1 = 26; // 4 regs (+0 to +3) + localparam SR_ERR_CTRL = 30; // 1 reg + localparam SR_TX_CTRL = 32; // 4 regs (+0 to +3) + localparam SR_TX_DSP = 38; // 3 regs (+0 to +2) + + localparam SR_TIME64 = 42; // 6 regs (+0 to +5) + localparam SR_RX_FRONT = 48; // 5 regs (+0 to +4) + localparam SR_TX_FRONT = 54; // 5 regs (+0 to +4) + + localparam SR_REG_TEST32 = 60; // 1 reg + localparam SR_CLEAR_RX_FIFO = 61; // 1 reg + localparam SR_CLEAR_TX_FIFO = 62; // 1 reg + localparam SR_GLOBAL_RESET = 63; // 1 reg + + wire [7:0] COMPAT_NUM = 8'd5; wire wb_clk = clk_fpga; wire wb_rst, global_reset; @@ -69,9 +76,9 @@ module u1e_core wire set_stb; wire [31:0] debug_vt; - wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; - assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; - assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + wire rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + wire rx_overrun = rx_overrun_gpmc | rx_overrun_dsp0 | rx_overrun_dsp1; + wire tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), @@ -110,7 +117,7 @@ module u1e_core .in(set_data),.out(),.changed(clear_tx)); gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) - gpmc (.arst(wb_rst), + gpmc (.arst(wb_rst), .bus_clk(bus_clk), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), @@ -133,44 +140,82 @@ module u1e_core .test_rate(test_rate), .test_ctrl(test_ctrl), .debug(debug_gpmc)); - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug, vr_debug; // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx; - wire strobe_rx, run_rx; - wire [35:0] vita_rx_data; - wire vita_rx_src_rdy, vita_rx_dst_rdy; + // RX ADC Frontend, does IQ Balance, DC Offset, muxing + + wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p + wire run_rx, run_rx0, run_rx1; - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); + .adc_a({rx_i,4'b00}),.adc_ovf_a(0), + .adc_b({rx_q,4'b00}),.adc_ovf_b(0), + .i_out(adc_i), .q_out(adc_q), .run(run_rx0 | run_rx1), .debug()); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 0 - vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain + wire [31:0] sample_rx0; + wire strobe_rx0; + wire [35:0] vita_rx_data0; + wire vita_rx_src_rdy0, vita_rx_dst_rdy0; + + dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain0 (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun_dsp), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy), - .debug(vr_debug) ); + .vita_time(vita_time), .overrun(rx_overrun_dsp0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0), + .debug() ); - fifo36_mux #(.prio(0)) mux_err_stream + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + + wire [31:0] sample_rx1; + wire strobe_rx1; + wire [35:0] vita_rx_data1; + wire vita_rx_src_rdy1, vita_rx_dst_rdy1; + + dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain1 + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun_dsp1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1), + .debug() ); + + // ///////////////////////////////////////////////////////////////////////// + // RX Stream muxing + + fifo36_mux #(.prio(0)) mux_data_streams (.clk(wb_clk), .reset(wb_rst), .clear(0), - .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0), + .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1), .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - + // /////////////////////////////////////////////////////////////////////////////////// // DSP TX - wire [15:0] tx_i_int, tx_q_int; + wire [23:0] tx_i_int, tx_q_int; wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), @@ -183,13 +228,16 @@ module u1e_core .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(tx_i_int),.dac_b(tx_q_int), + .tx_i(tx_i_int),.tx_q(tx_q_int), .underrun(tx_underrun_dsp), .run(run_tx), .debug(debug_vt)); - - assign tx_i = tx_i_int[15:2]; - assign tx_q = tx_q_int[15:2]; - + + tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend + (.clk(wb_clk), .rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1), + .dac_a(tx_i), .dac_b(tx_q)); + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -255,7 +303,7 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; // ///////////////////////////////////////////////////////////////////////////////////// @@ -336,7 +384,7 @@ module u1e_core wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; i2c_master_top #(.ARST_LVL(1)) i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), .wb_ack_o(s3_ack),.wb_inta_o(), .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), @@ -361,6 +409,43 @@ module u1e_core .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); + //////////////////////////////////////////////////////////////////////////// + // FIFO to WB slave for async messages - Slave #5 + + //signals between fifo and buffer module + wire [35:0] _tx_err_data; + wire _tx_err_src_rdy, _tx_err_dst_rdy; + + fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) err_fifo( + .clk(wb_clk), .reset(wb_rst), .clear(wb_rst), + .datain(tx_err_data), .src_rdy_i(tx_err_src_rdy), .dst_rdy_o(tx_err_dst_rdy), + .dataout(_tx_err_data), .src_rdy_o(_tx_err_src_rdy), .dst_rdy_i(_tx_err_dst_rdy) + ); + + wire [31:0] err_status, err_data32; + //the buffer is 32 bits, but the data is 16, so mux based on the addr bit + assign s5_dat_miso = (s5_adr[1] == 1'b0)? err_data32[15:0] : err_data32[31:16]; + + buffer_int2 #(.BASE(SR_ERR_CTRL), .BUF_SIZE(5)) fifo_to_wb( + .clk(wb_clk), .rst(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .status(err_status), + // Wishbone interface to RAM + .wb_clk_i(wb_clk), .wb_rst_i(wb_rst), + .wb_we_i(s5_we), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_i({16'b0, s5_dat_mosi}), + .wb_dat_o(err_data32), .wb_ack_o(s5_ack), + // Write FIFO Interface + .wr_data_i(_tx_err_data), .wr_ready_i(_tx_err_src_rdy), .wr_ready_o(_tx_err_dst_rdy), + // Read FIFO Interface + .rd_data_o(), .rd_ready_o(), .rd_ready_i(1'b0) + ); + + //////////////////////////////////////////////////////////////////////////// + // Interrupts + + assign proc_int = (|err_status[1:0]); + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #8 + 9 @@ -369,7 +454,7 @@ module u1e_core (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); - + // ///////////////////////////////////////////////////////////////////////// // ATR Controller -- Slave #6 @@ -384,8 +469,9 @@ module u1e_core wire [31:0] reg_test32; + //this setting reg is persistent across resets, to check for fpga loaded setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + (.clk(wb_clk),.rst(/*wb_rst*/1'b0),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(reg_test32),.changed()); wb_readback_mux_16LE readback_mux_32 @@ -394,7 +480,7 @@ module u1e_core .word00(vita_time[63:32]), .word01(vita_time[31:0]), .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), - .word04(reg_test32), .word05(32'b0), + .word04(reg_test32), .word05(err_status), .word06(32'b0), .word07(32'b0), .word08(32'b0), .word09(32'b0), .word10(32'b0), .word11(32'b0), @@ -423,7 +509,7 @@ module u1e_core */ assign debug = debug_gpmc; - assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx, tx_i[11:0]}, + assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx0, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; assign debug_gpio_1 = debug_vt; @@ -431,7 +517,7 @@ module u1e_core /* assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, - {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, + {2'b0, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, {2'b0, bus_error, debug_gpmc[4:0] }, {misc_gpio[7:0]} }; */ diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v index 8a7c6ddee..e2142ad06 100644 --- a/fpga/usrp2/top/N2x0/u2plus_core.v +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -428,7 +428,7 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd6; + localparam compat_num = {16'd7, 16'd0}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -584,6 +584,17 @@ module u2plus_core .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); // ///////////////////////////////////////////////////////////////////////// + // ADC Frontend + wire [23:0] adc_i, adc_q; + + rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), + .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), + .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); + + // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; wire clear_rx0, strobe_rx0; @@ -594,7 +605,7 @@ module u2plus_core dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); @@ -622,7 +633,7 @@ module u2plus_core dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); @@ -676,6 +687,8 @@ module u2plus_core .debug(debug_extfifo), .debug2(debug_extfifo2) ); + wire [23:0] tx_i, tx_q; + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), @@ -686,10 +699,16 @@ module u2plus_core .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(dac_a),.dac_b(dac_b), + .tx_i(tx_i),.tx_q(tx_q), .underrun(underrun), .run(run_tx), .debug(debug_vt)); - + + tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .tx_i(tx_i), .tx_q(tx_q), .run(1'b1), + .dac_a(dac_a), .dac_b(dac_b)); + // /////////////////////////////////////////////////////////////////////////////////// // SERDES diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index ca9762ac5..2e3d41731 100644 --- a/fpga/usrp2/top/USRP2/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -283,7 +283,7 @@ module u2_core .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - ////////////////////////////////////////////////////////////////////////////////////////// + // //////////////////////////////////////////////////////////////////////////////////////// // Reset Controller system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), .ram_loader_rst_o(ram_loader_rst), @@ -433,7 +433,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd6; + localparam compat_num = {16'd7, 16'd0}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -583,6 +583,17 @@ module u2_core assign sd_dat_i[31:8] = 0; // ///////////////////////////////////////////////////////////////////////// + // ADC Frontend + wire [23:0] adc_i, adc_q; + + rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), + .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), + .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); + + // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; wire clear_rx0, strobe_rx0; @@ -593,7 +604,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); @@ -621,7 +632,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); @@ -673,6 +684,8 @@ module u2_core .debug(debug_extfifo), .debug2(debug_extfifo2) ); + wire [23:0] tx_i, tx_q; + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), @@ -683,10 +696,16 @@ module u2_core .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(dac_a),.dac_b(dac_b), + .tx_i(tx_i),.tx_q(tx_q), .underrun(underrun), .run(run_tx), .debug(debug_vt)); - + + tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .tx_i(tx_i), .tx_q(tx_q), .run(1'b1), + .dac_a(dac_a), .dac_b(dac_b)); + // /////////////////////////////////////////////////////////////////////////////////// // SERDES diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v index 542968afa..ac9f08fc8 100644 --- a/fpga/usrp2/vrt/vita_tx_chain.v +++ b/fpga/usrp2/vrt/vita_tx_chain.v @@ -29,7 +29,7 @@ module vita_tx_chain input [63:0] vita_time, input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i, - output [15:0] dac_a, output [15:0] dac_b, + output [23:0] tx_i, output [23:0] tx_q, output underrun, output run, output [31:0] debug); @@ -84,7 +84,7 @@ module vita_tx_chain (.clk(clk),.rst(reset), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample(sample_tx), .run(run), .strobe(strobe_tx), - .dac_a(dac_a),.dac_b(dac_b), + .tx_i(tx_i),.tx_q(tx_q), .debug(debug_tx_dsp) ); wire [35:0] flow_data, err_data_int; |