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| author | Josh Blum <josh@joshknows.com> | 2013-03-25 16:06:07 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2013-03-25 16:06:07 -0700 |
| commit | 404a84fcef665d262eee09ba10c841acdd7cbdf2 (patch) | |
| tree | 94108853d2aee5b3a87981a9f5df123178949af2 /fpga/usrp2/top/E1x0/Makefile.E110 | |
| parent | ee3082224f579da63b33f44f5275288032aac774 (diff) | |
| parent | 81447a405eab9cfe154ebcf1d809d95269ed349a (diff) | |
| download | uhd-404a84fcef665d262eee09ba10c841acdd7cbdf2.tar.gz uhd-404a84fcef665d262eee09ba10c841acdd7cbdf2.tar.bz2 uhd-404a84fcef665d262eee09ba10c841acdd7cbdf2.zip | |
Merge branch 'fpga_master' into maint
Diffstat (limited to 'fpga/usrp2/top/E1x0/Makefile.E110')
| -rw-r--r-- | fpga/usrp2/top/E1x0/Makefile.E110 | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110 index e5be8d2fa..c2d3e39e6 100644 --- a/fpga/usrp2/top/E1x0/Makefile.E110 +++ b/fpga/usrp2/top/E1x0/Makefile.E110 @@ -50,7 +50,6 @@ simulator "ISE Simulator (VHDL/Verilog)" \ TOP_SRCS = \ ../B100/u1plus_core.v \ E1x0.v \ -E1x0.ucf \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ |