Merge branch 'fpga_master' into maint

9 files changed, 58 insertions, 43 deletions

diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc.v b/fpga/usrp2/gpmc/fifo_to_gpmc.v
index 26443a702..93341975d 100644
--- a/fpga/usrp2/gpmc/fifo_to_gpmc.v
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc.v
@@ -46,7 +46,6 @@ module fifo_to_gpmc
    output reg data_available);
 
     //states for the GPMC side of things
-    wire [17:0] data_o;
     reg gpmc_state;
     reg [ADDR_WIDTH:1] addr;
     reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr;
@@ -147,14 +146,11 @@ module fifo_to_gpmc
 
     assign dst_rdy_o = fifo_state == FIFO_STATE_FILL;
 
-    //assign data from bram output
-    assign EM_D = data_o[15:0];
-
     //instantiate dual ported bram for async read + write
-    ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
+    ram_2port #(.DWIDTH(16),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
      (.clka(clk),.ena(1'b1),.wea(src_rdy_i && dst_rdy_o),
-      .addra({fifo_ptr[PTR_WIDTH-1:0], counter}),.dia(data_i),.doa(),
+      .addra({fifo_ptr[PTR_WIDTH-1:0], counter}),.dia(data_i[15:0]),.doa(),
       .clkb(EM_CLK),.enb(1'b1),.web(1'b0),
-      .addrb({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dib(18'h3ffff),.dob(data_o));
+      .addrb({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dib(18'h3ffff),.dob(EM_D));
 
 endmodule // fifo_to_gpmc
diff --git a/fpga/usrp2/gpmc/gpmc.v b/fpga/usrp2/gpmc/gpmc.v
index 2ba69d184..2f22889cc 100644
--- a/fpga/usrp2/gpmc/gpmc.v
+++ b/fpga/usrp2/gpmc/gpmc.v
@@ -58,8 +58,8 @@ module gpmc
    wire [35:0] 	  txb_data;
    wire 	  txb_src_rdy, txb_dst_rdy;
 
-   gpmc_to_fifo #(.ADDR_WIDTH(ADDR_WIDTH)) gpmc_to_fifo
-     (.EM_D(EM_D), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS4 & ~EM_NWE),
+   gpmc_to_fifo #(.ADDR_WIDTH(10), .LAST_ADDR(10'h3ff), .PTR_WIDTH(2)) gpmc_to_fifo
+     (.EM_D(EM_D), .EM_A(EM_A[10:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS4 & ~EM_NWE),
       .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
       .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
       .have_space(tx_have_space));
@@ -112,8 +112,8 @@ module gpmc
    wire [35:0] 	  ctrlb_data;
    wire 	  ctrlb_src_rdy, ctrlb_dst_rdy;
 
-   gpmc_to_fifo #(.PTR_WIDTH(5), .ADDR_WIDTH(5)) ctrl_gpmc_to_fifo
-     (.EM_D(EM_D), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS6 & ~EM_NWE & (EM_A[ADDR_WIDTH:6] == 0)),
+   gpmc_to_fifo #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) ctrl_gpmc_to_fifo
+     (.EM_D(EM_D), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS6 & ~EM_NWE),
       .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
       .data_o(ctrl18_data), .src_rdy_o(ctrl18_src_rdy), .dst_rdy_i(ctrl18_dst_rdy),
       .have_space(/*always*/));
@@ -149,12 +149,12 @@ module gpmc
       .f36_datain(respb_data), .f36_src_rdy_i(respb_src_rdy), .f36_dst_rdy_o(respb_dst_rdy),
       .f19_dataout({resp_dummy,resp18_data}), .f19_src_rdy_o(resp18_src_rdy), .f19_dst_rdy_i(resp18_dst_rdy) );
 
-   fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH), .LAST_ADDR(10'h00f)) resp_fifo_to_gpmc
+   fifo_to_gpmc #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) resp_fifo_to_gpmc
      (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
       .data_i(resp18_data), .src_rdy_i(resp18_src_rdy), .dst_rdy_o(resp18_dst_rdy),
-      .EM_D(EM_D_ctrl), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS6 & ~EM_NOE),
+      .EM_D(EM_D_ctrl), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS6 & ~EM_NOE),
       .data_available(resp_have_data));
-
+//*
     assign debug = {
         EM_D,
         //resp18_data[15:0], //16
@@ -163,5 +163,5 @@ module gpmc
         EM_NCS4, EM_NCS6, EM_NWE, EM_NOE, //4
         EM_CLK, resp_have_data //2
     };
-
+//*/
 endmodule // gpmc
diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo.v b/fpga/usrp2/gpmc/gpmc_to_fifo.v
index 3932b81ac..d1897faec 100644
--- a/fpga/usrp2/gpmc/gpmc_to_fifo.v
+++ b/fpga/usrp2/gpmc/gpmc_to_fifo.v
@@ -36,18 +36,15 @@
 ////////////////////////////////////////////////////////////////////////
 
 module gpmc_to_fifo
-  #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter XFER_OFFSET = 2)
+  #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter LAST_ADDR = 10'h3ff)
   (input [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_WE,
    input clk, input reset, input clear, input arst,
    output [17:0] data_o, output src_rdy_o, input dst_rdy_i,
    output reg have_space);
 
     //states for the GPMC side of things
-    wire [17:0] data_i;
     reg gpmc_state;
-    reg [15:0] vita_len;
     reg [ADDR_WIDTH:1] addr;
-    wire [ADDR_WIDTH:1] last_addr = {vita_len[ADDR_WIDTH-2:0], 1'b0} - 1'b1 + XFER_OFFSET;
     reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr;
     localparam GPMC_STATE_START = 0;
     localparam GPMC_STATE_FILL = 1;
@@ -55,6 +52,8 @@ module gpmc_to_fifo
     //states for the FIFO side of things
     reg [1:0] fifo_state;
     reg [ADDR_WIDTH-1:0] counter;
+    reg [ADDR_WIDTH-1:0] last_counter;
+    reg [ADDR_WIDTH-1:0] last_xfer;
     reg [PTR_WIDTH:0] fifo_ptr;
     localparam FIFO_STATE_CLAIM = 0;
     localparam FIFO_STATE_EMPTY = 1;
@@ -75,15 +74,14 @@ module gpmc_to_fifo
             case(gpmc_state)
 
             GPMC_STATE_START: begin
-                if (data_i[16]) begin
+                if (EM_A == 0) begin
                     gpmc_state <= GPMC_STATE_FILL;
-                    vita_len <= EM_D;
                     next_gpmc_ptr <= gpmc_ptr + 1;
                 end
             end
 
             GPMC_STATE_FILL: begin
-                if (data_i[17]) begin
+                if (addr == LAST_ADDR) begin
                     gpmc_state <= GPMC_STATE_START;
                     gpmc_ptr <= next_gpmc_ptr;
                     addr <= 0;
@@ -123,14 +121,14 @@ module gpmc_to_fifo
         if (reset | clear) begin
             fifo_state <= FIFO_STATE_CLAIM;
             fifo_ptr <= 0;
-            counter <= XFER_OFFSET;
+            counter <= 0;
         end
         else begin
             case(fifo_state)
 
             FIFO_STATE_CLAIM: begin
                 if (bram_available_to_empty && data_o[16]) fifo_state <= FIFO_STATE_PRE;
-                counter <= XFER_OFFSET;
+                counter <= 0;
             end
 
             FIFO_STATE_PRE: begin
@@ -142,7 +140,7 @@ module gpmc_to_fifo
                 if (src_rdy_o && dst_rdy_i && data_o[17]) begin
                     fifo_state <= FIFO_STATE_CLAIM;
                     fifo_ptr <= fifo_ptr + 1;
-                    counter <= XFER_OFFSET;
+                    counter <= 0;
                 end
                 else if (src_rdy_o && dst_rdy_i) begin
                     counter <= counter + 1;
@@ -157,16 +155,23 @@ module gpmc_to_fifo
 
     assign src_rdy_o = fifo_state == FIFO_STATE_EMPTY;
 
-    //assign data and frame bits to bram input
-    assign data_i[15:0] = EM_D;
-    assign data_i[16] = (addr == XFER_OFFSET);
-    assign data_i[17] = (addr == last_addr);
-
     //instantiate dual ported bram for async read + write
-    ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
+    ram_2port #(.DWIDTH(16),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
      (.clka(~EM_CLK),.ena(1'b1),.wea(EM_WE),
-      .addra({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dia(data_i),.doa(),
+      .addra({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dia(EM_D),.doa(),
       .clkb(clk),.enb(enable),.web(1'b0),
-      .addrb({fifo_ptr[PTR_WIDTH-1:0], counter}),.dib(18'h3ffff),.dob(data_o));
+      .addrb({fifo_ptr[PTR_WIDTH-1:0], counter}),.dib(18'h3ffff),.dob(data_o[15:0]));
+
+    //store the vita length -> last xfer count
+    always @(posedge clk) begin
+        if (src_rdy_o && dst_rdy_i && data_o[16]) begin
+            last_xfer <= {data_o[ADDR_WIDTH-2:0], 1'b0};
+        end
+    end
+
+    //logic for start and end of frame
+    always @(posedge clk) if (enable) last_counter <= counter;
+    assign data_o[17] = !data_o[16] && ((last_counter + 1'b1) == last_xfer);
+    assign data_o[16] = last_counter == 0;
 
 endmodule // gpmc_to_fifo
diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf
index c4404e1d0..7b212a9a6 100644
--- a/fpga/usrp2/top/B100/timing.ucf
+++ b/fpga/usrp2/top/B100/timing.ucf
@@ -15,5 +15,10 @@ INST "GPIF_SLOE" TNM = gpif_net_out;
 INST "GPIF_SLRD" TNM = gpif_net_out;
 INST "GPIF_PKTEND" TNM = gpif_net_out;
 
-TIMEGRP "gpif_net_in" OFFSET = IN 7 ns VALID 14 ns BEFORE "IFCLK" RISING;
+TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "IFCLK" RISING;
 TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING;
+
+TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
+
+NET PPS_IN TIG;
+NET debug_led* TIG;
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index 423282153..302565101 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -71,7 +71,7 @@ module u1plus_core
     localparam SR_GPIO         = 224;     // 5
 
     //compatibility number -> increment when the fpga has been sufficiently altered
-    localparam compat_num = {16'd11, 16'd1}; //major, minor
+    localparam compat_num = {16'd11, 16'd2}; //major, minor
 
     //assign run signals used for ATR logic
     wire [NUM_RX_DSPS-1:0] run_rx_n;
diff --git a/fpga/usrp2/top/E1x0/E1x0.v b/fpga/usrp2/top/E1x0/E1x0.v
index 8efb056e9..44129ce92 100644
--- a/fpga/usrp2/top/E1x0/E1x0.v
+++ b/fpga/usrp2/top/E1x0/E1x0.v
@@ -59,10 +59,20 @@ module E1x0
    wire clk_fpga;
    wire reset;
 
-   reg async_reset;
-   always @(negedge EM_CLK) begin
-        async_reset <= ~EM_NCS6 && ~EM_NWE && (EM_A[9:2] == 8'hff) && EM_D[0];
-   end
+   reg                 por_rst;
+   reg [7:0]   por_counter = 8'h0;
+
+   always @(posedge clk_fpga)
+     if (por_counter != 8'h55)
+       begin
+          por_counter <= por_counter + 8'h1;
+          por_rst <= 1'b1;
+       end
+     else por_rst <= 1'b0;
+
+   wire async_reset;
+   cross_clock_reader #(.WIDTH(1)) read_gpio_reset
+       (.clk(clk_fpga), .rst(por_rst), .in(cgen_sen_b & ~cgen_sclk), .out(async_reset));
 
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110
index e5be8d2fa..c2d3e39e6 100644
--- a/fpga/usrp2/top/E1x0/Makefile.E110
+++ b/fpga/usrp2/top/E1x0/Makefile.E110
@@ -50,7 +50,6 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 TOP_SRCS = \
 ../B100/u1plus_core.v \
 E1x0.v \
-E1x0.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf
index 7d3d9e090..1483c2a05 100644
--- a/fpga/usrp2/top/E1x0/timing.ucf
+++ b/fpga/usrp2/top/E1x0/timing.ucf
@@ -14,8 +14,8 @@ INST "EM_NCS6" TNM = gpmc_net;
 INST "EM_NWE" TNM = gpmc_net;
 INST "EM_NOE" TNM = gpmc_net;
 
-TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 12 ns BEFORE "EM_CLK" FALLING;
-TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read
+TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 10 ns BEFORE "EM_CLK" FALLING;
+#TIMEGRP "gpmc_net_out" OFFSET = OUT 13 ns AFTER "EM_CLK" RISING; //2 clock cyc per read
 
 #constrain interrupt lines
 NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space
diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common
index 3b71e7b13..bd999f007 100644
--- a/fpga/usrp2/top/Makefile.common
+++ b/fpga/usrp2/top/Makefile.common
@@ -55,7 +55,7 @@ $(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST)
 
 $(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST)
 	@echo $@
-	$(ISE_HELPER) "Generate Programming File"
+	$(ISE_HELPER) "Generate Programming File" 2>&1 | tee $(BUILD_DIR)/build.log
 	touch $@
 
 $(MCS_FILE): $(BIN_FILE)