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author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/sdr_lib/integrate.v | |
parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/sdr_lib/integrate.v')
-rw-r--r-- | fpga/usrp2/sdr_lib/integrate.v | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/fpga/usrp2/sdr_lib/integrate.v b/fpga/usrp2/sdr_lib/integrate.v new file mode 100644 index 000000000..db33de979 --- /dev/null +++ b/fpga/usrp2/sdr_lib/integrate.v @@ -0,0 +1,38 @@ +module integrate + #(parameter INPUTW = 16, + parameter ACCUMW = 32, + parameter OUTPUTW = 16) + + (input clk_i, + input rst_i, + input ena_i, + + input dump_i, + input [INPUTW-1:0] data_i, + + output reg stb_o, + output reg [OUTPUTW-1:0] integ_o + ); + + wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i}; + reg [ACCUMW-1:0] accum; + + always @(posedge clk_i) + if (rst_i | ~ena_i) + begin + accum <= 0; + integ_o <= 0; + end + else + if (dump_i) + begin + integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW]; + accum <= data_ext; + end + else + accum <= accum + data_ext; + + always @(posedge clk_i) + stb_o <= dump_i; + +endmodule // integrate |