From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/sdr_lib/integrate.v | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 fpga/usrp2/sdr_lib/integrate.v

(limited to 'fpga/usrp2/sdr_lib/integrate.v')

diff --git a/fpga/usrp2/sdr_lib/integrate.v b/fpga/usrp2/sdr_lib/integrate.v
new file mode 100644
index 000000000..db33de979
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/integrate.v
@@ -0,0 +1,38 @@
+module integrate
+  #(parameter INPUTW = 16,
+    parameter ACCUMW = 32,
+    parameter OUTPUTW = 16)
+
+   (input clk_i,
+    input rst_i,
+    input ena_i,
+
+    input dump_i,
+    input [INPUTW-1:0] data_i,
+
+    output reg stb_o,
+    output reg [OUTPUTW-1:0] integ_o
+   );
+   
+   wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i};
+   reg  [ACCUMW-1:0] accum;
+
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       begin
+	  accum <= 0;
+	  integ_o <= 0;
+       end
+     else
+       if (dump_i)
+	 begin
+	    integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW];
+	    accum <= data_ext;
+	 end
+       else
+	 accum <= accum + data_ext;
+
+   always @(posedge clk_i)
+     stb_o <= dump_i;
+   
+endmodule // integrate
-- 
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