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author | Josh Blum <josh@joshknows.com> | 2011-07-08 12:17:54 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2011-07-08 12:17:54 -0700 |
commit | 17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9 (patch) | |
tree | e2d0d39d6b44b72c759b8be1380b2024de50bdf6 /fpga/usrp2/sdr_lib/add2_and_clip_reg.v | |
parent | 60933a242cce0b1ec45e9f948e3da9ab72b2fd90 (diff) | |
parent | 4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4 (diff) | |
download | uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.tar.gz uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.tar.bz2 uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.zip |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/sdr_lib/add2_and_clip_reg.v')
-rw-r--r-- | fpga/usrp2/sdr_lib/add2_and_clip_reg.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/fpga/usrp2/sdr_lib/add2_and_clip_reg.v b/fpga/usrp2/sdr_lib/add2_and_clip_reg.v new file mode 100644 index 000000000..8073b3b54 --- /dev/null +++ b/fpga/usrp2/sdr_lib/add2_and_clip_reg.v @@ -0,0 +1,25 @@ + +module add2_and_clip_reg + #(parameter WIDTH=16) + (input clk, + input rst, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + input strobe_in, + output reg [WIDTH-1:0] sum, + output reg strobe_out); + + wire [WIDTH-1:0] sum_int; + + add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + if(rst) + sum <= 0; + else if(strobe_in) + sum <= sum_int; + + always @(posedge clk) + strobe_out <= strobe_in; + +endmodule // add2_and_clip_reg |