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authorJosh Blum <josh@joshknows.com>2011-07-08 12:17:54 -0700
committerJosh Blum <josh@joshknows.com>2011-07-08 12:17:54 -0700
commit17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9 (patch)
treee2d0d39d6b44b72c759b8be1380b2024de50bdf6 /fpga/usrp2/sdr_lib/add2_and_clip_reg.v
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Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/sdr_lib/add2_and_clip_reg.v')
-rw-r--r--fpga/usrp2/sdr_lib/add2_and_clip_reg.v25
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diff --git a/fpga/usrp2/sdr_lib/add2_and_clip_reg.v b/fpga/usrp2/sdr_lib/add2_and_clip_reg.v
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+++ b/fpga/usrp2/sdr_lib/add2_and_clip_reg.v
@@ -0,0 +1,25 @@
+
+module add2_and_clip_reg
+ #(parameter WIDTH=16)
+ (input clk,
+ input rst,
+ input [WIDTH-1:0] in1,
+ input [WIDTH-1:0] in2,
+ input strobe_in,
+ output reg [WIDTH-1:0] sum,
+ output reg strobe_out);
+
+ wire [WIDTH-1:0] sum_int;
+
+ add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int));
+
+ always @(posedge clk)
+ if(rst)
+ sum <= 0;
+ else if(strobe_in)
+ sum <= sum_int;
+
+ always @(posedge clk)
+ strobe_out <= strobe_in;
+
+endmodule // add2_and_clip_reg