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| author | Josh Blum <josh@joshknows.com> | 2010-10-14 16:55:56 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-10-14 16:55:56 -0700 |
| commit | 26b7de0ac0cd64946582b2d52ab0bb3555156039 (patch) | |
| tree | 5dc670eaaab60bf2bda90d905210bc9432cecea3 /fpga/usrp2/extramfifo/fifo_extram36_tb.build | |
| parent | 71e1763332141603e9edba097fd19b00e9a76ab8 (diff) | |
| parent | ee03f1d4acf5c7d3359c86baba5085660d63ebae (diff) | |
| download | uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.tar.gz uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.tar.bz2 uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.zip | |
Merge branch 'flow_control' into flow_ctrl
Diffstat (limited to 'fpga/usrp2/extramfifo/fifo_extram36_tb.build')
| -rwxr-xr-x | fpga/usrp2/extramfifo/fifo_extram36_tb.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.build b/fpga/usrp2/extramfifo/fifo_extram36_tb.build new file mode 100755 index 000000000..ac9369758 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram36_tb.build @@ -0,0 +1 @@ +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v |