diff options
57 files changed, 10817 insertions, 256 deletions
diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs index 7b29225ca..a59696d15 100644 --- a/fpga/usrp2/coregen/Makefile.srcs +++ b/fpga/usrp2/coregen/Makefile.srcs @@ -16,4 +16,8 @@ fifo_xlnx_16x19_2clk.v \ fifo_xlnx_16x19_2clk.xco \ fifo_xlnx_16x40_2clk.v \ fifo_xlnx_16x40_2clk.xco \ +fifo_xlnx_512x36_2clk_36to18.v \ +fifo_xlnx_512x36_2clk_36to18.xco \ +fifo_xlnx_512x36_2clk_18to36.v \ +fifo_xlnx_512x36_2clk_18to36.xco \ )) diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp index 810d64dac..4c9201aff 100644 --- a/fpga/usrp2/coregen/coregen.cgp +++ b/fpga/usrp2/coregen/coregen.cgp @@ -1,20 +1,22 @@ -# Date: Thu Sep 3 17:40:48 2009 -SET addpads = False -SET asysymbol = False +# Date: Mon Jul 26 21:55:33 2010 + +SET addpads = false +SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False +SET createndf = false SET designentry = Verilog SET device = xc3s2000 SET devicefamily = spartan3 SET flowvendor = Other -SET formalverification = False -SET foundationsym = False +SET formalverification = false +SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 -SET removerpms = False +SET removerpms = false SET simulationfiles = Behavioral SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/matt/coregen/tmp +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = /tmp/ +# CRC: 394da717 diff --git a/fpga/usrp2/coregen/fifo_generator_ug175.pdf b/fpga/usrp2/coregen/fifo_generator_ug175.pdf Binary files differindex 2c3e3c200..5fba6029c 100644 --- a/fpga/usrp2/coregen/fifo_generator_ug175.pdf +++ b/fpga/usrp2/coregen/fifo_generator_ug175.pdf diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise new file mode 100644 index 000000000..c18cf3bf0 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_18to36.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_18to36.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc new file mode 100644 index 000000000..d9277b0c3 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$45640<,[o}e~g`n;"2*726&;$:,)?40493456712:;<=>?01274>6789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123454<80;0=>5>.130?46=AGZ^X7OKDSC?=?699l1:<7GAPTV9twi`Wog`Rzgrdqk8<<76;?0==4FNQWW>uthoVl~`aQ{hsgplZgt{lx044?>37855<NFY__6}|`g^dvhiYs`{oxdR`jg`vf8<<76830==4@UURVP?bf|hUhcx`{<883:4e<990DYY^ZT;uq[agsiVidycz39;2=57=6>3CE\XZ5DHC?50<76890=;4@UURVP?BHI5;>6=0>2:3;>LHW]]0oec2>7;2=5>433;98?<?42;KMTPR=L@ZJ0<4?>0086?IR\Y__6IA_A=394;753:81EC^ZT;FJF956294:?6==:NWWTPR=LFH7?<4?>06873<H]]Z^X7j`uu>01?69l29x>=>?ff662(363=>08=HI1097>LHW]]0OE]L33;2=57=32F__\XZ5DNRA86<7681=>6864:4:=32<09:;866J8@38=1=>8939748;;845=44<13CE\XZ5AEFQF9>=87;n744FNQWW>uthoVof|ywPtipfwm:?29499675IORVP?vugnUna}zv_ujqavnXizyn~y27:1<11>?=AGZ^X7~}of]fiur~W}byi~fPndebp`:?294:n675OTVSQQ<ulVnjxlQlotlw8=<76;1J>55NDEPB858?3HNO^L2>>99B@ATF4;437LJKR@>0:==FLMXJ0907;@FGVD:2611JHI\N<7<;?DBCZH6<255NDEPB8=8f3HNO^L26:1<;?DBCZH62255NDEPA858?3HNO^O2>>99B@ATE4;437LJKRC>0:==FLMXI0907;@FGVG:2611JHI\M<7<;?DBCZK6<2l5NDEPA8=<7611JHI\M<9<0?DJK12KXUCMPRDE0?GS502H^_RGAFN38G7=DM880OEKLK^NJG@HTMV^R\H<4CH68GIMF<2IGGO=4CMP:?FIJE@^_II?;;BMQAZABFLXJXDAA_HLEK2=DZLK_II?4D39GG7=CA?1OEL2?>69GMD:687=0HDO310<4?AOF4885;6JFA=30:2=CAH6:8374DHC?50<76>1OEL2>5?48@LG;97<0HDO32?48@LG;;7<0HDO34?48@LG;=7<0HDO36?48@LG;?7<0HDO38?48@LG;17<0HDL30?58@LD;994<7IGM<03=3>BNJ5;92:5KIC>27;1<L@H7=908;EKA8439?2NBN1?9>69GMG:6?7=0HDL319<4?AOE4835:6JFB=3=3>BNJ58;2:5KIC>15;1<L@H7>?08;EKA8759?2NBN1<;>69GMG:5=7=0HDL327<4?AOE4;=5;6JFB=0;:2=CAK695384DH@?6;1<L@H7?=06;EKA867=87=0HDL330<5?AOE4:4=7IGM<5<5?AOE4<4=7IGM<7<5?AOE4>4=7IGM<9<5?AOE404<7IG_A=2==>BNXH6:6=08;EKSE979?2NB\O2?>69GMUD;97=0HD^M<3<:?AOWJ591<394DHRA86813MEJ0=08;EMB8469?2NDM1?>>69GKD:6:7=0HBO312<4?AIF48>556J@A=36>5803MEJ0<;16:FLE979>2NDM1<16:FLE959>2NDM1:16:FLE939>2NDM1816:FLE919>2NDM1616:FLE9?9?2NDMR\JG79GKG:76>1OCO2>0?58@JD;984<7IAM<00=3>BHJ5;82:5KOC>20;1<LFH7=808;EMA8409?2NDN1?8>69GKG:607=0HBL318<5?AIE484<7IAM<32=3>BHJ58:2:5KOC>16;1<LFH7>>08;EMA8729?2NDN1<:>69GKG:5>7=0HBL326<4?AIE4;25;6J@B=0::3=CGK692:5KOC>04;?<LFH7?<4?>69GKG:497<0HBL33?48@JD;<7<0HBL35?48@JD;>7<0HBL37?48@JD;07<0HBL39?58@JDXZLM<7IA_A=2==>BHXH6:6=08;EMSE979?2ND\O2?>69GKUD;97=0HB^M<3<:?AIWJ591<394DNRA86843LDJ?6KABc9FJZCDKVXNMIm4EO]FGFYPZ@^N>6H=2:D;1>@FDZO97KJ<;GF@0>@CKL90JI^;;GFSA1=AL[O?7KH7009D7>AIL81B>6G?2:K26>O5:2C846GAIUR\45><AGC_\R>>8:KMMQVX8;20ECG[P^20<>OIA]ZT<964IOKWTZ6202CEEY^P07:8MKOSXV:<56GAIUQWEQC03@DBXR>?7:KMMQY79>1BBDZP0358MKOSW99<7D@FT^273>OIA]U;9:5FNHV\431<AGC_S=98;HLJPZ6??2CEEYQ?969JJLRX8H=0ECG[_1@4?LHN\V:H;6GAIU]3@2=NF@^T<H94IOKW[5@03@DBXR??7:KMMQY69>1BBDZP1358MKOSW89<7D@FT^373>OIA]U:9:5FNHV\531<AGC_S<98;HLJPZ7??2CEEYQ>969JJLRX9H=0ECG[_0@4?LHN\V;H;6GAIU]2@2=NF@^T=H94IOKW[4@03@DBXR<?7:KMMQY59>1BBDZP2358MKOSW;9<7D@FT^073>OIA]U99:5FNHV\631<AGC_S?98;HLJPZ4??2CEEYQ=969JJLRX:H=0ECG[_3@4?LHN\V8H;6GAIU]1@2=NF@^T>H94IOKW[7@03@DBXR=?7:KMMQY49>1BBDZP3358MKOSW:9<7D@FT^173>OIA]U89:5FNHV\731<AGC_S>98;HLJPZ5??2CEEYQ<969JJLRX;H=0ECG[_2@4?LHN\V9H;6GAIU]0@2=NF@^T?H94IOKW[6@13@DBXRO9;HLJPZD43@D]>6BF2:NL2>JHIMOO;6B@GHABH1=K]];?7A[[259OQQ533E__8;5CUU6\@0=J[NEE96CZXB[`?Hgmg{\n~~g`nb9Nmkiu^lxxeb`<;O226>H6<2D:<=:4N0220>H68;>0B<><4:L2412<F8:>86@>0768J460<2D:<5:4N02:7>H69=1E=<>;;O3251=I988?7C?>359M54233G;:995A1047?K76?=1E=<6;;O32=6=I9;>0B<<?4:L2642<F88986@>2268J443<2D:>8:4N0050>H6:>>0B<<73:L271=I9:;87C?;3:L216=I9?>0B<8;3:L236=I9190B<7=;O00?K47;2D9=>5A2318J7543G8??6@=529M635<F;=87C<73:L1=7=I;:1E?=<4N408J24<F090B4?<;O;17>H>;:1E59=4N870?K?1;2D2;>5A9918J<?a3GHTNX]_IO]SVJVT?2DNXZA]K09L6>IL92Z?7]O]T`9SMKYE]ZCOTo5_IO]AQVHFEL90\_K>;P38V`=UIDH::R]>8^Q02d=UMHNTJD\\Tb9QADBX_@N_DROl;SGB@ZQNL]BTN<5\129PMHYDGEFB_DAA_BJFGN0<[F_YOH94SSTBHZG03ZX]MAQM4:QPVD2<[ZXI86ZVPD11?P6(o{l%~k!hcy,`hn~(EqeySjPpovq[beXpfx;<=>PRdqvhq74:2_;#j|i.sd,cf~)keas#@v`r^pg[uhszVmhSua}0122[Wct}e~:??5Z0.eqb+ta'nis"nbdx.O{kwYulVzexQhc^zlv567:VXnxb{1208Q5)`zo$yj"ilx/aoo})JpfxT~iQnup\cfYg{:;<>Q]erwop4553\:$kh!rg-dg}(ddbr$Aua}_sf\tkruWniTtb|?016\V`urd};8>6[?/fpe*w`(ojr%oaew/LzlvZtcWyd~Ril_ymq4562W[oxyaz>339V4*aun'xm#jmw.bnh|*Kg{UyhR~ats]dgZ~hz9:;:R\jstnw564<]9%l~k }f.e`|+ekcq%Ftb|Pre]sjqtXojUsc>?06]Qavsk|8997X> gsd-vc)`kq$h`fv Mymq[rtXxg~ySjmPxnp3456XZly~`y?<2:W3+bta&{l$knv!cmi{+H~hzV}yS}`{r^e`[}iu89::S_k|umv277=R8&myj#|i/fa{*fjlp&GscQxr^rmpwY`kVrd~=>?2^Pfwpjs9:80Y=!hrg,qb*adp'iggu!Bxnp\swYwf}xTknQwos2346YUmzgx<==;T2,cw`)zo%lou lljz,I}iuW~xT|cz}_fa\|jt789>T^h}zlu306>S7'nxm"h gbz-gim'Drd~Ry}_qlwvZadWqey<=>:_Sgpqir6;;1^<"i}f/pe+be&jf`t"Cwos]tvZvi|{UloRv`r1232ZTb{|f=><4U1-dvc(un&mht#mcky-N|jtX{U{by|Pgb]{kw678>UYi~{ct011?P6(o{l%~k!hcy,`hn~(EqeySz|Ppovq[beXpfx;<=6PRdqvhq7592_;#j|i.sd,cf~)keas#jPpovq[goi4949=6[?/fpe*w`(ojr%oaew/sf\tkruWkce0<0=1:W3+bta&{l$knv!cmi{+wbXxg~ySoga<3<15>S7'nxm"h gbz-gim'{nT|cz}_ckm868592_;#j|i.sd,cf~)keas#jPpovq[goi4=49=6[?/fpe*w`(ojr%oaew/sf\tkruWkce080=1:W3+bta&{l$knv!cmi{+wbXxg~ySoga<7<15>S7'nxm"h gbz-gim'{nT|cz}_ckm828592_;#j|i.sd,cf~)keas#jPpovq[goi4149<6[?/fpe*w`(ojr%oaew/sf\tkruWkceS=<?;T2,cw`)zo%lou lljz,vaYwf}xTnd`P1328Q5)`zo$yj"ilx/aoo})ulVzexQmio]165=R8&myj#|i/fa{*fjlp&xoS}`{r^`jjZ5582_;#j|i.sd,cf~)keas#jPpovq[goiW=8;7X> gsd-vc)`kq$h`fv re]sjqtXj`dT9?>4U1-dvc(un&mht#mcky-q`Zvi|{UiecQ9219V4*aun'xm#jmw.bnh|*tcWyd~Rlfn^514>S7'nxm"h gbz-gim'{nT|cz}_ckm[=413\:$kh!rg-dg}(ddbr$~iQnup\flhXpfx;<=>=7:W3+bta&{l$knv!cmi{+wbXxg~ySoga_ymq45679;<0Y=!hrg,qb*adp'iggu!}d^rmpwYeagUsc>?0004?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\|jt789;:>;5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbRv`r123671<]9%l~k }f.e`|+ekcq%yhR~ats]amkYg{:;<??=6:W3+bta&{l$knv!cmi{+wbXxg~ySoga_ymq4564:>1^<"i}f/pe+be&jf`t"|k_qlwvZdnfVrd~=>?3305?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\|jt789>9;6[?/fpe*w`(ojr%oaew/sf\tkruWkceSua}0127570<]9%l~k }f.e`|+ekcq%yhR~ats]amkYg{:;<8<8;T2,cw`)zo%lou lljz,vaYwf}xTnd`Pxnp34536:?1^<"i}f/pe+be&jf`t"|k_qlwvZdnfVrd~=>?63:8Q5)`zo$yj"ilx/aoo})ulVzexQmio]{kw678?;:>:5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbRv`r123274e3\:$kh!rg-dg}(ddbr$~iQnup\flhXpfx;<=8Pbef363=R8&myj#|i/fa{*fjlp&xoS}`{r^`jjZ~hz9:;;?94U1-dvc(un&mht#mcky-q`Zvi|{UiecQwos23427582_;#j|i.sd,cf~)keas#jPpovq[be;878;7X> gsd-vc)`kq$h`fv re]sjqtXoj6:2?>4U1-dvc(un&mht#mcky-q`Zvi|{Ulo1<1219V4*aun'xm#jmw.bnh|*tcWyd~Ril<2<14>S7'nxm"h gbz-gim'{nT|cz}_fa?0;473\:$kh!rg-dg}(ddbr$~iQnup\cf:26;:0Y=!hrg,qb*adp'iggu!}d^rmpwY`k5<5>=5Z0.eqb+ta'nis"nbdx.pg[uhszVmh0:0=0:W3+bta&{l$knv!cmi{+wbXxg~ySjm38?3e?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb]35c=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[47a3\:$kh!rg-dg}(ddbr$~iQnup\cfY59o1^<"i}f/pe+be&jf`t"|k_qlwvZadW:;m7X> gsd-vc)`kq$h`fv re]sjqtXojU?=k5Z0.eqb+ta'nis"nbdx.pg[uhszVmhS8?i;T2,cw`)zo%lou lljz,vaYwf}xTknQ91g9V4*aun'xm#jmw.bnh|*tcWyd~Ril_63e?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb];63=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumn6;2?84U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde?5;413\:$kh!rg-dg}(ddbr$~iQnup\cfYf{{ol0?0=6:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfc959:?1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyij2;>348Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`a;=78=7X> gsd-vc)`kq$h`fv re]sjqtXojUjkh<7<12>S7'nxm"h gbz-gim'{nT|cz}_fa\evtbo5=5>;5Z0.eqb+ta'nis"nbdx.pg[uhszVmhSl}}ef>;:73<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmT<?;4U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\573<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmT>?;4U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\773<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmT8?;4U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\173<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmT:?;4U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\373<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmT4?74U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\`4:76;30Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiPd0>2:7?<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<2=>3;8Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`aXl8682?74U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\`4:36;30Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiPd0>6:7?<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<29>3;8Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`aXl86<2?74U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\`4:?6;20Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiPd0]36==R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=R?=8:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb6W;837X> gsd-vc)`kq$h`fv re]sjqtXojUjkh_e3\77><]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<Q;299V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc9V?946[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^f2[34?3\:$kh!rg-dg}(ddbr$~iQnup\cfYf{{olSi?P73:8Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`aXl8U3>85Z0.eqb+ta'nis"nbdx.pg[uhszVmhSua}012360=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[}iu89::>85Z0.eqb+ta'nis"nbdx.pg[uhszVmhSua}012160=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[}iu89:8>85Z0.eqb+ta'nis"nbdx.pg[uhszVmhSua}012760=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[}iu89:>>85Z0.eqb+ta'nis"nbdx.pg[uhszVmhSua}012560=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[}iu89:<><5Z0.eqb+ta'nis"nbdx.uq[uhszVhbb1?1209V4*aun'xm#jmw.bnh|*quWyd~Rlfn=0=64=R8&myj#|i/fa{*fjlp&}yS}`{r^`jj959:81^<"i}f/pe+be&jf`t"y}_qlwvZdnf5>5><5Z0.eqb+ta'nis"nbdx.uq[uhszVhbb1;1209V4*aun'xm#jmw.bnh|*quWyd~Rlfn=4=64=R8&myj#|i/fa{*fjlp&}yS}`{r^`jj919:81^<"i}f/pe+be&jf`t"y}_qlwvZdnf525><5Z0.eqb+ta'nis"nbdx.uq[uhszVhbb171219V4*aun'xm#jmw.bnh|*quWyd~Rlfn^314>S7'nxm"h gbz-gim'~xT|cz}_ckm[7473\:$kh!rg-dg}(ddbr${Qnup\flhX;;:0Y=!hrg,qb*adp'iggu!xr^rmpwYeagU?>=5Z0.eqb+ta'nis"nbdx.uq[uhszVhbbR;=0:W3+bta&{l$knv!cmi{+rtXxg~ySoga_703?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\376<]9%l~k }f.e`|+ekcq%|~R~ats]amkY?:91^<"i}f/pe+be&jf`t"y}_qlwvZdnfV39:6[?/fpe*w`(ojr%oaew/vp\tkruWkceSua}012362=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ~hz9:;<<<9;T2,cw`)zo%lou lljz,swYwf}xTnd`Pxnp34575?2_;#j|i.sd,cf~)keas#z|Ppovq[goiWqey<=>>1348Q5)`zo$yj"ilx/aoo})pzVzexQmio]{kw678;8<7X> gsd-vc)`kq$h`fv ws]sjqtXj`dTtb|?010263=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ~hz9:;??94U1-dvc(un&mht#mcky-tvZvi|{UiecQwos234645>2_;#j|i.sd,cf~)keas#z|Ppovq[goiWqey<=>;269V4*aun'xm#jmw.bnh|*quWyd~Rlfn^zlv567<88=7X> gsd-vc)`kq$h`fv ws]sjqtXj`dTtb|?01713>S7'nxm"h gbz-gim'~xT|cz}_ckm[}iu89:>=?84U1-dvc(un&mht#mcky-tvZvi|{UiecQwos23434?3\:$kh!rg-dg}(ddbr${Qnup\flhXpfx;<=8>1358Q5)`zo$yj"ilx/aoo})pzVzexQmio]{kw678?89n6[?/fpe*w`(ojr%oaew/vp\tkruWkceSua}0125[gbc8;<0Y=!hrg,qb*adp'iggu!xr^rmpwYeagUsc>?0604?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\|jt789=:>=5Z0.eqb+ta'nis"nbdx.uq[uhszVmh0=0=0:W3+bta&{l$knv!cmi{+rtXxg~ySjm31?03?P6(o{l%~k!hcy,`hn~({U{by|Pgb>1:76<]9%l~k }f.e`|+ekcq%|~R~ats]dg959:91^<"i}f/pe+be&jf`t"y}_qlwvZad4=49<6[?/fpe*w`(ojr%oaew/vp\tkruWni793<?;T2,cw`)zo%lou lljz,swYwf}xTkn29>328Q5)`zo$yj"ilx/aoo})pzVzexQhc=5=65=R8&myj#|i/fa{*fjlp&}yS}`{r^e`8=8582_;#j|i.sd,cf~)keas#z|Ppovq[be;17;m7X> gsd-vc)`kq$h`fv ws]sjqtXojU;=k5Z0.eqb+ta'nis"nbdx.uq[uhszVmhS<?i;T2,cw`)zo%lou lljz,swYwf}xTknQ=1g9V4*aun'xm#jmw.bnh|*quWyd~Ril_23e?P6(o{l%~k!hcy,`hn~({U{by|Pgb]75c=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[07a3\:$kh!rg-dg}(ddbr${Qnup\cfY19o1^<"i}f/pe+be&jf`t"y}_qlwvZadW>;m7X> gsd-vc)`kq$h`fv ws]sjqtXojU3=k5Z0.eqb+ta'nis"nbdx.uq[uhszVmhS4<9;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd8585>2_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnk1?1279V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqab:56;<0Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hi33?05?P6(o{l%~k!hcy,`hn~({U{by|Pgb]bwwc`4=49:6[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg=7=63=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumn6=2?84U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde?3;413\:$kh!rg-dg}(ddbr${Qnup\cfYf{{ol050=6:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfc9?9:<1^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQ?249V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabY6:<1^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQ=249V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabY4:<1^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQ;249V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabY2:<1^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQ9249V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabY0:<1^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQ7249V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabY>:01^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1=3=6<=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=1<1289V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc9595>45Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g5929:01^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1=7=6<=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=181289V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc95=5>45Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g59>9:01^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1=;=6==R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=R?=8:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfcZb6W;837X> gsd-vc)`kq$h`fv ws]sjqtXojUjkh_e3\77><]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmTh<Q;299V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc9V?946[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg^f2[34?3\:$kh!rg-dg}(ddbr${Qnup\cfYf{{olSi?P73:8Q5)`zo$yj"ilx/aoo})pzVzexQhc^cpv`aXl8U3>55Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g5Z?5=2_;#j|i.sd,cf~)keas#z|Ppovq[beXpfx;<=>=5:W3+bta&{l$knv!cmi{+rtXxg~ySjmPxnp34575=2_;#j|i.sd,cf~)keas#z|Ppovq[beXpfx;<=<=5:W3+bta&{l$knv!cmi{+rtXxg~ySjmPxnp34555=2_;#j|i.sd,cf~)keas#z|Ppovq[beXpfx;<=:=5:W3+bta&{l$knv!cmi{+rtXxg~ySjmPxnp34535=2_;#j|i.sd,cf~)keas#z|Ppovq[beXpfx;<=8=5:W3+bta&{l$knv!cmi{+rtXxg~ySjmPxnp34515=2_;#j|i.sd,cf~)keas#z|Ppovq[beXpfx;<=6<0:W3+bta&{l$ka>!re-dv4(un~l#@czx^PBIZTCWLDTJZH[200e?P6(o{l%~k!hl1,q`*au9'xm{kz Mlw{[WGJW[OLCXZPEO326a=R8&myj#|i/fn3*wb(o{;%~kyit.avvwYao~Tyo{e=2=6a=R8&myj#|i/fn3*wb(o{;%~kyit.avvwYao~Tyo{e=3=6f=R8&myj#|i/fn3*wb(o{;%~kyit.avvwYao~Tyo{e^21g>S7'nxm"h gm2-va)`z8$yjzh{/bwqvZ`pn}Uxxlzj_016?P6(o{l%~k!hl1,q`*au9'xm{kz ctpq[cqa|VymykPmtz3457;879=7X> gsd-vc)`d9$yh"i}1/pescr(k|xySkyit^qweqcXe|r;<=?30?301>S7'nxm"h gm2-va)`z8$yjzh{/bwqvZ`pn}Uxxlzj_lw{45664848:6[?/fpe*w`(oe:%~i!hr0,qbr`s'jy~Rhxfu]ppdrbWds<=>><0<26==R8&myj#|i/fn3*wb(o{;%~kyit.gntqXn~lSkl=7:W3+bta&{l$ka>!re-dv4(un~l#hctx]escrXa;l0Y=!hrg,qb*ak8'xo#j|>.sdtbq)bey~rSkyit^k\ip~789:8<6[?/fpe*w`(oe:%~i!hr0,qbr`s'lg{xtQiwgv\mZkrp9:;<<<6;T2,cw`)zo%l`= }d.eqev(u{}y$o=!laspzj`r;87827X> gsd-vc)`d9$yh"i}ar,qwqu(k9%hm|vndv?5;4>3\:$kh!rg-dh5(ul&mym~ }suq,g5)di{xrbhz32?0:?P6(o{l%~k!hl1,q`*auiz$yy} c1-`ewt~fl~7?3<i;T2,cw`)zo%l`= }d.eqev(u{}y$o=!hmtz-ch]7U'mf=#c>2g9V4*aun'xm#jb?.sf,cwgt&{y"m?/fov|+ajS8W%k`}!mr0e?P6(o{l%~k!hl1,q`*auiz$yy} c1-dip~)odQ9Q#ibs/op6c=R8&myj#|i/fn3*wb(o{kx"}{s.a3+bkrp'mfW>S!glq-iv4a3\:$kh!rg-dh5(ul&mym~ }suq,g5)`e|r%k`U;]/enw+kt::1^<"i}f/pe+bj7&{n$ko|.sqww*e7';7<3<<;T2,cw`)zo%l`= }d.eqev(u{}y$o=!y1=3=66=R8&myj#|i/fn3*wb(o{kx"}{s.a3+s7;:7887X> gsd-vc)`d9$yh"i}ar,qwqu(k9%}=1=1229V4*aun'xm#jb?.sf,cwgt&{y"m?/w3?0;4e3\:$kh!rg-dh5(ul&mym~ }suq,g5)q9V:Tmcj?01226g=R8&myj#|i/fn3*wb(o{kx"}{s.a3+s7X9Vkeh=>?000a?P6(o{l%~k!hl1,q`*auiz$yy} c1-u5Z4Xign;<=>>2c9V4*aun'xm#jb?.sf,cwgt&{y"m?/w3\7Zgil9:;<<<m;T2,cw`)zo%l`= }d.eqev(u{}y$o=!y1^6\jjr789::>45Z0.eqb+ta'nf;"j gscp*wus{&i:#no}rxlfp969:01^<"i}f/pe+bj7&{n$ko|.sqww*e6'jky~t`jt=3=6<=R8&myj#|i/fn3*wb(o{kx"}{s.a2+fguzpdnx1<1289V4*aun'xm#jb?.sf,cwgt&{y"m>/bcqv|hb|595>k5Z0.eqb+ta'nf;"j gscp*wus{&i:#jczx/en_5[)od;%a<<i;T2,cw`)zo%l`= }d.eqev(u{}y$o<!hmtz-ch]6U'mf#c|2g9V4*aun'xm#jb?.sf,cwgt&{y"m>/fov|+ajS;W%k`}!mr0e?P6(o{l%~k!hl1,q`*auiz$yy} c0-dip~)odQ8Q#ibs/op6c=R8&myj#|i/fn3*wb(o{kx"}{s.a2+bkrp'mfW9S!glq-iv443\:$kh!rg-dh5(ul&mym~ }suq,g4)q95:5>>5Z0.eqb+ta'nf;"j gscp*wus{&i:#{?31?00?P6(o{l%~k!hl1,q`*auiz$yy} c0-u5949::1^<"i}f/pe+bj7&{n$ko|.sqww*e6';7?3<<;T2,cw`)zo%l`= }d.eqev(u{}y$o<!y1=6=6g=R8&myj#|i/fn3*wb(o{kx"}{s.a2+s7X8Vkeh=>?000a?P6(o{l%~k!hl1,q`*auiz$yy} c0-u5Z7Xign;<=>>2c9V4*aun'xm#jb?.sf,cwgt&{y"m>/w3\6Zgil9:;<<<m;T2,cw`)zo%l`= }d.eqev(u{}y$o<!y1^1\ekb789::>o5Z0.eqb+ta'nf;"j gscp*wus{&i:#{?P4^llp567888;7X> gsd-vc)`d9$yh"i}ar,qwqu(kfg{<?>4U1-dvc(un&mg<#|k/fpbw+tt|z%hc`~>289V4*aun'xm#jb?.sf,cwgt&{y"|nm^gntqXnkUb?=5Z0.eqb+ta'nf;"j gscp*wus{&xjaRkbpu{\bgYnWfx;<=><1:W3+bta&{l$ka>!re-dvdu)zz~x#ob_dosp|YajVcTc>?01317>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|;>0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|Vidycz>259V4*aun'xm#jb?.sf,vuhsz&Ghcx`{_bmvjq45<2_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfex><;;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw072<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~>>95Z0.eqb+ta'nf;"j rqlwv*Kdg|dSnaznu410>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|>8?7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{83;8Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkrXkp6;2?m4U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\g|:76Vx>45Z0.eqb+ta'nf;"j rqlwv*Kdg|dSnaznu]`}979:j1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQly=3=[wr512_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfexRmv<3<1g>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vir0?0Pru0:?P6(o{l%~k!hl1,q`*twf}x$Anaznu]`kphsWjs7?3<l;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[f;;7Uyx?74U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\g|:36;i0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPcx>7:Zts:01^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQly=7=6f=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Uhu1;1_sv1=>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vir0;0=c:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmpZe~4?4T~y<6;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[f;?78h7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_b{?3;Yu|;k0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPxnp?4;4f3\:$kh!rg-dh5(ul&x{by| MbmvjqYdg|dSua}<0<1e>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vrd~1<12`9V4*aun'xm#jb?.sf,vuhsz&Ghcx`{_bmvjqYg{682?o4U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\|jt;<78j7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_ymq8085i2_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfexRv`r=4=6d=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Usc28>3c8Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkrXpfx743<k;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[}iu414T~y?i;T2,cw`)zo%l`= }d.psjqt(kfex1>11g9V4*aun'xm#jb?.sf,vuhsz&idycz31?3e?P6(o{l%~k!hl1,q`*twf}x$ob{at=0=5c=R8&myj#|i/fn3*wb(zyd~"m`uov?7;7a3\:$kh!rg-dh5(ul&x{by| cnwmp9299o1^<"i}f/pe+bj7&{n$~}`{r.alqkr;=7;m7X> gsd-vc)`d9$yh"|nup,gjsi|5<5=k5Z0.eqb+ta'nf;"j rqlwv*eh}g~7;3?i;T2,cw`)zo%l`= }d.psjqt(kfex1611d9V4*aun'xm#jb?.sf,vuhsz&idyczP00g8Q5)`zo$yj"ic0/pg+wvi|{%hcx`{_03f?P6(o{l%~k!hl1,q`*twf}x$ob{at^02a>S7'nxm"h gm2-va)uxg~y#naznu]05`=R8&myj#|i/fn3*wb(zyd~"m`uov\04c<]9%l~k }f.eo4+tc'{zex!lotlw[07b3\:$kh!rg-dh5(ul&x{by| cnwmpZ06m2_;#j|i.sd,ci6)zm%y|cz}/bmvjqY09l1^<"i}f/pe+bj7&{n$~}`{r.alqkrX0;80Y=!hrg,qb*ak8'xo#~ats-`kphsWm;7<3<=;T2,cw`)zo%l`= }d.psjqt(kfexRj><0<16>S7'nxm"h gm2-va)uxg~y#naznu]g5949:;1^<"i}f/pe+bj7&{n$~}`{r.alqkrXl8682?<4U1-dvc(un&mg<#|k/srmpw)dg|dSi?34?01?P6(o{l%~k!hl1,q`*twf}x$ob{at^f28085:2_;#j|i.sd,ci6)zm%y|cz}/bmvjqYc95<5>?5Z0.eqb+ta'nf;"j rqlwv*eh}g~Th<28>308Q5)`zo$yj"ic0/pg+wvi|{%hcx`{_e3?<;463\:$kh!rg-dh5(ul&x{by| cnwmpZb6W98:7X> gsd-vc)`d9$yh"|nup,gjsi|Vn:S<<>;T2,cw`)zo%l`= }d.psjqt(kfexRj>_302?P6(o{l%~k!hl1,q`*twf}x$ob{at^f2[6463\:$kh!rg-dh5(ul&x{by| cnwmpZb6W=8:7X> gsd-vc)`d9$yh"|nup,gjsi|Vn:S8<>;T2,cw`)zo%l`= }d.psjqt(kfexRj>_702?P6(o{l%~k!hl1,q`*twf}x$ob{at^f2[2463\:$kh!rg-dh5(ul&x{by| cnwmpZb6W18?7X> gsd-vc)`d9$yh"|nup,gjsi|Vddx=>?12d8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-NeabXl`lmS}`{r^rb`Zgcl9:;<Rmv<1<0b>S7'nxm"h gm2-sw)`hy%k}h!wsre+HgclVnbjkQnup\tdbXimn;<=>Pcx>2:6`<]9%l~k }f.eo4+qu'n}j#if/uqtc)JimnThdhi_qlwvZvflVkoh=>?0^az8784n2_;#j|i.sd,ci6){%l{l}!gqd-swva'DkohRjffg]sjqtXxhnTmij?012\g|:46:l0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%FmijPdhde[uhszVzjhRokd1234Ze~4=48j6[?/fpe*w`(oe:%{!hw`q-cu`){zm#@okd^fjbcYwf}xT|ljPaef3456Xkp6>2>h4U1-dvc(un&mg<#y}/fubw+awn'}y|k!Baef\`l`aWyd~R~nd^cg`5678Vir0;0<f:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/Lcg`ZbnnoU{by|Pp`f\eab789:Tot28>2d8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-NeabXl`lmS}`{r^rb`Zgcl9:;<Rmv<9<0b>S7'nxm"h gm2-sw)`hy%k}h!wsre+HgclVnbjkQnup\tdbXimn;<=>Pcx>::17<]9%l~k }f.eo4+qu'n}j#if/uqtc)JimnThdhi_qlwvZvflVkoh=>?0^nvp9776=:0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%FmijPdhde[uhszVzjhRokd1234Zjr|5;58;5Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"Cnde]gmc`Xxg~yS}ok_`fg4567We0<0PIOT\416<]9%l~k }f.eo4+qu'n}j#if/uqtc)JimnThdhi_qlwvZvflVkoh=>?0^nvp949<91^<"i}f/pe+bj7&~x$kzo|.fre*rtwn&GjhiQkigd\tkruWykoSljk0123[iss4:4?<6[?/fpe*w`(oe:%{!hw`q-cu`){zm#@okd^fjbcYwf}xT|ljPaef3456Xd|~783:?;T2,cw`)zo%l`= xr.etev(`xo$|~}h M`fg[aoanVzexQae]b`a6789Ugyy2:>528Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-NeabXl`lmS}`{r^rb`Zgcl9:;<Rbzt=4=05=R8&myj#|i/fn3*rt(o~kx"j~i.vpsb*KflmUoekhPpovq[ugcWhno<=>?_mww828382_;#j|i.sd,ci6){%l{l}!gqd-swva'DkohRjffg]sjqtXxhnTmij?012\hpr;07>;7X> gsd-vc)`d9$|~"ixar,dtc(pzyl$Aljk_ekebZvi|{U{miQnde2345Yk}}6229?4U1-dvc(un&mg<#y}/fubw+awn'}y|k!Baef\`l`aWyd~R~nd^cg`5678Vrd~1??>528Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-NeabXl`lmS}`{r^rb`Zgcl9:;<Rv`r=3=05=R8&myj#|i/fn3*rt(o~kx"j~i.vpsb*KflmUoekhPpovq[ugcWhno<=>?_ymq878382_;#j|i.sd,ci6){%l{l}!gqd-swva'DkohRjffg]sjqtXxhnTmij?012\|jt;;7>;7X> gsd-vc)`d9$|~"ixar,dtc(pzyl$Aljk_ekebZvi|{U{miQnde2345Yg{6?29>4U1-dvc(un&mg<#y}/fubw+awn'}y|k!Baef\`l`aWyd~R~nd^cg`5678Vrd~1;1419V4*aun'xm#jb?.vp,crgt&nzm"z|f.Ob`aYcaolT|cz}_qcg[dbc89:;Sua}<7<74>S7'nxm"h gm2-sw)`hy%k}h!wsre+HgclVnbjkQnup\tdbXimn;<=>Pxnp?3;273\:$kh!rg-dh5(pz&m|m~ hpg,tvu`(EhnoSigif^rmpwYwimUjhi>?01]{kw:?6=:0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%FmijPdhde[uhszVzjhRokd1234Z~hz535?=5Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"jffg]sjqtXxhn7==0=f:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/ekebZvi|{U{mi2>>3d8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-gmc`Xxg~yS}ok<3<1b>S7'nxm"h gm2-sw)`hy%k}h!wsre+aoanVzexQae>0:7`<]9%l~k }f.eo4+qu'n}j#if/uqtc)caolT|cz}_qcg8185n2_;#j|i.sd,ci6){%l{l}!gqd-swva'mcmjR~ats]sea:26;l0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%oekhPpovq[ugc4?49j6[?/fpe*w`(oe:%{!hw`q-cu`){zm#igif^rmpwYwim6<2?h4U1-dvc(un&mg<#y}/fubw+awn'}y|k!kigd\tkruWyko050=f:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/ekebZvi|{U{mi26>3g8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-gmc`Xxg~yS}ok_00e?P6(o{l%~k!hl1,tv*apiz$l|k xrqd,`l`aWyd~R~nd^336`=R8&myj#|i/fn3*rt(o~kx"j~i.vpsb*bnnoU{by|Pp`f\67c<]9%l~k }f.eo4+qu'n}j#if/uqtc)caolT|cz}_qcg[64b3\:$kh!rg-dh5(pz&m|m~ hpg,tvu`(l`lmS}`{r^rb`Z25m2_;#j|i.sd,ci6){%l{l}!gqd-swva'mcmjR~ats]seaY2:l1^<"i}f/pe+bj7&~x$kzo|.fre*rtwn&nbjkQnup\tdbX>;o0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%oekhPpovq[ugcW>8n7X> gsd-vc)`d9$|~"ixar,dtc(pzyl$hdhi_qlwvZvflV29i6[?/fpe*w`(oe:%{!hw`q-cu`){zm#igif^rmpwYwimU2?55Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"jffg]sjqtXxhnTmij?012?5584?2_;#j|i.sd,ci6){%l{l}!gqd-swva'mcmjR~ats]seaYflm:;<=2>>258Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-gmc`Xxg~yS}ok_`fg45674;48;6[?/fpe*w`(oe:%{!hw`q-cu`){zm#igif^rmpwYwimUjhi>?01>0:61<]9%l~k }f.eo4+qu'n}j#if/uqtc)caolT|cz}_qcg[dbc89:;090<7:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/ekebZvi|{U{miQnde2345:26:=0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%oekhPpovq[ugcWhno<=>?<7<03>S7'nxm"h gm2-sw)`hy%k}h!wsre+aoanVzexQae]b`a67896<2>94U1-dvc(un&mg<#y}/fubw+awn'}y|k!kigd\tkruWykoSljk01238=84?2_;#j|i.sd,ci6){%l{l}!gqd-swva'mcmjR~ats]seaYflm:;<=26>3c8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-svjaXn|fgSd==;T2,cw`)zo%l`= xr.etev(`xo$|~}h psmd[cskdVcTaxv?01100>S7'nxm"h gm2-sw)`hy%k}h!wsre+uthoVl~`aQf_lw{4564989?7X> gsd-vc)`d9$|~"ixar,dtc(pzyl$|ah_gwohZoXe|r;<==>92:8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-svjaXn|fgSdQbuy23467>WZ];??5Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"~}of]eqijXaVddx=>?13;8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.abvwim}6;2?74U1-dvc(un&mg<#y}/fubw+qt|z%h="mnrs{maq:66;30Y=!hrg,qb*ak8'}y#jyns/uppv)d9&ij~waeu>1:7?<]9%l~k }f.eo4+qu'n}j#y|tr-`5*efz{seiy2<>3d8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.enq}(`eR:V"jc>.l31b>S7'nxm"h gm2-sw)`hy%{~z|/b3,chs&ngP=P hmr,nw7`<]9%l~k }f.eo4+qu'n}j#y|tr-`5*aj}q$laV<R.fop*hu5n2_;#j|i.sd,ci6){%l{l}!wrvp+f7(ods"jcT3\,div(j{;l0Y=!hrg,qb*ak8'}y#jyns/uppv)d9&mfyu hmZ6^*bkt&dy9?6[?/fpe*w`(oe:%{!hw`q-svrt'j;$z<2?>318Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.t28485;2_;#j|i.sd,ci6){%l{l}!wrvp+f7(~8692?=4U1-dvc(un&mg<#y}/fubw+qt|z%h="x><2<17>S7'nxm"h gm2-sw)`hy%{~z|/b3,r4:36;h0Y=!hrg,qb*ak8'}y#jyns/uppv)d9&|:S=Qnne234575j2_;#j|i.sd,ci6){%l{l}!wrvp+f7(~8U:Sl`k012357d<]9%l~k }f.eo4+qu'n}j#y|tr-`5*p6W;Ujbi>?0131f>S7'nxm"h gm2-sw)`hy%{~z|/b3,r4Y4Whdo<=>?13`8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.t2[1Yffm:;<=?=9:W3+bta&{l$ka>!ws-dsdu)z~x#n< c`pq}kcs494956[?/fpe*w`(oe:%{!hw`q-svrt'j8$ol|}yogw848512_;#j|i.sd,ci6){%l{l}!wrvp+f4(khxyuck{<3<1=>S7'nxm"h gm2-sw)`hy%{~z|/b0,gdtuqgo0>0=f:W3+bta&{l$ka>!ws-dsdu)z~x#n< glw{*bk\8T$la< b13d8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.enq}(`eR;V"jc|.lq1b>S7'nxm"h gm2-sw)`hy%{~z|/b0,chs&ngP>P hmr,nw7`<]9%l~k }f.eo4+qu'n}j#y|tr-`6*aj}q$laV=R.fop*hu5n2_;#j|i.sd,ci6){%l{l}!wrvp+f4(ods"jcT4\,div(j{;90Y=!hrg,qb*ak8'}y#jyns/uppv)d:&|:0=0=3:W3+bta&{l$ka>!ws-dsdu)z~x#n< v0>2:75<]9%l~k }f.eo4+qu'n}j#y|tr-`6*p64;49?6[?/fpe*w`(oe:%{!hw`q-svrt'j8$z<2<>318Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.t28185j2_;#j|i.sd,ci6){%l{l}!wrvp+f4(~8U;Sl`k012357d<]9%l~k }f.eo4+qu'n}j#y|tr-`6*p6W8Ujbi>?0131f>S7'nxm"h gm2-sw)`hy%{~z|/b0,r4Y5Whdo<=>?13`8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.t2[6Yffm:;<=?=b:W3+bta&{l$ka>!ws-dsdu)z~x#n< v0]7[dhc89:;=?>4U1-dvc(un&mg<#y}/fubw+qt|z%hc`~>219V4*aun'xm#jb?.vp,crgt&~y"m`mq014>S7'nxm"h gm2-sw)`hy%{~z|/bmnt64c3\:$kh!rg-dh5(pz&m|m~ xsuq,cd`)k:%hm|vndv?4;4c3\:$kh!rg-dh5(pz&m|m~ xsuq,cd`)k:%hm|vndv?5;4c3\:$kh!rg-dh5(pz&m|m~ xsuq,cd`)k:%hm|vndv?6;4c3\:$kh!rg-dh5(pz&m|m~ xsuq,cd`)k:%hm|vndv?7;543\:$kh!rg-dh5(pz&m|m~ xsuq,cd`)k:%laxv!glY3Y+aj9'g:?>5Z0.eqb+ta'nf;"z| gvcp*rus{&mjj#m</fov|+ajS8W%k`}!mr10?P6(o{l%~k!hl1,tv*apiz$|y} g`d-g6)`e|r%k`U=]/enw+kt;:1^<"i}f/pe+bj7&~x$kzo|.vqww*afn'i8#jczx/en_6[)ody%a~=<;T2,cw`)zo%l`= xr.etev(p{}y$klh!c2-dip~)odQ?Q#ibs/op62=R8&myj#|i/fn3*rt(o~kx"z}{s.ebb+e4';7<3<8;T2,cw`)zo%l`= xr.etev(p{}y$klh!c2-u5979:>1^<"i}f/pe+bj7&~x$kzo|.vqww*afn'i8#{?32?04?P6(o{l%~k!hl1,tv*apiz$|y} g`d-g6)q9595>:5Z0.eqb+ta'nf;"z| gvcp*rus{&mjj#m</w3?0;4a3\:$kh!rg-dh5(pz&m|m~ xsuq,cd`)k:%}=R>Paof34566:o1^<"i}f/pe+bj7&~x$kzo|.vqww*afn'i8#{?P1^cm`567888m7X> gsd-vc)`d9$|~"ixar,twqu(ohl%o>!y1^0\ekb789::>k5Z0.eqb+ta'nf;"z| gvcp*rus{&mjj#m</w3\7Zgil9:;<<<i;T2,cw`)zo%l`= xr.etev(p{}y$klh!c2-u5Z2Xign;<=>>2b9V4*aun'xm#jb?.vp,crgt&~y"|nm^coijusWog`Rg<4:W3+bta&{l$ka>!ws-dsdu)z~x#ob_`nnkvrXn|fgSdQbuy2345523\:$kh!rg-dh5(pz&m|m~ xsuq,vdkXiegdyQiumn\mZkrp9:;<<=m;T2,cw`)zo%l`= xr.etev(p{}y$~lcPamolwqYa}efTeR``t12354YNF_U;>55Z0.eqb+ta'nf;"z| gvcp*rus{&xjaRhzlm]efZo5=2_;#j|i.sd,ci6){%l{l}!wrvp+wgjWog`Rg=d:W3+bta&{l$ka>!ws-dsdu)z~x#ob_gwohZoXe|r;<=>=e:W3+bta&{l$ka>!ws-dsdu)z~x#ob_gwohZoXe|r;<=>>1e9V4*aun'xm#jb?.vp,vdkX{UnbRg>1g9V4*aun'xm#jb?.vp,vdkX{UnbRg>_000?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphs:=1^<"i}f/pe+bj7&~x${}`{r.O`kphsWje~by?=4:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmp7433\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|d??:4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov761=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}?986[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at707?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphs?;>0Y=!hrg,qb*ak8'}y#z~ats-Ngjsi|Vidycz7259V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjq?512_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRmv<1<1g>S7'nxm"h gm2-sw)pxg~y#@m`uov\gjsi|Vir0=0Pru0:?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphsWjs7=3<l;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw[f;97Uyx?74U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov\g|:56;i0Y=!hrg,qb*ak8'}y#z~ats-Ngjsi|VidyczPcx>1:Zts:01^<"i}f/pe+bj7&~x${}`{r.O`kphsWje~byQly=1=6f=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}Uhu1=1_sv1=>S7'nxm"h gm2-sw)pxg~y#@m`uov\gjsi|Vir090=c:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmpZe~4=4T~y<6;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw[f;=78h7X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{_b{?1;Yu|;30Y=!hrg,qb*ak8'}y#z~ats-Ngjsi|VidyczPcx>5:7e<]9%l~k }f.eo4+qu'~zex!BcnwmpZeh}g~Tot29>^pw6<=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}Uhu1912b9V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYdq5=5Sz=9:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmpZe~4149o6[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^az8=8Xz}8j7X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{_ymq8585i2_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRv`r=3=6d=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}Usc2=>3c8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXpfx7?3<n;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw[}iu4=49m6[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^zlv939:h1^<"i}f/pe+bj7&~x${}`{r.O`kphsWje~byQwos>5:7g<]9%l~k }f.eo4+qu'~zex!BcnwmpZeh}g~Ttb|37?0b?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphsWqey050=a:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmpZ~hz535>i5Z0.eqb+ta'nf;"z| wqlwv*Kdg|dSnaznu]{kw:>6Vx=k5Z0.eqb+ta'nf;"z| wqlwv*eh}g~7<3?i;T2,cw`)zo%l`= xr.usjqt(kfex1?11g9V4*aun'xm#jb?.vp,suhsz&idycz32?3e?P6(o{l%~k!hl1,tv*qwf}x$ob{at=1=5c=R8&myj#|i/fn3*rt(yd~"m`uov?0;7a3\:$kh!rg-dh5(pz&}{by| cnwmp9399o1^<"i}f/pe+bj7&~x${}`{r.alqkr;>7;m7X> gsd-vc)`d9$|~"ynup,gjsi|5=5=k5Z0.eqb+ta'nf;"z| wqlwv*eh}g~743?i;T2,cw`)zo%l`= xr.usjqt(kfex1711d9V4*aun'xm#jb?.vp,suhsz&idyczP00g8Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_03f?P6(o{l%~k!hl1,tv*qwf}x$ob{at^02a>S7'nxm"h gm2-sw)pxg~y#naznu]05`=R8&myj#|i/fn3*rt(yd~"m`uov\04c<]9%l~k }f.eo4+qu'~zex!lotlw[07b3\:$kh!rg-dh5(pz&}{by| cnwmpZ06m2_;#j|i.sd,ci6){%||cz}/bmvjqY09l1^<"i}f/pe+bj7&~x${}`{r.alqkrX08o0Y=!hrg,qb*ak8'}y#z~ats-`kphsW0897X> gsd-vc)`d9$|~"ynup,gjsi|Vn:0=0=2:W3+bta&{l$ka>!ws-ttkru'je~byQk1=3=67=R8&myj#|i/fn3*rt(yd~"m`uov\`4:56;80Y=!hrg,qb*ak8'}y#z~ats-`kphsWm;7?3<=;T2,cw`)zo%l`= xr.usjqt(kfexRj><5<16>S7'nxm"h gm2-sw)pxg~y#naznu]g5939:;1^<"i}f/pe+bj7&~x${}`{r.alqkrXl86=2?<4U1-dvc(un&mg<#y}/vrmpw)dg|dSi?37?01?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f28=85:2_;#j|i.sd,ci6){%||cz}/bmvjqYc9535><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th<Q?209V4*aun'xm#jb?.vp,suhsz&idyczPd0]264=R8&myj#|i/fn3*rt(yd~"m`uov\`4Y5:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl8U8><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th<Q;209V4*aun'xm#jb?.vp,suhsz&idyczPd0]664=R8&myj#|i/fn3*rt(yd~"m`uov\`4Y1:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl8U<><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th<Q7209V4*aun'xm#jb?.vp,suhsz&idyczPd0]:67=R8&myj#|i/fn3*rt(yd~"m`uov\`7:76;80Y=!hrg,qb*ak8'}y#z~ats-`kphsWm87=3<=;T2,cw`)zo%l`= xr.usjqt(kfexRj=<3<16>S7'nxm"h gm2-sw)pxg~y#naznu]g6959:;1^<"i}f/pe+bj7&~x${}`{r.alqkrXl;6?2?<4U1-dvc(un&mg<#y}/vrmpw)dg|dSi<35?01?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f18385:2_;#j|i.sd,ci6){%||cz}/bmvjqYc:5=5>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th?27>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e0?=;463\:$kh!rg-dh5(pz&}{by| cnwmpZb5W98:7X> gsd-vc)`d9$|~"ynup,gjsi|Vn9S<<>;T2,cw`)zo%l`= xr.usjqt(kfexRj=_302?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f1[6463\:$kh!rg-dh5(pz&}{by| cnwmpZb5W=8:7X> gsd-vc)`d9$|~"ynup,gjsi|Vn9S8<>;T2,cw`)zo%l`= xr.usjqt(kfexRj=_702?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f1[2463\:$kh!rg-dh5(pz&}{by| cnwmpZb5W18:7X> gsd-vc)`d9$|~"ynup,gjsi|Vn9S4<=;T2,cw`)zo%l`= xr.usjqt(kfexRj<<1<16>S7'nxm"h gm2-sw)pxg~y#naznu]g7979:;1^<"i}f/pe+bj7&~x${}`{r.alqkrXl:692?<4U1-dvc(un&mg<#y}/vrmpw)dg|dSi=33?01?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f08185:2_;#j|i.sd,ci6){%||cz}/bmvjqYc;5?5>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th>29>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e1?3;453\:$kh!rg-dh5(pz&}{by| cnwmpZb44149>6[?/fpe*w`(oe:%{!xpovq+firf}Uo?171209V4*aun'xm#jb?.vp,suhsz&idyczPd2]364=R8&myj#|i/fn3*rt(yd~"m`uov\`6Y6:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl:U9><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th>Q<209V4*aun'xm#jb?.vp,suhsz&idyczPd2]764=R8&myj#|i/fn3*rt(yd~"m`uov\`6Y2:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl:U=><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th>Q8209V4*aun'xm#jb?.vp,suhsz&idyczPd2];64=R8&myj#|i/fn3*rt(yd~"m`uov\`6Y>:=1^<"i}f/pe+bj7&~x${}`{r.alqkrXff~;<=?>7:W3+bta&{l$ahc dnww[l:76820Y=!hrg,qb*kbe&ndyyQf<02=5==R8&myj#|i/lgn+air|Vc7=<0>8:W3+bta&{l$ahc dnww[l:6:7;37X> gsd-vc)jmd%ocxzPi=30:4><]9%l~k }f.ofi*bh}}Ub0<:1199V4*aun'xm#`kb/emvpZo;9<4:46[?/fpe*w`(elg$hb{{_h>22;7?3\:$kh!rg-nah)cg|~Te1?8>0:8Q5)`zo$yj"cjm.flqqYn4825=55Z0.eqb+ta'dof#iazt^k?5<86?2_;#j|i.sd,i`k(lfSd2>>0:8Q5)`zo$yj"cjm.flqqYn4;:5=55Z0.eqb+ta'dof#iazt^k?648602_;#j|i.sd,i`k(lfSd2=2?3;?P6(o{l%~k!bel-gkprXa5882<64U1-dvc(un&gna"j`uu]j8729911^<"i}f/pe+hcj'me~xRg324<2<>S7'nxm"h mdo,`jssW`69:3?7;T2,cw`)zo%fi`!kotv\m9406820Y=!hrg,qb*kbe&ndyyQf<3:=5==R8&myj#|i/lgn+air|Vc7>40>7:W3+bta&{l$ahc dnww[l:56820Y=!hrg,qb*kbe&ndyyQf<22=5==R8&myj#|i/lgn+air|Vc7?<0>8:W3+bta&{l$ahc dnww[l:4:7;37X> gsd-vc)jmd%ocxzPi=10:4><]9%l~k }f.ofi*bh}}Ub0>:1199V4*aun'xm#`kb/emvpZo;;<4:;6[?/fpe*w`(elg$hb{{_h>0:41<]9%l~k }f.ofi*bh}}Ub090>7:W3+bta&{l$ahc dnww[l:268=0Y=!hrg,qb*kbe&ndyyQf<7<23>S7'nxm"h mdo,`jssW`6<2<94U1-dvc(un&gna"j`uu]j8=86?2_;#j|i.sd,i`k(lfSd26>048Q5)`zo$yj"cjm.flqqYnW9;=7X> gsd-vc)jmd%ocxzPi^323>S7'nxm"h mdo,`jssW`U:<<94U1-dvc(un&gna"j`uu]j[476?2_;#j|i.sd,i`k(lfSdQ>2058Q5)`zo$yj"cjm.flqqYnW89:;6[?/fpe*w`(elg$hb{{_h]2041<]9%l~k }f.ofi*bh}}UbS<;>7:W3+bta&{l$ahc dnww[lY6>8=0Y=!hrg,qb*kbe&ndyyQf_0523>S7'nxm"h mdo,`jssW`U:4<94U1-dvc(un&gna"j`uu]j[4?6>2_;#j|i.sd,i`k(lfSdQ=169V4*aun'xm#`kb/emvpZoX:9;<7X> gsd-vc)jmd%ocxzPi^0252=R8&myj#|i/lgn+air|VcT>??8;T2,cw`)zo%fi`!kotv\mZ449>1^<"i}f/pe+hcj'me~xRgP2534?P6(o{l%~k!bel-gkprXaV8>=:5Z0.eqb+ta'dof#iazt^k\63703\:$kh!rg-nah)cg|~TeR<8169V4*aun'xm#`kb/emvpZoX:1;<7X> gsd-vc)jmd%ocxzPi^0:53=R8&myj#|i/lgn+air|VcT?<94U1-dvc(un&gna"j`uu]j[666?2_;#j|i.sd,i`k(lfSdQ<1058Q5)`zo$yj"cjm.flqqYnW:8:;6[?/fpe*w`(elg$hb{{_h]0741<]9%l~k }f.ofi*bh}}UbS>:>7:W3+bta&{l$ahc dnww[lY4=8<0Y=!hrg,qb*kbe&ndyyQf_535?P6(o{l%~k!bel-gkprXaV?::6[?/fpe*w`(elg$hb{{_h]553=R8&myj#|i/lgn+air|VcT;<84U1-dvc(un&gna"j`uu]j[=713\:$kh!rg-nah)cg|~TeR7>9:W3+bta&{l$ahc dnww[hcj494:m6[?/fpe*w`(elg$hb{{_lgn84699h1^<"i}f/pe+hcj'me~xRcjm=32:4g<]9%l~k }f.ofi*bh}}Ufi`2>2?3b?P6(o{l%~k!bel-gkprXelg7=>0>a:W3+bta&{l$ahc dnww[hcj48>5=l5Z0.eqb+ta'dof#iazt^ofi97268k0Y=!hrg,qb*kbe&ndyyQbel>22;7f3\:$kh!rg-nah)cg|~Tahc316<2e>S7'nxm"h mdo,`jssWdof0<611`9V4*aun'xm#`kb/emvpZkbe5;22<74U1-dvc(un&gna"j`uu]nah:668k0Y=!hrg,qb*kbe&ndyyQbel>14;7f3\:$kh!rg-nah)cg|~Tahc320<2e>S7'nxm"h mdo,`jssWdof0?<11`9V4*aun'xm#`kb/emvpZkbe5882<o4U1-dvc(un&gna"j`uu]nah:5<7;j7X> gsd-vc)jmd%ocxzPmdo?6086i2_;#j|i.sd,i`k(lfS`kb<34=5d=R8&myj#|i/lgn+air|Vgna1<8>0c8Q5)`zo$yj"cjm.flqqYjmd6943?n;T2,cw`)zo%fi`!kotv\i`k;:04:56[?/fpe*w`(elg$hb{{_lgn8786i2_;#j|i.sd,i`k(lfS`kb<22=5d=R8&myj#|i/lgn+air|Vgna1=>>0c8Q5)`zo$yj"cjm.flqqYjmd68>3?n;T2,cw`)zo%fi`!kotv\i`k;;:4:m6[?/fpe*w`(elg$hb{{_lgn86299h1^<"i}f/pe+hcj'me~xRcjm=16:4?<]9%l~k }f.ofi*bh}}Ufi`2<>0;8Q5)`zo$yj"cjm.flqqYjmd6?2<74U1-dvc(un&gna"j`uu]nah:26830Y=!hrg,qb*kbe&ndyyQbel>5:4?<]9%l~k }f.ofi*bh}}Ufi`28>0;8Q5)`zo$yj"cjm.flqqYjmd632<74U1-dvc(un&gna"j`uu]nah:>6>>0Y=!hrg,qb*kbe&mia#immf,dfhaf&gmnon mmf-ahnYjmdUlick}aumq+sgkam$hy| r`ookjv\8T$ym` }/r1\jjoia}$ym`!kpscn*av60q9="ob1c9V4*aun'xm#`kb/uos[wgjW{nTic?l;T2,cw`)zo%fi`!{mq]qehYulVoe=<94U1-dvc(un&xjaR|jgnww[`h6l2_;#j|i.sd,vvredb%yhR||t^cpv`a582_;#j|i.sd,vvredb%yhR||t^cpv`aXl88;7X> gsd-vc)u{}hgg"|k_sqw[duumnUo><m4U1-dvc(un&xxxobd/sf\vvrXkfgi=i5Z0.eqb+ta'{ynae re]qwqYdgdh:=h5Z0.eqb+ta'{ynae re]qwqYumn6;2<k4U1-dvc(un&xxxobd/sf\vvrXzlm7=3?j;T2,cw`)zo%yylck.pg[wusW{ol0?0>d:W3+bta&{l$~~zmlj-q`Ztt|VxnkR>>d:W3+bta&{l$~~zmlj-q`Ztt|VxnkR?>d:W3+bta&{l$~~zmlj-q`Ztt|VxnkR<>d:W3+bta&{l$~~zmlj-tvZtt|Vkx~hi=0:W3+bta&{l$~~zmlj-tvZtt|Vkx~hiPd003?P6(o{l%~k!}su`oo*quW{ySl}}ef]g64e<]9%l~k }f.pppgjl'~xT~~zPcnoa5a=R8&myj#|i/sqwfim({UyyQlol`25`=R8&myj#|i/sqwfim({UyyQ}ef>3:4c<]9%l~k }f.pppgjl'~xT~~zPrde?5;7c3\:$kh!rg-qwqdkc&}yS}{_sgd[57c3\:$kh!rg-qwqdkc&}yS}{_sgd[4g<]ZOYSLBFARa8QVCUW_CXEOBJ3:T@G<=QAL]TXT^J3:UFE6=PMKi0[_G[E^OL@@YFk2]YEYKPMNFF[Gb<_[C_IRYFDUJ\Ea=PZ@^NSZGKTI]A5a=_AECET VKB!2-5%US]K*;"<.NSBKJ1>^HZJS=7U][LH@4?]USWNDO;6V\T^T@Gg=_WJEYIRGAFN48\adXAml0TifPPsknR`ttafd:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`nb9bhhit|Vof|ywm;`nnkvrXn|fg:6lncjws`>dfkb{S`o}kdp0?fjll2njxlQlotlw,5/c3mkmRm`uov+5,b<lh~jSnaznu*1-a=ci}kTob{at)1*`>bf|hUhcx`{(5+g?agsiVidycz'5(f8`drfWje~by&9)e9geqgXkfex%9&d:fbpdYdg|d$5'k;ecweZeh}g~#5$h4d`vb[firf}626=08;e`jp`tu>2nbb%>&6:fjj-7.?2nbb%??)69gmk.69 =0hd`'13+4?aoi 89";6jfn)37-2=cag":9$94dhl+53/03mce$<9&6:fjj-4.>2nbb%=&6:fjj-2.>2nbb%;&6:fjj-0.>2nbb%9&6:fjj->.>2nbb%7&6:fjj969?2nbb1??>69gmk:697=0hd`313<4?aoi4895;6jfn=37:2=cag6:9394dhl?538>3mce0<950?58`lh;9>4=7iga<0<5?aoi4;4=7iga<2<5?aoi4=4=7iga<4<5?aoi4?4=7iga<6<5?aoi414=7iga<8<4?air|!:";6j`uu*2-==cg|~#=='7;emvp-76!11ocxz'13+;?air|!;8%55kotv+51/?3me~x%?:)99gkpr/9?#37iazt)34-==cg|~#=5'7;emvp-7>!>1ocxz'2(:8`jss ;:"46j`uu*15,><lf$?<&8:flqq.5; 20hb{{(36*<>bh}}"99$64dnww,70.02ndyy&=7(:8`jss ;2"46j`uu*1=,1<lf$>'7;emvp-57!11ocxz'30+;?air|!99%55kotv+76/?3me~x%=;)99gkpr/;<#<7iazt)6*3>bh}}">%:5kotv+2,1<lf$:'8;emvp->.?2ndyy&6)69gkpr;8720hb{{<02=<>bh}}6:=364dnww844902ndyy2>3?:8`jss48>546j`uu>21;><lf0<818:flqq:6?720hb{{<0:=<>bh}}6:5394dnww848?3me~x1<?>99gkpr;:8437iazt=01:==cg|~7>>07;emvp943611ocxz324<;?air|58=255kotv?628?3me~x1<7>99gkpr;:04<7iazt=0=<>bh}}68<364dnww867902ndyy2<2?:8`jss4:9546j`uu>00;g<lf0>;50?:8`jss4:?5;6j`uu>0:2=cg|~78394dnww80803me~x1817:flqq:06>1ocxz38?58`jss40437hjff3ld`0=bey~r>k5iigm\c`hbzh~d~Rx9_0.#\ljnfq*HC_K/Gdlfvdrhz);9"<?l;gkekZ~kfqU>=?v<6^0`hnY60}e8:>o4fhdl[}jipV?:>u=9_3aooZ7?|f9= kgio^efj`tf|fxTz;Q>,OMMA)HHFL>;?6hffn]{hk~X=88s?;Q=cmi\5=rh;?&mekaPgdlfvdrhzV|=S<"tc^jbwZoi|Vigg0>#c^jbwZuu{}7; nQ}d^dqat;6$jUnbllce^pppZu~fj7: nQgar]q`Zbf|hUhcx`{=1.`[aoiW~coxe3>8-a\lduX{UomyoPcnwmp86+kVl~`aQil`ep[wusWkg1="l_hosh`kbf}keb`Ptxrf97*dW|ynShcmeeff`Ztbo4:'oRy}_gpfu87+kVxiRj`uu]qwq;6$jU~bik}fmmt[iip59&hSeo|_ntfvcjh4:'oR~}emmb`Zjf|ldhu0>#c^flqqYpam~c1>8#c^opcjhX~hf6=!mPre]gauro5<;9 nQjrsmq[lhmmj~bccQ{yqg>4)eX`hyTycjjrgnls86+kVbjRocmnqw[cskd4;'oRfns^ppp87+kVnjxlQlotlw[roc|a7:<!mPh`q\swYfkb7; nQzsd]fgf;7$jUhc`c`n^aokfm:8%iT{Qncj]okr;7$jUyhR~ats]tmaro50&hSx}j_guepZbf|hUhcx`{=1.`[mgtWhffc~zPelrw}86+kVxoSio{a^alqkrX`nd07#c^muaw`kg~Ugcz3?,b]tvZvi|{U|eizg=02/gZvugnUna}zv_u{sa86+kV}ySio{a^alqkrX`nd0??,b]sv`jhimUyij}21-a\`jssW{yS{oc=1.`[mgtWmkmRm`uov>4)eXx{elSk{cl^vkv`uoWgolmykPv`n>5573$jU|~Rjjpuj>5543$jU{~biPelrw}ZrozlycSckhaug\rdj:=%iT|ah_dosp|Ys`{oxdRo|sdpw[sgk5=&hSeo|_wcoma;7$jU{~biPftno[qnumzbTm~}jru]uei;688?'obcoogmpZhfel7mekaPxml{[075p:<T>nbd_0:wk60+kV|j`djPlnu>4)eXx{cfSkgio^vzt`;6cq;3 nQrne\bpjkW}s{i0?#c^ofijt~W}s{i0?#}248bl`hWqfetR;>2y15[7ekcV;3xb=9_gkekZabflxjxb|Pv7]2[}usW8>0jxbcd:kmn`eslkci|k;hliafrtj`~n~94iov\gim?3gmhnxgcd99lr`tadf}j7}|`g^gntq6<2zycjQjmqvz[qnumzb#<$?;;qplcZcjx}sTxe|jsi*2-42<x{elShctx]wlwct`!8"=95rne\ahvsqV~c~h}g(2+20>vugnUna}zv_ujqavn/< ;?7}|`g^gntqX|axne&:)068twi`Wlg{xtQ{hsgpl-0.9=1{~biPelrw}Zrozlyc$:'>4:rqkbYbey~rSyf}erj+<,713yxdkRkbpu{\pmtb{a636=0>b:rqkbYbey~rSyf}erj\evubz}";%<l4psmd[`kw|pUdk|h^cpw`ts 8#:n6~}of]fiur~W}byi~fParqfvq.5!8h0|ah_dosp|Ys`{oxdRo|sdpw,6/6j2zycjQjmqvz[qnumzbTm~}jru*7-4d<x{elShctx]wlwct`Vkxh|{(4+2f>vugnUna}zv_ujqavnXizyn~y&9)0`8twi`Wlg{xtQ{hsgplZgt{lx$:'>b:rqkbYbey~rSyf}erj\evubz}"3%<j4psmd[`kw|pUdk|h^cpw`ts410;2<l4psmd[`kw|pUdk|h^lfcdrb 9#:n6~}of]fiur~W}byi~fPndebp`.6!8h0|ah_dosp|Ys`{oxdR`jg`vf,7/6j2zycjQjmqvz[qnumzbTbhintd*0-4d<x{elShctx]wlwct`Vdnklzj(5+2f>vugnUna}zv_ujqavnXflmjxh&:)0`8twi`Wlg{xtQ{hsgplZhboh~n$;'>b:rqkbYbey~rSyf}erj\j`af|l"<%<l4psmd[`kw|pUdk|h^lfcdrb 1#:h6~}of]fiur~W}byi~fPndebp`:?29427}|`g^dvhi743yxdkRhzlm]wlwct`!:"=>5rne\bpjkW}byi~f'1(30?uthoVl~`aQ{hsgpl-4.9:1{~biPftno[qnumzb#?$?<;qplcZ`rdeUdk|h)6*56=wzfmTjxbc_ujqavn/= ;87}|`g^dvhiYs`{oxd%8&129svjaXn|fgSyf}erj+3,743yxdkRhzlm]wlwct`!2"=>5rne\bpjkW}byi~f'9(36?uthoVl~`aQ{hsgpl9?=87;j7}|`g^dvhiYs`{oxdRo|sdpw,5/6i2zycjQiumn\pmtb{aUj~k}t)3*5d=wzfmTjxbc_ujqavnXizyn~y&=)0c8twi`Wog`Rzgrdqk[dutm{~#?$?n;qplcZ`rdeUdk|h^cpw`ts =#:m6~}of]eqijX|axneQnsrgqp-3.9h1{~biPftno[qnumzbTm~}jru*5-4g<x{elSk{cl^vkv`uoWhyxiz'7(3b?uthoVl~`aQ{hsgplZgt{lx$5'>a:rqkbYa}efTxe|jsi]bwvcu|!3"=n5rne\bpjkW}byi~fParqfvq:>294:m6~}of]eqijX|axneQaefcwa-6.9h1{~biPftno[qnumzbTbhintd*2-4g<x{elSk{cl^vkv`uoWgolmyk'2(3b?uthoVl~`aQ{hsgplZhboh~n$>'>a:rqkbYa}efTxe|jsi]mabgsm!>"=l5rne\bpjkW}byi~fPndebp`.2!8k0|ah_gwohZrozlycSckhaug+2,7f3yxdkRhzlm]wlwct`Vdnklzj(6+2e>vugnUmyabPtipfwmYimnki%6&1`9svjaXn|fgSyf}erj\j`af|l"2%<m4psmd[cskdV~c~h}g_ogdeqc;13:5:6|k_bnh55=ulVnjxlQlotlw,5/682xoSio{a^alqkr/9 ;;7jPd`vb[firf}"9%<>4re]geqgXkfex%=&119q`Zbf|hUhcx`{(5+24>tcWmkmRm`uov+1,773{nThlzn_bmvjq.1!8:0~iQkauc\gjsi|!="==5}d^fbpdYdg|d$5'>0:pg[agsiVidycz30?31?wbXlh~jSnaznu>;>5823{nTic84re]qwq5<zz~<7~lftdpq0>uu{}837yc/^ad+coagVrgbuQ:13z02Z4ddbU:4ya<6/ldk1=sz|o27x`kesdokr3<~hfbh;5xr^c`o3=pzVigg<>4ws]geqgXkfex%>&119tvZbf|hUhcx`{(0+24>quWmkmRm`uov+6,773~xThlzn_bmvjq.4!8:0{Qkauc\gjsi|!>"==5xr^fbpdYdg|d$8'>0:uq[agsiVidycz'6(33?rtXlh~jSnaznu*4-46<{UomyoPcnwmp->.991|~Rjnt`]`kphs 0#:>6y}_ecweZeh}g~757>15:uq[`h13~xT~~zr@Ar``==GHq?=>7H54;3xW1c==991;7?<2c4g6?4f:k=pb96=:09m0=5=>2.?4=4;7`9~W1e==991;7?<2c4g6?4f:k=0_<<m:42f>5<6;;h=h?4=a3`;?V2d2<:n6=4>33`5`7<5i;h37i;?6;295?7|[=o19==57;306g0c:38j>o94vU3;e?6=93;1=n>tS5g9155=?3;8>o8k2;0b6g1<,==86<<l;W6;5?4|}89?6<5z12794>{#9>o1=55m51494?5a2:08jvF;709Y01<5s8=1==4r$0:e>0613-><j7;?5:k61a<722e?484?::m66c<722c>;>4?::m64d<722e><94?::k622<722c>9k4?::m7`2<72-;3<7:ia:l23c<732e?h;4?:%3;4?2ai2d:;k4>;:m7`0<72-;3<7:ia:l23c<532e?h94?:%3;4?2ai2d:;k4<;:m7`6<72-;3<7:ia:l23c<332e?h?4?:%3;4?2ai2d:;k4:;:m7`5<72-;3<7:ia:l23c<132e?ok4?:%3;4?2ai2d:;k48;:m7g`<72-;3<7:ia:l23c<?32e?oi4?:%3;4?2ai2d:;k46;:m7gf<72-;3<7:ia:l23c<f32e?oo4?:%3;4?2ai2d:;k4m;:m7gd<72-;3<7:ia:l23c<d32e?o44?:%3;4?2ai2d:;k4k;:m7g=<72-;3<7:ia:l23c<b32e?o:4?:%3;4?2ai2d:;k4i;:m7g0<72-;3<7:ia:l23c<6821d8n:50;&2<5<3nh1e=:h51098k1e4290/=5>54gc8j41a28807b:l2;29 4>72=lj7c?8f;30?>i3k80;6)?70;6ee>h6?o0:865`4b294?"6090?jl5a16d950=<g=hm6=4+19290cg<f8=m6<84;n6aa?6=,82;69hn;o34b?7032e?ni4?:%3;4?2ai2d:;k4>8:9l0ge=83.:4=4;f`9m52`=9010c9jk:18'5=6=<ok0b<9i:0c8?j2ck3:1(<6?:5db?k70n3;i76a;dc83>!7?83>mm6`>7g82g>=h<mk1<7*>8187bd=i9>l1=i54o5f:>5<#91:18ko4n05e>4c<3f>o47>5$0:3>1`f3g;<j7?i;:m7`4<72-;3<7:ia:l23c<5821d8n850;&2<5<3nh1e=:h52098k1de290/=5>54gc8j41a2;807b:ma;29 4>72=lj7c?8f;00?>o31l0;6)?70;6bb>h6?o0;76g;9e83>!7?83>jj6`>7g82?>o31j0;6)?70;6bb>h6?o0976g;9c83>!7?83>jj6`>7g80?>o31h0;6)?70;6bb>h6?o0?76g;9883>!7?83>jj6`>7g86?>o3110;6)?70;6bb>h6?o0=76g;9683>!7?83>jj6`>7g84?>o3i?0;6)?70;6bb>h6?o0376g;a483>!7?83>jj6`>7g8:?>o3i=0;6)?70;6bb>h6?o0j76g;a283>!7?83>jj6`>7g8a?>o3i;0;6)?70;6bb>h6?o0h76g;a083>!7?83>jj6`>7g8g?>o3i90;6)?70;6bb>h6?o0n76g;9g83>!7?83>jj6`>7g8e?>o31?0;6)?70;6bb>h6?o0:<65f48794?"6090?mk5a16d954=<a<?:6=44b551>5<6290;wE:81:&2<c<3?;1d=:j50;9~fa1=83;1<7>tH552?!7?n3n<7bj9:188yg24290j:7?74;3`4~N3?81Q894>6z0;>71=:00h644n:c823?772;k1h7m5d;34>7g=:10:<7l5a;;96<<5?3w/=5h551;8 11==9=0(9j551:8 41>28=h7d;=3;29 4>72<8?7c?8f;28?l35:3:1(<6?:407?k70n3;07d;=1;29 4>72<8?7c?8f;08?l3583:1(<6?:407?k70n3907d;>f;29 4>72<8?7c?8f;68?l36m3:1(<6?:407?k70n3?07d;>d;29 4>72<8?7c?8f;48?l36k3:1(<6?:407?k70n3=07d;>b;29 4>72<8?7c?8f;:8?l37k3:17d;:e;29?l3193:17b;95;29?l3613:1(<6?:43b?k70n3:07d;>8;29 4>72<;j7c?8f;38?l36?3:1(<6?:43b?k70n3807d;>6;29 4>72<;j7c?8f;18?l36=3:1(<6?:43b?k70n3>07d;>4;29 4>72<;j7c?8f;78?l36;3:1(<6?:43b?k70n3<07d;>2;29 4>72<;j7c?8f;58?l3693:1(<6?:43b?k70n3207d;:d;29?j37n3:17d;=d;29 4>72<8n7c?8f;28?l35k3:1(<6?:40f?k70n3;07d;=b;29 4>72<8n7c?8f;08?l35i3:1(<6?:40f?k70n3907d;=9;29 4>72<8n7c?8f;68?l3503:1(<6?:40f?k70n3?07d;=7;29 4>72<8n7c?8f;48?l35>3:1(<6?:40f?k70n3=07d;=5;29 4>72<8n7c?8f;:8?j2?=3:17b:62;29 4>72=387c?8f;28?j2>93:1(<6?:5;0?k70n3;07b:60;29 4>72=387c?8f;08?j2?n3:1(<6?:5;0?k70n3907b:7e;29 4>72=387c?8f;68?j2?l3:1(<6?:5;0?k70n3?07b:7c;29 4>72=387c?8f;48?j2?j3:1(<6?:5;0?k70n3=07b:7a;29 4>72=387c?8f;:8?j2?13:1(<6?:5;0?k70n3307b;=f;29?l30;3:17d;<9;29 4>72<9j7c?8f;28?l3403:1(<6?:41b?k70n3;07d;<7;29 4>72<9j7c?8f;08?l34>3:1(<6?:41b?k70n3907d;<5;29 4>72<9j7c?8f;68?l34<3:1(<6?:41b?k70n3?07d;<3;29 4>72<9j7c?8f;48?l34:3:1(<6?:41b?k70n3=07d;<1;29 4>72<9j7c?8f;:8?l3483:1(<6?:41b?k70n3307b;?a;29?j37<3:17d;97;29?l2??3:17d;;4;29 4>72<>>7c?8f;28?l33;3:1(<6?:466?k70n3;07d;;2;29 4>72<>>7c?8f;08?l3393:1(<6?:466?k70n3907d;;0;29 4>72<>>7c?8f;68?l34n3:1(<6?:466?k70n3?07d;<e;29 4>72<>>7c?8f;48?l34l3:1(<6?:466?k70n3=07d;<c;29 4>72<>>7c?8f;:8?l34j3:1(<6?:466?k70n3307d;;f;29 4>72<?;7c?8f;28?l33m3:1(<6?:473?k70n3;07d;;d;29 4>72<?;7c?8f;08?l33k3:1(<6?:473?k70n3907d;;b;29 4>72<?;7c?8f;68?l33i3:1(<6?:473?k70n3?07d;;9;29 4>72<?;7c?8f;48?l3303:1(<6?:473?k70n3=07d;;7;29 4>72<?;7c?8f;:8?l33>3:1(<6?:473?k70n3307b:74;29?l37l3:17d:78;29?l30<3:17b;90;29?j31>3:17d;:f;29?j2c?3:1(<6?:5db?k70n3:07b:k6;29 4>72=lj7c?8f;38?j2c=3:1(<6?:5db?k70n3807b:k4;29 4>72=lj7c?8f;18?j2c;3:1(<6?:5db?k70n3>07b:k2;29 4>72=lj7c?8f;78?j2c83:1(<6?:5db?k70n3<07b:lf;29 4>72=lj7c?8f;58?j2dm3:1(<6?:5db?k70n3207b:ld;29 4>72=lj7c?8f;;8?j2dk3:1(<6?:5db?k70n3k07b:lb;29 4>72=lj7c?8f;`8?j2di3:1(<6?:5db?k70n3i07b:l9;29 4>72=lj7c?8f;f8?j2d03:1(<6?:5db?k70n3o07b:l7;29 4>72=lj7c?8f;d8?j2d=3:1(<6?:5db?k70n3;;76a;c583>!7?83>mm6`>7g825>=h<j91<7*>8187bd=i9>l1=?54o5a1>5<#91:18ko4n05e>45<3f>h=7>5$0:3>1`f3g;<j7?;;:m7g5<72-;3<7:ia:l23c<6=21d8oh50;&2<5<3nh1e=:h51798k1db290/=5>54gc8j41a28=07b:md;29 4>72=lj7c?8f;3;?>i3jj0;6)?70;6ee>h6?o0:565`4ef94?"6090?jl5a16d95d=<g=nh6=4+19290cg<f8=m6<l4;n6gf?6=,82;69hn;o34b?7d32e?hl4?:%3;4?2ai2d:;k4>d:9l0a?=83.:4=4;f`9m52`=9l10c9j7:18'5=6=<ok0b<9i:0d8?j2c93:1(<6?:5db?k70n38;76a;c783>!7?83>mm6`>7g815>=h<kh1<7*>8187bd=i9>l1>?54o5`b>5<#91:18ko4n05e>75<3`>2i7>5$0:3>1ga3g;<j7>4;h6:`?6=,82;69oi;o34b?7<3`>2o7>5$0:3>1ga3g;<j7<4;h6:f?6=,82;69oi;o34b?5<3`>2m7>5$0:3>1ga3g;<j7:4;h6:=?6=,82;69oi;o34b?3<3`>247>5$0:3>1ga3g;<j784;h6:3?6=,82;69oi;o34b?1<3`>j:7>5$0:3>1ga3g;<j764;h6b1?6=,82;69oi;o34b??<3`>j87>5$0:3>1ga3g;<j7o4;h6b7?6=,82;69oi;o34b?d<3`>j>7>5$0:3>1ga3g;<j7m4;h6b5?6=,82;69oi;o34b?b<3`>j<7>5$0:3>1ga3g;<j7k4;h6:b?6=,82;69oi;o34b?`<3`>2:7>5$0:3>1ga3g;<j7??;:k7=0<72-;3<7:nf:l23c<6921b85850;9l10g=83.:4=4:5b9m52`=821d98750;&2<5<2=j1e=:h51:9l10>=83.:4=4:5b9m52`=:21d98950;&2<5<2=j1e=:h53:9l100=83.:4=4:5b9m52`=<21d98;50;&2<5<2=j1e=:h55:9l102=83.:4=4:5b9m52`=>21d98=50;&2<5<2=j1e=:h57:9l104=83.:4=4:5b9m52`=021d9:?50;&2<5<2?;1e=:h50:9l126=83.:4=4:739m52`=921d9;h50;&2<5<2?;1e=:h52:9l13c=83.:4=4:739m52`=;21d9;j50;&2<5<2?;1e=:h54:9l13e=83.:4=4:739m52`==21d9;l50;&2<5<2?;1e=:h56:9l13g=83.:4=4:739m52`=?21d9;750;&2<5<2?;1e=:h58:9l13>=83.:4=4:739m52`=121d9<>50;9j15d=831d84:50;9j107=831d9;:50;9a02b=83;1<7>t$0:e>a1<@==h7E:81:mg2?6=3th?;h4?:083>5}#91l18:<4H55`?M2092e:;i4?::a6d6=83>1<7>t$0:e>a4<@==h7E:81:&f1?0<a=?1<75f4g83>>o6080;66a>8383>>{e<<o1<7=50;2x 4>a2jl0D99l;I645>N3:2.:??4:629'a0<63`>>6=44i5d94?=h9181<75rb54:>5<4290;w)?7f;ae?M20k2B?;<5G439'564==?90(h;51:k71?6=3`>m6=44o0:1>5<<uk>>h7>53;294~"60o0hj6F;7b9K027<@=80(<==:440?!c2281b884?::k7b?6=3f;3>7>5;|`722<72<0;6=u+19d9`6=O<>i0D99>;I61?!74:3?=?6g;5;29?l212900e9h50;9j5=7=831d=5<50;9~f10?29086=4?{%3;b?ea3A><o6F;709K07=#9:819;=4$d795>o3=3:17d:i:188k4>52900qo::c;291?6=8r.:4k4k3:J73f=O<>;0D9<4$011>0043`>>6=44i5494?=n<o0;66g>8083>>i60;0;66sm47494?2=83:p(<6i:e08L11d3A><=6*j5;48m13=831b8k4?::k2<4<722e:4?4?::a033=83>1<7>t$0:e>a4<@==h7E:81:&f1?0<a=?1<75f4g83>>o6080;66a>8383>>{e<?>1<7:50;2x 4>a2m80D99l;I645>"b=3<0e9;50;9j0c<722c:4<4?::m2<7<722wi8;h50;694?6|,82m6i<4H55`?M2092.n9784i5794?=n<o0;66g>8083>>i60;0;66sm47g94?2=83:p(<6i:e08L11d3A><=6*j5;48m13=831b8k4?::k2<4<722e:4?4?::a642=83>1<7>t$0:e>a6<@==h7E:81:&f1?7<a=?1<75f4c83>>o3n3:17b?72;29?xd59:0;694?:1y'5=`=l91C8:m4H552?!c2281b884?::k7f?6=3`>m6=44o0:1>5<<uk8:>7>54;294~"60o0o<6F;7b9K027<,l?1=6g;5;29?l2e2900e9h50;9l5=4=831vn??>:187>5<7s-;3j7j?;I64g>N3?81/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm20294?2=83:p(<6i:e28L11d3A><=6*j5;38m13=831b8o4?::k7b?6=3f;3>7>5;|`14c<72=0;6=u+19d9`5=O<>i0D99>;%g6>4=n<<0;66g;b;29?l2a2900c<6=:188yg47m3:187>50z&2<c<c82B?;n5G4638 `3=92c?97>5;h6a>5<<a=l1<75`19094?=zj;:o6=4;:183!7?n3n;7E:8c:J734=#m<0:7d:::188m1d=831b8k4?::m2<7<722wi>=m50;694?6|,82m6i>4H55`?M2092.n97?4i5794?=n<k0;66g;f;29?j7?:3:17pl>b383>1<729q/=5h5d19K02e<@==:7)k::09j00<722c?n7>5;h6e>5<<g8296=44}c3a5?6=<3:1<v*>8g8g4>N3?j1C8:?4$d795>o3=3:17d:m:188m1`=831d=5<50;9~f4d7290?6=4?{%3;b?b73A><o6F;709'a0<63`>>6=44i5`94?=n<o0;66a>8383>>{e9hl1<7:50;2x 4>a2m:0D99l;I645>"b=3;0e9;50;9j0g<722c?j7>5;n3;6?6=3th:mh4?:583>5}#91l1h=5G46a8L1163-o>6<5f4483>>o3j3:17d:i:188k4>52900qo?nd;290?6=8r.:4k4k0:J73f=O<>;0(h;51:k71?6=3`>i6=44i5d94?=h9181<75rb0c`>5<3290;w)?7f;f3?M20k2B?;<5+e482?l222900e9l50;9j0c<722e:4?4?::a5dd=83>1<7>t$0:e>a6<@==h7E:81:&f1?7<a=?1<75f4c83>>o3n3:17b?72;29?xd6ih0;694?:1y'5=`=l91C8:m4H552?!c2281b884?::k7f?6=3`>m6=44o0:1>5<<uk8=<7>54;294~"60o0o<6F;7b9K027<,l?1=6g;5;29?l2e2900e9h50;9l5=4=831vn?;i:187>5<7s-;3j7j?;I64g>N3?81/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm24g94?2=83:p(<6i:e28L11d3A><=6*j5;38m13=831b8o4?::k7b?6=3f;3>7>5;|`11a<72=0;6=u+19d9`5=O<>i0D99>;%g6>4=n<<0;66g;b;29?l2a2900c<6=:188yg42k3:187>50z&2<c<c82B?;n5G4638 `3=92c?97>5;h6a>5<<a=l1<75`19094?=zj;?i6=4;:183!7?n3n;7E:8c:J734=#m<0:7d:::188m1d=831b8k4?::m2<7<722wi>8o50;694?6|,82m6i>4H55`?M2092.n97?4i5794?=n<k0;66g;f;29?j7?:3:17pl=5883>1<729q/=5h5d19K02e<@==:7)k::09j00<722c?n7>5;h6e>5<<g8296=44}c06<?6=<3:1<v*>8g8g4>N3?j1C8:?4$d795>o3=3:17d:m:188m1`=831d=5<50;9~f4`f290?6=4?{%3;b?b73A><o6F;709'a0<63`>>6=44i5`94?=n<o0;66a>8383>>{e9o31<7:50;2x 4>a2m:0D99l;I645>"b=3;0e9;50;9j0g<722c?j7>5;n3;6?6=3th:j54?:583>5}#91l1h=5G46a8L1163-o>6<5f4483>>o3j3:17d:i:188k4>52900qo?i7;290?6=8r.:4k4k0:J73f=O<>;0(h;51:k71?6=3`>i6=44i5d94?=h9181<75rb0d5>5<3290;w)?7f;f3?M20k2B?;<5+e482?l222900e9l50;9j0c<722e:4?4?::a5c3=83>1<7>t$0:e>a6<@==h7E:81:&f1?7<a=?1<75f4c83>>o3n3:17b?72;29?xd6n=0;694?:1y'5=`=l91C8:m4H552?!c2281b884?::k7f?6=3`>m6=44o0:1>5<<uk;m?7>54;294~"60o0o<6F;7b9K027<,l?1=6g;5;29?l2e2900e9h50;9l5=4=831vn<h=:187>5<7s-;3j7j?;I64g>N3?81/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25g94?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25f94?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25a94?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25`94?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25c94?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25;94?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25:94?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25594?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25494?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm25794?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d:94?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d594?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d494?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d794?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d694?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d194?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d094?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d394?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1d294?2=83:p(<6i:e28L11d3A><=6F;2:&277<2>:1/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm1e494?2=83:p(<6i:e28L11d3A><=6*j5;38m13=831b8o4?::k7b?6=3f;3>7>5;|`2`0<72=0;6=u+19d9`5=O<>i0D99>;%g6>4=n<<0;66g;b;29?l2a2900c<6=:188yg7c<3:187>50z&2<c<c82B?;n5G4638 `3=92c?97>5;h6a>5<<a=l1<75`19094?=zj8n86=4;:183!7?n3n;7E:8c:J734=#m<0:7d:::188m1d=831b8k4?::m2<7<722wi=i<50;694?6|,82m6i>4H55`?M2092.n97?4i5794?=n<k0;66g;f;29?j7?:3:17pl>d083>1<729q/=5h5d19K02e<@==:7)k::09j00<722c?n7>5;h6e>5<<g8296=44}c3g4?6=<3:1<v*>8g8g4>N3?j1C8:?4$d795>o3=3:17d:m:188m1`=831d=5<50;9~f4ea290?6=4?{%3;b?b73A><o6F;709'a0<63`>>6=44i5`94?=n<o0;66a>8383>>{e9jo1<7:50;2x 4>a2m:0D99l;I645>"b=3;0e9;50;9j0g<722c?j7>5;n3;6?6=3th9?l4?:583>5}#91l1h=5G46a8L1163-o>6<5f4483>>o3j3:17d:i:188k4>52900qo<<9;290?6=8r.:4k4k0:J73f=O<>;0(h;51:k71?6=3`>i6=44i5d94?=h9181<75rb31;>5<3290;w)?7f;f3?M20k2B?;<5+e482?l222900e9l50;9j0c<722e:4?4?::a661=83>1<7>t$0:e>a6<@==h7E:81:&f1?7<a=?1<75f4c83>>o3n3:17b?72;29?xd5;?0;694?:1y'5=`=l91C8:m4H552?!c2281b884?::k7f?6=3`>m6=44o0:1>5<<uk8897>54;294~"60o0o<6F;7b9K027<,l?1=6g;5;29?l2e2900e9h50;9l5=4=831vn?=;:187>5<7s-;3j7j?;I64g>N3?81/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm22194?2=83:p(<6i:e28L11d3A><=6*j5;38m13=831b8o4?::k7b?6=3f;3>7>5;|`177<72=0;6=u+19d9`5=O<>i0D99>;%g6>4=n<<0;66g;b;29?l2a2900c<6=:188yg4493:187>50z&2<c<c82B?;n5G4638 `3=92c?97>5;h6a>5<<a=l1<75`19094?=zj;n<6=4::183!7?n3n:7E:8c:J734=#m<0:7d:::188m10=831b8o4?::k7b?6=3f;3>7>5;|`1`3<72<0;6=u+19d9`4=O<>i0D99>;%g6>4=n<<0;66g;6;29?l2e2900e9h50;9l5=4=831vn?j::186>5<7s-;3j7j>;I64g>N3?81/i84>;h66>5<<a=<1<75f4c83>>o3n3:17b?72;29?xd5l=0;684?:1y'5=`=l81C8:m4H552?!c2281b884?::k72?6=3`>i6=44i5d94?=h9181<75rb3f0>5<2290;w)?7f;f2?M20k2B?;<5+e482?l222900e9850;9j0g<722c?j7>5;n3;6?6=3th9h?4?:483>5}#91l1h<5G46a8L1163-o>6<5f4483>>o3>3:17d:m:188m1`=831d=5<50;9~f7b7290>6=4?{%3;b?b63A><o6F;709'a0<63`>>6=44i5494?=n<k0;66g;f;29?j7?:3:17pl=cg83>0<729q/=5h5d29K02e<@==:7)k::79j00<722c?:7>5;h6e>5<<a82:6=44o0:1>5<<uk8o=7>55;294~"60o0o=6F;7b9K027<,l?1=6g;5;29?l212900e9l50;9j0c<722e:4?4?::a6f2=8391<7>t$0:e>11e3A><o6F;709j0=<722c:>44?::m23g<722wi>n=50;194?6|,82m699m;I64g>N3?81b854?::k26<<722e:;o4?::a6gg=83>1<7>t$0:e>4543A><o6F;709j0=<722c>=7>5;h3;<?6=3f;<n7>5;|`1g7<72:0;6=u+19d902d<@==h7E:81:k7<?6=3`;957>5;n34f?6=3th9n54?:583>5}#91l1=>=4H55`?M2092c?47>5;h72>5<<a8236=44o05a>5<<uk8h=7>53;294~"60o0?;o5G46a8L1163`>36=44i00:>5<<g8=i6=44}c0a2?6=<3:1<v*>8g8276=O<>i0D99>;h6;>5<<a<;1<75f19:94?=h9>h1<75rb3a3>5<4290;w)?7f;64f>N3?j1C8:?4i5:94?=n9;31<75`16`94?=zj;h?6=4;:183!7?n3;8?6F;7b9K027<a=21<75f5083>>o6010;66a>7c83>>{e:kl1<7=50;2x 4>a2==i7E:8c:J734=n<10;66g>2883>>i6?k0;66sm2c094?2=83:p(<6i:010?M20k2B?;<5f4983>>o293:17d?78;29?j70j3:17pl=bd83>6<729q/=5h546`8L11d3A><=6g;8;29?l7513:17b?8b;29?xd5j90;694?:1y'5=`=9:90D99l;I645>o303:17d;>:188m4>?2900c<9m:188yg4el3:1?7>50z&2<c<3?k1C8:m4H552?l2?2900e<<6:188k41e2900qo<ne;290?6=8r.:4k4>329K02e<@==:7d:7:188m07=831b=5650;9l52d=831vn?ll:180>5<7s-;3j7:8b:J73f=O<>;0e9650;9j57?=831d=:l50;9~f7gd290?6=4?{%3;b?74;2B?;n5G4638m1>=831b9<4?::k2<=<722e:;o4?::a6`?=83?1<7>t$0:e>a7<@==h7E:81:&f1?7<a=?1<75f4783>>o3j3:17d:i:188k4>52900qo<j8;291?6=8r.:4k4k1:J73f=O<>;0(h;51:k71?6=3`>=6=44i5`94?=n<o0;66a>8383>>{e:l=1<7;50;2x 4>a2m;0D99l;I645>"b=3;0e9;50;9j03<722c?n7>5;h6e>5<<g8296=44}c0f2?6==3:1<v*>8g8g5>N3?j1C8:?4$d795>o3=3:17d:9:188m1d=831b8k4?::m2<7<722wi>h;50;794?6|,82m6i?4H55`?M2092.n97?4i5794?=n<?0;66g;b;29?l2a2900c<6=:188yg4b<3:197>50z&2<c<c92B?;n5G4638 `3=92c?97>5;h65>5<<a=h1<75f4g83>>i60;0;66sm2d194?3=83:p(<6i:e38L11d3A><=6*j5;38m13=831b8;4?::k7f?6=3`>m6=44o0:1>5<<uk8n>7>55;294~"60o0o=6F;7b9K027<,l?1=6g;5;29?l212900e9l50;9j0c<722e:4?4?::a6`7=83?1<7>t$0:e>a7<@==h7E:81:&f1?7<a=?1<75f4783>>o3j3:17d:i:188k4>52900qo<84;290?6=8r.:4k4k2:J73f=O<>;0(h;56:k71?6=3`>m6=44i0:2>5<<g8296=44}c041?6=<3:1<v*>8g8g6>N3?j1C8:?4$d792>o3=3:17d:i:188m4>62900c<6=:188yg41n3:187>50z&2<c<c82B?;n5G4638 `3=92c?97>5;h6a>5<<a=l1<75`19094?=zj;<n6=4;:183!7?n3n;7E:8c:J734=#m<0:7d:::188m1d=831b8k4?::m2<7<722wi?=>50;194?6|,82m699m;I64g>N3?81b854?::k26<<722e:;o4?::a75?=8391<7>t$0:e>11e3A><o6F;709j0=<722c:>44?::m23g<722wi>k:50;694?6|,82m6<=<;I64g>N3?81b854?::k65?6=3`;347>5;n34f?6=3th8<54?:283>5}#91l18:l4H55`?M2092c?47>5;h31=?6=3f;<n7>5;|`1b6<72=0;6=u+19d9565<@==h7E:81:k7<?6=3`?:6=44i0:;>5<<g8=i6=44}c133?6=;3:1<v*>8g873g=O<>i0D99>;h6;>5<<a8826=44o05a>5<<uk8m>7>54;294~"60o0:?>5G46a8L1163`>36=44i4394?=n9121<75`16`94?=zj::=6=4<:183!7?n3><n6F;7b9K027<a=21<75f13;94?=h9>h1<75rb3d2>5<3290;w)?7f;307>N3?j1C8:?4i5:94?=n=80;66g>8983>>i6?k0;66sm31794?5=83:p(<6i:55a?M20k2B?;<5f4983>>o6:00;66a>7c83>>{e:o:1<7:50;2x 4>a28987E:8c:J734=n<10;66g:1;29?l7?03:17b?8b;29?xd48=0;6>4?:1y'5=`=<>h0D99l;I645>o303:17d?=9;29?j70j3:17pl=eg83>1<729q/=5h51218L11d3A><=6g;8;29?l362900e<67:188k41e2900qo=?3;297?6=8r.:4k4;7c9K02e<@==:7d:7:188m44>2900c<9m:188yg4bm3:187>50z&2<c<6;:1C8:m4H552?l2?2900e8?50;9j5=>=831d=:l50;9~f66529086=4?{%3;b?20j2B?;n5G4638m1>=831b=?750;9l52d=831vn?kk:187>5<7s-;3j7?<3:J73f=O<>;0e9650;9j14<722c:454?::m23g<722wi?=?50;194?6|,82m699m;I64g>N3?81b854?::k26<<722e:;o4?::a6`e=83>1<7>t$0:e>4543A><o6F;709j0=<722c>=7>5;h3;<?6=3f;<n7>5;|`1ag<72=0;6=u+19d9565<@==h7E:81:k7<?6=3`?:6=44i0:;>5<<g8=i6=44}c121?6=<3:1<v*>8g8g4>N3?j1C8:?4$d795>o3=3:17d:m:188m1`=831d=5<50;9~f67c290?6=4?{%3;b?b73A><o6F;709'a0<63`>>6=44i5`94?=n<o0;66a>8383>>{e;8i1<7:50;2x 4>a2m:0D99l;I645>"b=3;0e9;50;9j0g<722c?j7>5;n3;6?6=3th8=o4?:583>5}#91l1h=5G46a8L1163-o>6<5f4483>>o3j3:17d:i:188k4>52900qo=>a;290?6=8r.:4k4k0:J73f=O<>;0(h;51:k71?6=3`>i6=44i5d94?=h9181<75rb23:>5<3290;w)?7f;f3?M20k2B?;<5+e482?l222900e9l50;9j0c<722e:4?4?::a74>=83>1<7>t$0:e>a6<@==h7E:81:&f1?7<a=?1<75f4c83>>o3n3:17b?72;29?xd49>0;694?:1y'5=`=l91C8:m4H552?!c2281b884?::k7f?6=3`>m6=44o0:1>5<<uk9::7>54;294~"60o0o<6F;7b9K027<,l?1=6g;5;29?l2e2900e9h50;9l5=4=831vn>?;:187>5<7s-;3j7j?;I64g>N3?81/i84>;h66>5<<a=h1<75f4g83>>i60;0;66sm33:94?3=83:p(<6i:e38L11d3A><=6*j5;38m13=831b8;4?::k7f?6=3`>m6=44o0:1>5<<uk82?7>54;294~"60o0:?>5G46a8L1163`>36=44i4394?=n9121<75`16`94?=zj;396=4;:183!7?n3;8?6F;7b9K027<a=21<75f5083>>o6010;66a>7c83>>{e:0;1<7:50;2x 4>a28987E:8c:J734=n<10;66g:1;29?l7?03:17b?8b;29?xd5190;694?:1y'5=`=9:90D99l;I645>o303:17d;>:188m4>?2900c<9m:188yg4?n3:187>50z&2<c<6;:1C8:m4H552?l2?2900e8?50;9j5=>=831d=:l50;9~f7>7290?6=4?{%3;b?74;2B?;n5G4638m1>=831b9<4?::k2<=<722e:;o4?::a62`=83>1<7>t$0:e>4543A><o6F;709j0=<722c>=7>5;h3;<?6=3f;<n7>5;|`13`<72=0;6=u+19d9565<@==h7E:81:k7<?6=3`?:6=44i0:;>5<<g8=i6=44}c04`?6=<3:1<v*>8g8276=O<>i0D99>;h6;>5<<a<;1<75f19:94?=h9>h1<75rb35`>5<3290;w)?7f;307>N3?j1C8:?4i5:94?=n=80;66g>8983>>i6?k0;66sm3c`94?3=83:p(<6i:e38L11d3A><=6*j5;38m13=831b8;4?::k7f?6=3`>m6=44o0:1>5<<uk9i57>55;294~"60o0o=6F;7b9K027<,l?1=6g;5;29?l212900e9l50;9j0c<722e:4?4?::a7gg=83?1<7>t$0:e>a5<@==h7E:81:&f1?0<a=?1<75f4783>>o3n3:17d?71;29?j7?:3:17pl<bb83>0<729q/=5h5d09K02e<@==:7)k::09j00<722c?:7>5;h6a>5<<a=l1<75`19094?=zj:ho6=4::183!7?n3n:7E:8c:J734=#m<0:7d:::188m10=831b8o4?::k7b?6=3f;3>7>5;|`0g5<72<0;6=u+19d9`4=O<>i0D99>;%g6>4=n<<0;66g;6;29?l2e2900e9h50;9l5=4=831vn>lj:186>5<7s-;3j7j>;I64g>N3?81/i84>;h66>5<<a=<1<75f4c83>>o3n3:17b?72;29?xd4jo0;684?:1y'5=`=l81C8:m4H552?!c2281b884?::k72?6=3`>i6=44i5d94?=h9181<75rb2a2>5<2290;w)?7f;f2?M20k2B?;<5+e482?l222900e9850;9j0g<722c?j7>5;n3;6?6=3th8o?4?:483>5}#91l1h<5G46a8L1163-o>6<5f4483>>o3>3:17d:m:188m1`=831d=5<50;9~f6ea290>6=4?{%3;b?b63A><o6F;709'a0<63`>>6=44i5494?=n<k0;66g;f;29?j7?:3:17pl<ce83>0<729q/=5h5d29K02e<@==:7)k::79j00<722c?:7>5;h6e>5<<a82:6=44o0:1>5<<uk9hi7>55;294~"60o0o=6F;7b9K027<,l?1=6g;5;29?l212900e9l50;9j0c<722e:4?4?::a7a6=83?1<7>t$0:e>a7<@==h7E:81:&f1?7<a=?1<75f4783>>o3j3:17d:i:188k4>52900qo=k1;291?6=8r.:4k4k1:J73f=O<>;0(h;51:k71?6=3`>=6=44i5`94?=n<o0;66a>8383>>{e;m>1<7;50;2x 4>a2m;0D99l;I645>"b=3;0e9;50;9j03<722c?n7>5;h6e>5<<g8296=44}c1g6?6==3:1<v*>8g8g5>N3?j1C8:?4$d795>o3=3:17d:9:188m1d=831b8k4?::m2<7<722wi?i=50;794?6|,82m6i?4H55`?M2092.n97?4i5794?=n<?0;66g;b;29?l2a2900c<6=:188yg5c=3:197>50z&2<c<c92B?;n5G4638 `3=92c?97>5;h65>5<<a=h1<75f4g83>>i60;0;66sm3e494?3=83:p(<6i:e38L11d3A><=6*j5;38m13=831b8;4?::k7f?6=3`>m6=44o0:1>5<<uk9jh7>55;294~"60o0o=6F;7b9K027<,l?1=6g;5;29?l212900e9l50;9j0c<722e:4?4?::a7de=83?1<7>t$0:e>a7<@==h7E:81:&f1?7<a=?1<75f4783>>o3j3:17d:i:188k4>52900qo=ne;291?6=8r.:4k4k1:J73f=O<>;0(h;51:k71?6=3`>=6=44i5`94?=n<o0;66a>8383>>{e;hk1<7;50;2x 4>a2m;0D99l;I645>"b=3;0e9;50;9j03<722c?n7>5;h6e>5<<g8296=44}c1b=?6==3:1<v*>8g8g5>N3?j1C8:?4$d795>o3=3:17d:9:188m1d=831b8k4?::m2<7<722wi?ll50;794?6|,82m6i?4H55`?M2092.n97?4i5794?=n<?0;66g;b;29?l2a2900c<6=:188yg5f?3:197>50z&2<c<c92B?;n5G4638 `3=92c?97>5;h65>5<<a=h1<75f4g83>>i60;0;66sm3`494?3=83:p(<6i:e18L11d3A><=6*j5;48m13=831b8;4?::k7b?6=3`;3=7>5;n3;6?6=3th8m54?:483>5}#91l1h<5G46a8L1163-o>6<5f4483>>o3>3:17d:m:188m1`=831d=5<50;9~f6g2290>6=4?{%3;b?b43A><o6F;709'a0<13`>>6=44i5494?=n<o0;66g>8083>>i60;0;66sm38;94?5=83:p(<6i:55a?M20k2B?;<5f4983>>o6:00;66a>7c83>>{e;021<7=50;2x 4>a2==i7E:8c:J734=n<10;66g>2883>>i6?k0;66sm39g94?2=83:p(<6i:010?M20k2B?;<5f4983>>o293:17d?78;29?j70j3:17pl<9683>6<729q/=5h546`8L11d3A><=6g;8;29?l7513:17b?8b;29?xd40j0;694?:1y'5=`=9:90D99l;I645>o303:17d;>:188m4>?2900c<9m:188yg5>>3:1?7>50z&2<c<3?k1C8:m4H552?l2?2900e<<6:188k41e2900qo=7a;290?6=8r.:4k4>329K02e<@==:7d:7:188m07=831b=5650;9l52d=831vn>7::180>5<7s-;3j7:8b:J73f=O<>;0e9650;9j57?=831d=:l50;9~f6>?290?6=4?{%3;b?74;2B?;n5G4638m1>=831b9<4?::k2<=<722e:;o4?::a7<2=8391<7>t$0:e>11e3A><o6F;709j0=<722c:>44?::m23g<722wi?5850;694?6|,82m6<=<;I64g>N3?81b854?::k65?6=3`;347>5;n34f?6=3th85>4?:283>5}#91l18:l4H55`?M2092c?47>5;h31=?6=3f;<n7>5;|`0<1<72=0;6=u+19d9565<@==h7E:81:k7<?6=3`?:6=44i0:;>5<<g8=i6=44}c1:6?6=;3:1<v*>8g873g=O<>i0D99>;h6;>5<<a8826=44o05a>5<<uk93>7>54;294~"60o0:?>5G46a8L1163`>36=44i4394?=n9121<75`16`94?=zj:3:6=4<:183!7?n3><n6F;7b9K027<a=21<75f13;94?=h9>h1<75rb2:3>5<3290;w)?7f;307>N3?j1C8:?4i5:94?=n=80;66g>8983>>i6?k0;66sm38294?5=83:p(<6i:55a?M20k2B?;<5f4983>>o6:00;66a>7c83>>{e;>o1<7:50;2x 4>a28987E:8c:J734=n<10;66g:1;29?l7?03:17b?8b;29?xd4mh0;684?:1y'5=`=l81C8:m4H552?!c2281b884?::k72?6=3`>i6=44i5d94?=h9181<75rb2g:>5<2290;w)?7f;f2?M20k2B?;<5+e482?l222900e9850;9j0g<722c?j7>5;n3;6?6=3th8i54?:483>5}#91l1h<5G46a8L1163-o>6<5f4483>>o3>3:17d:m:188m1`=831d=5<50;9~f6c0290>6=4?{%3;b?b63A><o6F;709'a0<63`>>6=44i5494?=n<k0;66g;f;29?j7?:3:17pl<e783>0<729q/=5h5d09K02e<@==:7)k::09j00<722c?:7>5;h6a>5<<a=l1<75`19094?=zj:o>6=4::183!7?n3n:7E:8c:J734=#m<0:7d:::188m10=831b8o4?::k7b?6=3f;3>7>5;|`0a1<72<0;6=u+19d9`4=O<>i0D99>;%g6>4=n<<0;66g;6;29?l2e2900e9h50;9l5=4=831vn>k<:186>5<7s-;3j7j>;I64g>N3?81/i84>;h66>5<<a=<1<75f4c83>>o3n3:17b?72;29?xd4m;0;684?:1y'5=`=l81C8:m4H552?!c2281b884?::k72?6=3`>i6=44i5d94?=h9181<75rb2g2>5<2290;w)?7f;f2?M20k2B?;<5+e482?l222900e9850;9j0g<722c?j7>5;n3;6?6=3th8??4?:583>5}#91l1=>=4H55`?M2092c?47>5;h72>5<<a8236=44o05a>5<<uk98?7>54;294~"60o0:?>5G46a8L1163`>36=44i4394?=n9121<75`16`94?=zj:9?6=4;:183!7?n3;8?6F;7b9K027<a=21<75f5083>>o6010;66a>7c83>>{e;:?1<7:50;2x 4>a28987E:8c:J734=n<10;66g:1;29?l7?03:17b?8b;29?xd4;?0;694?:1y'5=`=9:90D99l;I645>o303:17d;>:188m4>?2900c<9m:188yg53=3:187>50z&2<c<6;:1C8:m4H552?l2?2900e8?50;9j5=>=831d=:l50;9~f621290?6=4?{%3;b?74;2B?;n5G4638m1>=831b9<4?::k2<=<722e:;o4?::a711=83>1<7>t$0:e>4543A><o6F;709j0=<722c>=7>5;h3;<?6=3f;<n7>5;|`00=<72=0;6=u+19d9565<@==h7E:81:k7<?6=3`?:6=44i0:;>5<<g8=i6=44}c17=?6=<3:1<v*>8g8276=O<>i0D99>;h6;>5<<a<;1<75f19:94?=h9>h1<75rb27a>5<3290;w)?7f;307>N3?j1C8:?4i5:94?=n=80;66g>8983>>i6?k0;66sm34a94?2=83:p(<6i:010?M20k2B?;<5f4983>>o293:17d?78;29?j70j3:17pl<5e83>1<729q/=5h51218L11d3A><=6g;8;29?l362900e<67:188k41e2900qo=:e;290?6=8r.:4k4>329K02e<@==:7d:7:188m07=831b=5650;9l52d=831vn>;i:187>5<7s-;3j7?<3:J73f=O<>;0e9650;9j14<722c:454?::m23g<722wi?;k50;694?6|,82m6i>4H55`?M2092.n97?4i5794?=n<k0;66g;f;29?j7?:3:17pl<6g83>1<729q/=5h5d19K02e<@==:7)k::09j00<722c?n7>5;h6e>5<<g8296=44}c15e?6==3:1<v*>8g8g5>N3?j1C8:?4$d795>o3=3:17d:9:188m1d=831b8k4?::m2<7<722wi8?j50;794?6|,82m6i:4H55`?M2092.n97?4i5794?=n<?0;66g;f;29?l7?;3:17b?72;29?xd3:j0;684?:1y'5=`=l=1C8:m4H552?!c2281b884?::k72?6=3`>m6=44i0:0>5<<g8296=44}c61f?6==3:1<v*>8g8g0>N3?j1C8:?4$d795>o3=3:17d:9:188m1`=831b=5=50;9l5=4=831vn9<n:186>5<7s-;3j7j;;I64g>N3?81/i84>;h66>5<<a=<1<75f4g83>>o60:0;66a>8383>>{e<;31<7;50;2x 4>a2m>0D99l;I645>"b=3;0e9;50;9j03<722c?j7>5;h3;7?6=3f;3>7>5;|`76=<72<0;6=u+19d9`1=O<>i0D99>;%g6>4=n<<0;66g;6;29?l2a2900e<6<:188k4>52900qo:=6;291?6=8r.:4k4k4:J73f=O<>;0(h;51:k71?6=3`>=6=44i5d94?=n9191<75`19094?=zj=8>6=4::183!7?n3n?7E:8c:J734=#m<0:7d:::188m10=831b8k4?::k2<6<722e:4?4?::a072=83?1<7>t$0:e>a2<@==h7E:81:&f1?7<a=?1<75f4783>>o3n3:17d?73;29?j7?:3:17pl;2283>0<729q/=5h5d59K02e<@==:7)k::09j00<722c?:7>5;h6e>5<<a8286=44o0:1>5<<uk>9>7>55;294~"60o0o86F;7b9K027<,l?1=6g;5;29?l212900e9h50;9j5=5=831d=5<50;9~f146290>6=4?{%3;b?b33A><o6F;709'a0<63`>>6=44i5494?=n<o0;66g>8283>>i60;0;66sm43294?3=83:p(<6i:e68L11d3A><=6*j5;38m13=831b8;4?::k7b?6=3`;3?7>5;n3;6?6=3th?=k4?:483>5}#91l1h95G46a8L1163-o>6<5f4483>>o3>3:17d:i:188m4>42900c<6=:188yg26m3:197>50z&2<c<c<2B?;n5G4638 `3=92c?97>5;h65>5<<a=l1<75f19194?=h9181<75rb53g>5<2290;w)?7f;f7?M20k2B?;<5+e482?l222900e9850;9j0c<722c:4>4?::m2<7<722wi8<l50;794?6|,82m6i:4H55`?M2092.n97?4i5794?=n<?0;66g;f;29?l7?;3:17b?72;29?xd39h0;684?:1y'5=`=l=1C8:m4H552?!c2281b884?::k72?6=3`>m6=44i0:0>5<<g8296=44}c62=?6==3:1<v*>8g8g0>N3?j1C8:?4$d795>o3=3:17d:9:188m1`=831b=5=50;9l5=4=831vn9?7:186>5<7s-;3j7j;;I64g>N3?81/i84>;h66>5<<a=<1<75f4g83>>o60:0;66a>8383>>{e<8=1<7;50;2x 4>a2m>0D99l;I645>"b=3;0e9;50;9j03<722c?j7>5;h3;7?6=3f;3>7>5;|`753<72<0;6=u+19d9`1=O<>i0D99>;%g6>4=n<<0;66g;6;29?l2a2900e<6<:188k4>52900qo:>5;291?6=8r.:4k4k4:J73f=O<>;0(h;51:k71?6=3`>=6=44i5d94?=n9191<75`19094?=zj=;?6=4::183!7?n3n?7E:8c:J734=#m<0:7d:::188m10=831b8k4?::k2<6<722e:4?4?::a045=83?1<7>t$0:e>a2<@==h7E:81:&f1?7<a=?1<75f4783>>o3n3:17d?73;29?j7?:3:17pl;1383>0<729q/=5h5d59K02e<@==:7)k::09j00<722c?:7>5;h6e>5<<a8286=44o0:1>5<<uk>8?7>55;294~"60o0o86F;7b9K027<,l?1=6g;5;29?l212900e9h50;9j5=5=831d=5<50;9~f155290>6=4?{%3;b?b33A><o6F;709'a0<63`>>6=44i5494?=n<o0;66g>8283>>i60;0;66sm42394?3=83:p(<6i:e68L11d3A><=6*j5;38m13=831b8;4?::k7b?6=3`;3?7>5;n3;6?6=3th??=4?:483>5}#91l1h95G46a8L1163-o>6<5f4483>>o3>3:17d:i:188m4>42900c<6=:188yg25n3:197>50z&2<c<c<2B?;n5G4638 `3=92c?97>5;h65>5<<a=l1<75f19194?=h9181<75rb50f>5<2290;w)?7f;f7?M20k2B?;<5+e482?l222900e9850;9j0c<722c:4>4?::m2<7<722wi8?950;794?6|,82m6i:4H55`?M2092.n97?4i5794?=n<?0;66g;f;29?l7?;3:17b?72;29?xd39j0;684?:1y'5=`=l=1C8:m4H552?!c2281b884?::k72?6=3`>m6=44i0:0>5<<g8296=44}c625?6==3:1<v*>8g8g0>N3?j1C8:?4$d795>o3=3:17d:9:188m1`=831b=5=50;9l5=4=831vn9??:186>5<7s-;3j7j;;I64g>N3?81/i84>;h66>5<<a=<1<75f4g83>>o60:0;66a>8383>>{e<?h1<7=50;2x 4>a288n7E:8c:J734=#m<0:56gk9;29?lbf2900c<9m:188yg2183:1?7>50z&2<c<6:l1C8:m4H552?!c22830ei750;9j`d<722e:;o4?::a640=8391<7>t$0:e>44b3A><o6F;709'a0<6l2co57>5;hfb>5<<g8=i6=44}c3a0?6=;3:1<v*>8g826`=O<>i0D99>;%g6>4b<am31<75fd`83>>i6?k0;66sm1`294?5=83:p(<6i:00f?M20k2B?;<5+e482`>oc13:17djn:188k41e2900qo?6f;297?6=8r.:4k4>2d9K02e<@==:7)k::0f8ma?=831bhl4?::m23g<722wi=4k50;194?6|,82m6<<j;I64g>N3?81/i84>d:kg=?6=3`nj6=44o05a>5<<uk;2h7>53;294~"60o0:>h5G46a8L1163-o>6<j4ie;94?=nlh0;66a>7c83>>{e90i1<7=50;2x 4>a288n7E:8c:J734=#m<0:h6gk9;29?lbf2900c<9m:188yg7>j3:1?7>50z&2<c<6:l1C8:m4H552?!c228n0ei750;9j`d<722e:;o4?::a5<g=8391<7>t$0:e>44b3A><o6F;709'a0<6l2co57>5;hfb>5<<g8=i6=44}c3:=?6=;3:1<v*>8g826`=O<>i0D99>;%g6>4b<am31<75fd`83>>i6?k0;66sm18:94?5=83:p(<6i:00f?M20k2B?;<5+e482`>oc13:17djn:188k41e2900qo?67;297?6=8r.:4k4>2d9K02e<@==:7)k::0f8ma?=831bhl4?::m23g<722wi=4850;194?6|,82m6<<j;I64g>N3?81/i84>d:kg=?6=3`nj6=44o05a>5<<uk;297>53;294~"60o0:>h5G46a8L1163-o>6<j4ie;94?=nlh0;66a>7c83>>{e90>1<7=50;2x 4>a288n7E:8c:J734=#m<0:h6gk9;29?lbf2900c<9m:188yg7>;3:1?7>50z&2<c<6:l1C8:m4H552?!c228n0ei750;9j`d<722e:;o4?::a5<4=8391<7>t$0:e>44b3A><o6F;709'a0<6l2co57>5;hfb>5<<g8=i6=44}c3:5?6=;3:1<v*>8g826`=O<>i0D99>;%g6>4b<am31<75fd`83>>i6?k0;66sm18294?5=83:p(<6i:00f?M20k2B?;<5+e482`>oc13:17djn:188k41e2900qo<83;290?6=8r.:4k4>2g9K02e<@==:7)k::ba8ma?=831bhl4?::kgf?6=3f;<n7>5;|`15=<72=0;6=u+19d957`<@==h7E:81:&f1?433`n26=44iec94?=nlk0;66a>7c83>>{e9k<1<7:50;2x 4>a288m7E:8c:J734=#m<0986gk9;29?lbf2900eil50;9l52d=831vn?9>:186>5<7s-;3j7?<0:J73f=O<>;0(h;51`9j`<<722com7>5;hfa>5<<ami1<75`16`94?=zj;;j6=4::183!7?n3;8<6F;7b9K027<,l?1=k5fd883>>oci3:17djm:188mae=831d=:l50;9~f4d?290>6=4?{%3;b?7482B?;n5G4638 `3=9o1bh44?::kge?6=3`ni6=44iea94?=h9>h1<75rb354>5<2290;w)?7f;304>N3?j1C8:?4$d7964=nl00;66gka;29?lbe2900eim50;9l52d=831vn?8m:187>5<7s-;3j7?=f:J73f=O<>;0(h;52c9j`<<722com7>5;hfa>5<<g8=i6=44}c02g?6=;3:1<v*>8g826`=O<>i0D99>;%g6>4b<am31<75fd`83>>i6?k0;66sm1cc94?5=83:p(<6i:00f?M20k2B?;<5+e482`>oc13:17djn:188k41e2900qo<>e;290?6=8r.:4k4>2g9K02e<@==:7)k::368ma?=831bhl4?::kgf?6=3f;<n7>5;|`2ff<72=0;6=u+19d957`<@==h7E:81:&f1?433`n26=44iec94?=nlk0;66a>7c83>>{e:;:1<7;50;2x 4>a289;7E:8c:J734=#m<0:j6gk9;29?lbf2900eil50;9j`f<722e:;o4?::a5gc=83?1<7>t$0:e>4573A><o6F;709'a0<6n2co57>5;hfb>5<<amh1<75fdb83>>i6?k0;66sm33c94?3=83:p(<6i:013?M20k2B?;<5+e4814>oc13:17djn:188mad=831bhn4?::m23g<722wi88o50;694?6|,82m6<<i;I64g>N3?81/i84:0:kg=?6=3`nj6=44ie`94?=h9>h1<75rb34b>5<2290;w)?7f;304>N3?j1C8:?4$d7957=nl00;66gka;29?lbe2900eim50;9l52d=831vn?7k:180>5<7s-;3j7?=e:J73f=O<>;0(h;5239j`<<722com7>5;n34f?6=3th94l4?:283>5}#91l1=?k4H55`?M2092.n97<=;hf:>5<<amk1<75`16`94?=zj:<26=4::183!7?n3;8<6F;7b9K027<,l?1>>5fd883>>oci3:17djm:188mae=831d=:l50;9~f634290>6=4?{%3;b?7482B?;n5G4638 `3=::1bh44?::kge?6=3`ni6=44iea94?=h9>h1<75rb263>5<2290;w)?7f;304>N3?j1C8:?4$d7966=nl00;66gka;29?lbe2900eim50;9l52d=831vn>87:186>5<7s-;3j7?<0:J73f=O<>;0(h;5229j`<<722com7>5;hfa>5<<ami1<75`16`94?=zj:?96=4::183!7?n3;8<6F;7b9K027<,l?1>>5fd883>>oci3:17djm:188mae=831d=:l50;9~f65a290>6=4?{%3;b?7482B?;n5G4638 `3=::1bh44?::kge?6=3`ni6=44iea94?=h9>h1<75rb3;`>5<2290;w)?7f;304>N3?j1C8:?4$d7966=nl00;66gka;29?lbe2900eim50;9l52d=831vn?66:186>5<7s-;3j7?<0:J73f=O<>;0(h;5229j`<<722com7>5;hfa>5<<ami1<75`16`94?=zj:<<6=4::183!7?n3;8<6F;7b9K027<,l?1>>5fd883>>oci3:17djm:188mae=831d=:l50;9~f636290>6=4?{%3;b?7482B?;n5G4638 `3=::1bh44?::kge?6=3`ni6=44iea94?=h9>h1<75rb21f>5<2290;w)?7f;304>N3?j1C8:?4$d7966=nl00;66gka;29?lbe2900eim50;9l52d=831vn?7m:186>5<7s-;3j7?<0:J73f=O<>;0(h;5229j`<<722com7>5;hfa>5<<ami1<75`16`94?=zj;236=4::183!7?n3;8<6F;7b9K027<,l?1>>5fd883>>oci3:17djm:188mae=831d=:l50;9~f601290>6=4?{%3;b?7482B?;n5G4638 `3=::1bh44?::kge?6=3`ni6=44iea94?=h9>h1<75rb273>5<2290;w)?7f;304>N3?j1C8:?4$d7966=nl00;66gka;29?lbe2900eim50;9l52d=831vn>=k:186>5<7s-;3j7?<0:J73f=O<>;0(h;5229j`<<722com7>5;hfa>5<<ami1<75`16`94?=zj;3j6=4::183!7?n3;8<6F;7b9K027<,l?1>>5fd883>>oci3:17djm:188mae=831d=:l50;9~f7>0290>6=4?{%3;b?7482B?;n5G4638 `3=::1bh44?::kge?6=3`ni6=44iea94?=h9>h1<75rb252>5<3290;w)?7f;31b>N3?j1C8:?4$d79ga=nl00;66gka;29?lbe2900c<9m:188yg51k3:187>50z&2<c<6:o1C8:m4H552?!c22jn0ei750;9j`d<722con7>5;n34f?6=3th9m?4?:583>5}#91l1=?h4H55`?M2092.n97mk;hf:>5<<amk1<75fdc83>>i6?k0;66sm37794?2=83:p(<6i:00e?M20k2B?;<5+e486?lb>2900eio50;9j`g<722e:;o4?::a71`=83>1<7>t$0:e>44a3A><o6F;709'a0<23`n26=44iec94?=nlk0;66a>7c83>>{e;:i1<7:50;2x 4>a288m7E:8c:J734=#m<0>7dj6:188mag=831bho4?::m23g<722wi>4750;794?6|,82m6<=?;I64g>N3?81/i84=3:kg=?6=3`nj6=44ie`94?=nlj0;66a>7c83>>{e:1<1<7;50;2x 4>a289;7E:8c:J734=#m<09?6gk9;29?lbf2900eil50;9j`f<722e:;o4?::a675=8391<7>t$0:e>44b3A><o6F;709'a0<5:2co57>5;hfb>5<<g8=i6=44}c3`5?6=;3:1<v*>8g826`=O<>i0D99>;%g6>74<am31<75fd`83>>i6?k0;66sm23494?2=83:p(<6i:00e?M20k2B?;<5+e482a>oc13:17djn:188mad=831d=:l50;9~f4e3290?6=4?{%3;b?75n2B?;n5G4638 `3=9l1bh44?::kge?6=3`ni6=44o05a>5<<uk9<>7>53;294~"60o0:>h5G46a8L1163-o>6<?4ie;94?=nlh0;66a>7c83>>{e:kh1<7<50;2x 4>a288o7E:8c:J734=#m<0:=6gk9;29?j70j3:17pl=b883>7<729q/=5h513f8L11d3A><=6*j5;32?lb>2900c<9m:188yg4e?3:1>7>50z&2<c<6:m1C8:m4H552?!c228;0ei750;9l52d=831vn?l::181>5<7s-;3j7?=d:J73f=O<>;0(h;5109j`<<722e:;o4?::a6g5=8381<7>t$0:e>44c3A><o6F;709'a0<692co57>5;n34f?6=3th9n<4?:383>5}#91l1=?j4H55`?M2092.n97?>;hf:>5<<g8=i6=44}c0bb?6=:3:1<v*>8g826a=O<>i0D99>;%g6>47<am31<75`16`94?=zj;ko6=4=:183!7?n3;9h6F;7b9K027<,l?1=<5fd883>>i6?k0;66sm39d94?4=83:p(<6i:00g?M20k2B?;<5+e4825>oc13:17b?8b;29?xd40m0;6?4?:1y'5=`=9;n0D99l;I645>"b=3;:7dj6:188k41e2900qo=7b;296?6=8r.:4k4>2e9K02e<@==:7)k::038ma?=831d=:l50;9~f6>>29096=4?{%3;b?75l2B?;n5G4638 `3=981bh44?::m23g<722wi?5950;094?6|,82m6<<k;I64g>N3?81/i84>1:kg=?6=3f;<n7>5;|`0<0<72;0;6=u+19d957b<@==h7E:81:&f1?763`n26=44o05a>5<<uk93?7>52;294~"60o0:>i5G46a8L1163-o>6<?4ie;94?=h9>h1<75rb2:2>5<5290;w)?7f;31`>N3?j1C8:?4$d7954=nl00;66a>7c83>>{e;>l1<7<50;2x 4>a288o7E:8c:J734=#m<0:=6gk9;29?j70j3:17pl=c483>7<729q/=5h513f8L11d3A><=6*j5;32?lb>2900c<9m:188yg5>i3:1>7>50z&2<c<6:m1C8:m4H552?!c228;0ei750;9l52d=831vn?h7:180>5<7s-;3j7?=e:J73f=O<>;0(h;5239j`<<722com7>5;n34f?6=3th9j44?:283>5}#91l1=?k4H55`?M2092.n97<=;hf:>5<<amk1<75`16`94?=zj;lj6=4<:183!7?n3;9i6F;7b9K027<,l?1>?5fd883>>oci3:17b?8b;29?xd5nk0;6>4?:1y'5=`=9;o0D99l;I645>"b=3897dj6:188mag=831d=:l50;9~f7`d29086=4?{%3;b?75m2B?;n5G4638 `3=:;1bh44?::kge?6=3f;<n7>5;|`1ba<72:0;6=u+19d957c<@==h7E:81:&f1?453`n26=44iec94?=h9>h1<75rb3df>5<4290;w)?7f;31a>N3?j1C8:?4$d7967=nl00;66gka;29?j70j3:17pl=fg83>6<729q/=5h513g8L11d3A><=6*j5;01?lb>2900eio50;9l52d=831vn?h::180>5<7s-;3j7?=e:J73f=O<>;0(h;5239j`<<722com7>5;n34f?6=3th8>n4?:483>5}#91l1=>>4H55`?M2092.n97j:;hf:>5<<amk1<75fdc83>>ock3:17b?8b;29?xd4:k0;684?:1y'5=`=9::0D99l;I645>"b=38;7dj6:188mag=831bho4?::kgg?6=3f;<n7>5;|`036<72:0;6=u+19d957c<@==h7E:81:&f1?763`n26=44iec94?=h9>h1<75rb3d4>5<5290;w)?7f;31<>N3?j1C8:?4ie:94?=h9>h1<75rb24g>5<5290;w)?7f;31<>N3?j1C8:?4ie:94?=h9>h1<75rb301>5<1290;w)?7f;305>N3?j1C8:?4$d7960=nl00;66gka;29?lbe2900eim50;9l57g=831d=:l50;9~f4e7290=6=4?{%3;b?7492B?;n5G4638 `3=:<1bh44?::kge?6=3`ni6=44iea94?=h9;k1<75`16`94?=zj=?36=477;294~N3?81/=5h51968^12=ir21>;4j:07956<6j3l1=;4>4;3`>x"6:>087)jk:59'``<33-nm695+e187?!c62=1/i?4;;%g0>1=#kh0hi6*j6;68 `1=<2.n47:4$d;90>"bi3>0(hl54:&fg?2<,ln186*je;68 ``=<2.m<7:4$g390>"a:3>0(k=54:&e0?2<,o?186*i6;68 c1=<2.m47:4$g;90>"ai3>0(kl54:&eg?2<,on186*ie;68 c`=<2.:<=4;;%335?2<,8:9695+11190>"68=0?7)??5;68 4612=1/==954:&24=<33-;;57:4$02b>1=#99h186*>0b87?!77l3>0(<>j:59'55`=<2.:==4;;%325?2<,8;9695+10190>"69=0?7)?>5;68 4712=1/=<954:&25=<33-;:57:4$03b>1=#98h186*>1b87?!76l3>0(<?j:59'54`=<2.:>=4;;%315?2<,889695+13190>"6:=0?7)?=5;68 4412;1/=575409'a1<33-;3n7<4$555>4>23-><;7?75:l:`?6<fkl1<6`>87826>h60>0986`;79826>h3?00986*lb;af?!7?k390e9750;9j0d<722c?;94?::k`=?6=3`2<6=4+1929<d=i9>l1?65f19g94?=n;?0;6)?70;16?k70n3:07d=;:18'5=6=;<1e=:h51:9j76<72-;3<7=:;o34b?4<3`996=4+192970=i9>l1?65f3083>!7?839>7c?8f;68?l57290/=5>5349m52`==21b>k4?:%3;4?523g;<j784;h0f>5<#91:1?85a16d93>=n:m0;6)?70;16?k70n3207d<l:18'5=6=;<1e=:h59:9j05<72-;3<7=i;o34b?6<3`9n6=4+19297c=i9>l1=65f3e83>!7?839m7c?8f;08?l5d290/=5>53g9m52`=;21b?o4?:%3;4?5a3g;<j7:4;h1b>5<#91:1?k5a16d91>=n;00;6)?70;1e?k70n3<07d=7:18'5=6=;o1e=:h57:9j72<72-;3<7=i;o34b?><3`?26=4+19291==i9>l1<65f5683>!7?83?37c?8f;38?l31290/=5>5599m52`=:21b984?:%3;4?3?3g;<j7=4;h77>5<#91:1955a16d90>=n=:0;6)?70;7;?k70n3?07d8=:18'5=6==11e=:h56:9j24<72-;3<7;7;o34b?1<3`<;6=4+19291==i9>l1465f5g83>!7?83?37c?8f;;8?l3b290/=5>5599m52`=i21b9i4?:%3;4?3?3g;<j7l4;h7`>5<#91:1955a16d9g>=n=k0;6)?70;7;?k70n3n07d;n:18'5=6==11e=:h5e:9j17<72-;3<7;7;o34b?`<3`2=6=4+1929<0=i9>l1<65f8583>!7?832>7c?8f;38?jd0290/=5>5b79m52`=821dn84?:%3;4?d13g;<j7?4;n`0>5<#91:1n;5a16d96>=hj;0;6)?70;`5?k70n3907bl>:18'5=6=j?1e=:h54:9lf5<72-;3<7l9;o34b?3<3fkm6=4+1929f3=i9>l1:65`ad83>!7?83h=7c?8f;58?jgc290/=5>5b79m52`=021dmn4?:%3;4?d13g;<j774;nca>5<#91:1n;5a16d9e>=hih0;6)?70;`5?k70n3h07bo7:18'5=6=j?1e=:h5c:9le2<72-;3<7l9;o34b?b<3fk=6=4+1929f3=i9>l1i65`a483>!7?83h=7c?8f;d8?jg3290/=5>5b79m52`=9910cl=50;&2<5<e>2d:;k4>1:9le7<72-;3<7l9;o34b?7532ej=7>5$0:3>g0<f8=m6<=4;nc3>5<#91:1n;5a16d951=<g0l1<7*>818a2>h6?o0:965`bd83>!7?83h=7c?8f;35?>iel3:1(<6?:c48j41a28=07bll:18'5=6=j?1e=:h51998kgd=83.:4=4m6:l23c<6121dnl4?:%3;4?d13g;<j7?n;:ma=?6=,82;6o84n05e>4d<3fh36=4+1929f3=i9>l1=n54oc694?"6090i:6`>7g82`>=hi00;6)?70;`5?k70n3;n76a6e;29 4>72k<0b<9i:0d8?je0290/=5>5c79m52`=821do84?:%3;4?e13g;<j7?4;na7>5<#91:1o;5a16d96>=hk:0;6)?70;a5?k70n3907dm7:188m4>c2900e99::188m2e=83.:4=48b:l23c<732c<m7>5$0:3>2d<f8=m6<54i6:94?"6090<n6`>7g81?>o0?3:1(<6?:6`8j41a2:10e:850;&2<5<0j2d:;k4;;:k41?6=,82;6:l4n05e>0=<a>>1<7*>8184f>h6?o0=76g83;29 4>72>h0b<9i:698m24=83.:4=48b:l23c<?32c<=7>5$0:3>2d<f8=m6454i6294?"6090<n6`>7g8b?>o1n3:1(<6?:6`8j41a2k10e;j50;&2<5<0j2d:;k4l;:k5g?6=,82;6:l4n05e>a=<a?h1<7*>8184f>h6?o0n76g9a;29 4>72>h0b<9i:g98m3?=83.:4=48b:l23c<6821b:54?:%3;4?1e3g;<j7?>;:k53?6=,82;6:l4n05e>44<3`<=6=4+19293g=i9>l1=>54i7794?"6090<n6`>7g820>=n>=0;6)?70;5a?k70n3;>76g73;29 4>72>h0b<9i:048?l>5290/=5>57c9m52`=9>10e5?50;&2<5<0j2d:;k4>8:9j<5<72-;3<79m;o34b?7>32c<j7>5$0:3>2d<f8=m6<o4;h5f>5<#91:1;o5a16d95g=<a>n1<7*>8184f>h6?o0:o65f7883>!7?83=i7c?8f;3g?>o1m3:1(<6?:6`8j41a28o07d8<:18'5=6=?k1e=:h51g98m=d=83.:4=47a:l23c<732c357>5$0:3>=g<f8=m6<54i9:94?"60903m6`>7g81?>i>;3:1(<6?:808j41a2910c4?50;&2<5<>:2d:;k4>;:m:4?6=,82;64<4n05e>7=<g1l1<7*>818:6>h6?o0876a7e;29 4>72080b<9i:598k=b=83.:4=462:l23c<232e2o7>5$0:3><4<f8=m6;54o8`94?"60902>6`>7g84?>i>i3:1(<6?:808j41a2110c4750;&2<5<>:2d:;k46;:m:<?6=,82;64<4n05e>d=<g0=1<7*>818:6>h6?o0i76a66;29 4>72080b<9i:b98k<3=83.:4=462:l23c<c32e287>5$0:3><4<f8=m6h54o9a94?"60902>6`>7g8e?>id:3:1(<6?:b38j41a2910cn>50;&2<5<d92d:;k4>;:p10b=83<pR8;k;<047?bf348<=7j6;<043?bd348=n7jm;<05e?b>3ty>9o4?:6gxZ1?33W?=:6P:659]0=2<V<<;7S;?f:\620=Y=8:0R97=;_6:5>X3191U85h4^5:f?[2?l2T?4n5Q49`8Z1>f3W>356P:709]126<V<<m7S;9e:\62a=Y=?i0R88m;_75e>X2>01U9;64^47b?[3212T>955Q5458Z0313W?>96P:559]105<V<?970:8d;f5?821?3>m70::c;6e?821>3>m70:95;6e?821<3>m70:9f;6e?821m3>m70<ma;72?84e03?:70<m6;72?84e<3?:70<m2;72?84e83?:70<ne;72?84fk3?:70<jb;3;<>;51:0>=63=93865>;5180>=63=91865>;50o0>=63=81865>;5?o0>=63=7d865>;5?m0>=63=7b865>;40l0>=63<8b865>;40h0>=63<89865>;40?0>=63<85865>;40;0>=63<81865>;4?l0>=63<33865>;4;:0>=63<35865>;4;<0>=63<37865>;4<<0>=63<47865>;4<>0>=63<49865>;4<00>=63<5c865>;4=j0>=63<5e865>;4=l0>=63<5g865>;3=103;63;5982<a=:<<218:;4=57;>2e<5=?36:o4=57;>2><5=?36:94=57;>20<5=?36:;4=57;>22<5=?36:=4=57;>24<5=?36:?4=57;>26<5=?36;h4=57;>3b<5=?36;m4=57;>3d<5=?36;o4=57;>3?<5=?36;64=57;>31<5=?36;84=57;>33<5=?36;:4=57;>=5<5=?365<4=57;>=7<5=?365>4=57;>2`<5=?36:k4=57;>2b<5=?36:74=57;>3c<5=?36;=4=57;>=d<5=?36574=57;>=><uz9=m7>52z\7<0=:;?k1=5<4}r76b?6=;rT>9k5247595=7<5=?h6<6>;|q130<72;qU9=:4=356>4>53ty>;>4?:2y]125<5:=96i74=250>a?<uz?>=7>569y]107<5;k;69;4=57f>13<5=?o69;4=57`>13<5=<=69;4=546>13<5=<?69;4=337>13<5;;869;4=331>13<5;;:69;4=333>13<5;:m69;4=32f>13<5;:o69;4=32`>13<5;<;69;4=37e>13<5;?n69;4=37g>13<5;?h69;4=37a>13<5;?j69;4=37:>13<5;?369;4=36f>13<5;>o69;4=36`>13<5;>i69;4=36b>13<5;>269;4=36;>13<5;><69;4=365>13<5;>>69;4=0f5>13<58n>69;4=0f7>13<58n869;4=0f1>13<58n:69;4=0f3>13<58im69;4=0af>13<5;n<69;4=3f5>13<5;n>69;4=3f7>13<5;n869;4=3f1>13<5;n;69;4=3ae>13<5;n:69;4=3g:>13<5;o369;4=3g4>13<5;o=69;4=3g6>13<5;o?69;4=3g0>13<5;o969;4=3g2>13<5;=?69;4=356>13<5;<m69;4=34f>13<5=8o69;4=50`>13<5=8i69;4=50b>13<5=8269;4=50;>13<5=8=69;4=506>13<5=8?69;4=500>13<5=8969;4=502>13<5=8;69;4=53e>13<5=;n69;4=53g>13<5=;i69;4=53b>13<5=;269;4=53;>13<5=;<69;4=535>13<5=;>69;4=537>13<5=;869;4=531>13<5=9869;4=511>13<5=9:69;4=513>13<5=8m69;4=50f>13<5=8<69;4=53`>13<5=;:69;4=533>13<5=?369o4}r15b?6=:rT><l5237d95=4<uz?=;7>563y]131<5=<269;4=544>13<5=<369;4=54e>13<5=<n69;4=0`1>13<58h:69;4=0`3>13<58km69;4=0cf>13<58ko69;4=0c`>13<58ki69;4=0cb>13<58lj69;4=0d:>13<58l369;4=0d4>13<58l=69;4=0d6>13<58l?69;4=0d0>13<58l969;4=0g;>13<58o<69;4=0g5>13<58o>69;4=0g7>13<58o869;4=0g1>13<58o:69;4=0g3>13<5;9j69;4=31:>13<5;9369;4=314>13<5;9=69;4=316>13<5;9?69;4=310>13<5;9969;4=312>13<5:;>69;4=23g>13<5:;h69;4=23a>13<5:;j69;4=23:>13<5:;369;4=234>13<5:;=69;4=237>13<5:8369;4=2`a>13<5:h269;4=2`b>13<5:hh69;4=2`g>13<5:i;69;4=2`f>13<5:hm69;4=2a2>13<5:i969;4=2ae>13<5:io69;4=2af>13<5:n;69;4=2f2>13<5:n?69;4=2f1>13<5:n869;4=2f6>13<5:n=69;4=2cg>13<5:kh69;4=2cf>13<5:kj69;4=2c:>13<5:ki69;4=2c4>13<5:k=69;4=2c;>13<5:k>69;4=2gb>13<5:o269;4=2g;>13<5:o<69;4=2g5>13<5:o>69;4=2g7>13<5:o869;4=2g1>13<5:o:69;4=24f>13<5:<m69;4=24b>13<5=?36974}r11<?6=:rT>>k5233:95=4<uz9m87>52z\7`2=:<831=5<4}r1e7?6=:rT?h;5240:95=4<uz9m>7>52z\7`0=:<8=1=5<4}r1e5?6=:rT?h95240495=4<uz9m<7>52z\7`6=:<8?1=5<4}r1fb?6=:rT?h?5240695=4<uz9ni7>52z\7`5=:<891=5<4}r1f`?6=:rT?ok5240095=4<uz>;j7>52z\7g`=:<:91=5<4}r63a?6=:rT?oi5242095=4<uz>;h7>52z\7gf=:<:;1=5<4}r63g?6=:rT?oo5242295=4<uz>;n7>52z\7gd=:<;l1=5<4}r63e?6=:rT?o45243g95=4<uz>;57>52z\7g==:<;=1=5<4}r636?6=:rT?o:5240a95=4<uz9m;7>52z\7g0=:<8;1=5<4}r1fg?6=:rT?o95240295=4<uz>;47>52z\7g6=:<;n1=5<4}r633?6=:rT?o?5243a95=4<uz>;:7>52z\7g4=:<;h1=5<4}r631?6=:rT?o=5243c95=4<uz>;87>52z\7fc=:<;31=5<4}r637?6=:rT?nh5243:95=4<uz>;=7>52z\7fa=:<;<1=5<4}r634?6=:rT?nn5243795=4<uz9mj7>52z\7`a=:<;>1=5<4}r1ea?6=:rT?hn5243195=4<uz9mh7>52z\7`g=:<;81=5<4}r1eg?6=:rT?hl5243395=4<uz9mn7>52z\7`<=:<;:1=5<4}r1ee?6=:rT?h55240d95=4<uz9m57>52z\7`4=:<8o1=5<4}r1e<?6=:rT?o;5240f95=4<uz9m:7>52z\7fg=:<8h1=5<4}r1e1?6=:rT?nl5240c95=4<uz>i<7>52z\7=`=:<<214;5rs5cf>5<5sW>2h63;5986=>{t<hn1<7<t^5;`?82203?<7p};ab83>7}Y<0h019;7:448yv2fj3:1>vP;9`9>00>==<1v9on:181[2>127?954:4:p0d?=838pR977;<66<?343ty?m54?:3y]0<1<5=?36;<4}r6a=?6=:rT?m;5244:924=z{=h36=4={_6b1>;3=10386s|4c594?4|V=k?70::8;43?xu3j?0;6?uQ4`18913?2<l0q~:m5;296~X3i;1688655d9~w1d32909wS:n1:?71=<2l2wx8o=50;0xZ1g734>>47;l;|q7f7<72;qU84h4=57;>0d<uz>i=7>52z\7=3=:<<219l5rs5c4>5<5sW>2963;59866>{t9:=1<7mt=55f>41c348io7:7;<0bg?2?348no7;>;<0ff?2?3483j7:7;<04g?2?3492<7:7;<14a?2?3498>7:7;<171?2?349>n7:7;|q1e4<72;q6>l>54g9>6d4=9>h0q~:93;295=}::h:1=5?4=545>4>5348o;7:m;<0g2?2e348o97:m;<0g0?2e348o?7:m;<0g6?2e348o<7:m;<0`b?7?9279h<4;b:?1a<<3j279i54;b:?1a2<3j279i;4;b:?1a0<3j279i94;b:?1a6<3j279i?4;b:?1a4<3j279;94>809>623=91;01?8i:5`8970b2=h0q~<n0;290~;5i90:4?522639`f=:<<k1h45227c9`d=z{=?o6=4<{<66a?2a34>>h7?72:?71f<3>2wx88k50;0x913b282970:90;f:?xu3>10;6>u247;90c=:<?=18;5247:95=4<uz>=57>52z?72<<60;168;l5d89~w13d2908w0::d;6e?822k3;3>63;618ge>{t<?=1<7=t=544>4>534>=47:i;<65f?bf3ty?9k4?:5y>030=91;0198::0:2?821<3;3=63;61823g=z{=<96=4=6z?720<60;16><:54c9>645=<k16><<54c9>647=<k16><>54c9>65`=<k16>=k54c9>65b=<k16>=m54c9>636=<k16>8h54c9>60c=<k16>8j54c9>60e=<k16>8l54c9>60g=<k16>8754c9>60>=<k16>9k54c9>61b=<k16>9m54c9>61d=<k16>9o54c9>61?=<k16>9654c9>611=<k16>9854c9>613=<k16=i854c9>5a3=<k16=i:54c9>5a5=<k16=i<54c9>5a7=<k16=i>54c9>5f`=<k16=nk54c9~w1062909;v3;6582<7=:<;n1=5=4=50`>4>434>9n7?73:?76d<60:168?751918914?282870:=6;3;7>;3:<0:4>5243695=5<5=886<6<;<616?7?;27?><4>829>076=919019?i:0:0?826m3;3?63;1e82<6=:<8h1=5=4=53b>4>434>:57?73:?75=<60:168<9519189171282870:>5;3;7>;39=0:4>5240195=5<5=;96<6<;<607?7?;27???4>829>067=919019=?:0:0?825n3;3?63;2d82<6=:<;=1=5=4=53`>4>434>:=7?73:?755<60:1688o5d`9>00>=91o0q~:9a;297~;3>o0:4<5247g95=7<5=<i6<9m;|q72a<72:9p198i:0:1?856=3>i70=>d;6a?856k3>i70=>b;6a?856i3>i70=>9;6a?85603>i70=>7;6a?856>3>i70=>4;6a?85ej3>i70=m9;6a?85ei3;3=63<bb87f>;4jm0?n63<c187f>;4jl0?n63<bg87f>;4k80?n63<c387f>;4ko0?n63<ce82<4=:;jo18o523e290g=:;m;18o523e690g=:;m818o523e190g=:;m?18o523e490g=:;hn18o523`a90g=:;ho18o523`c90g=:;h318o523``90g=:;h=18o523`495=7<5:k369l4=2c6>4>6349nm7:m;<1f=?2e349n47:m;<1f3?2e349n:7:m;<1f1?2e349n87:m;<1f7?2e349n>7:m;<1f5?2e3ty?:n4?:3cx910b282970?m2;6a?87e93>i70?m0;6a?87fn3>i70?ne;6a?87fl3>i70?nc;6a?87fj3>i70?na;6a?87ai3>i70?i9;6a?87a03>i70?i7;6a?87a>3>i70?i5;6a?87a<3>i70?i3;6a?87a:3>i70?j8;6a?87b?3>i70?j6;6a?87b=3>i70?j4;6a?87b;3>i70?j2;6a?87b93>i70?j0;6a?844i3>i70<<9;6a?84403>i70<<7;6a?844>3>i70<<5;6a?844<3>i70<<3;6a?844:3>i70<<1;6a?85503>i70=9e;6a?851n3>i70=9a;6a?xu5=>0;68u220690c=::?:1=5<4=335>ag<5;;36i74=33b>ae<uz8;n7>53z?151<60;16>4j5d89>6=g=l01v??::181846;3>m70<>6;34f>{t:9k1<7=t=330>4>53482o7jn;<0;=?bf3ty9=:4?:3y>644=<o16><6516`8yv4713:1?v3=1382<7=::0i1hn5229;9`f=z{;;26=49{<025?2a348:m7?8b:?15f<ci279=h4k9:?165<cj279>?4kc:p65>=839p1??>:0:1?84>j3nj70<78;fb?xu59k0;6?u220290c=::8i1=:l4}r033?6=;r79==4>839>6<d=lj16>565db9~w77c2909w0<?f;6e?846m3;<n6s|21494?5|5;:m6<6=;<0:e?bf3483;7jn;|q15c<72;q6>=k54g9>676=9>h0q~<?5;297~;58l0:4?5228c9`f=::1=1hn5rs302>5<5s48;h7:i;<017?70j2wx>=:50;1x976c282970<69;fb?84?>3nj7p}=2483>7}::9i18k52234952d<uz8;?7>53z?14f<60;16>475db9>6=0=lj1v<h>:18687e:3>m70?ia;3;6>;6j=0om63>b78g=>;6j10oo6s|1`;94?3|58h96<6=;<15=?b>349>?7j6;<174?b>348m97jn;|q2f6<72;q6=o?54g9>5g2=9>h0q~?n8;291~;6j80:4?5237;9`g=:;<91ho523529`g=::ol1hl5rs0`6>5<5s4;i<7:i;<3a2?70j2wx=l950;7x94d7282970=98;f:?852:3n270=<f;f:?84am3nj7p}>b683>3}:9hl18k521c:952d<58hj6io4=0``>a?<58hn6il4=0a3>ae<uz;j:7>55z?2ec<60;16?;65dc9>704=lk16?>h5dc9>6cb=lh1v<l6:18187fm3>m70?ma;34f>{t9h?1<7;t=0cf>4>5349=;7j6;<165?b>3498i7j6;<0eg?bf3ty:no4?:3y>5db=<o16=om516`8yv7f<3:19v3>ae82<7=:;?=1ho523439`g=:;:o1ho522g`9`d=z{8ho6=4={<3bg?2a34;ii7?8b:p5d5=83?p1<ol:0:1?851>3n270=:0;f:?854l3n270<ia;fb?xu6jo0;6?u21``90c=:9j;1=:l4}r3b6?6==r7:mo4>839>730=lk16?8>5dc9>76b=lk16>k75d`9~w4e42909w0?na;6e?87d<3;<n6s|1`394?3|58kj6<6=;<151?b>349?j7j6;<10g?b>348m47jn;|q101<72;q6>;>54g9>61c=9180q~<;3;296~;5=o0?j63=4e82<7=z{;?=6=4;{<06b?7?:279=;4k9:?15=<ci279=l4kb:p614=838p1?;j:5d8972d28297p}=5483>6}::<o1=5<4=33;>ad<5;;j6io4}r075?6=:r799i4;f:?10g<60;1v?;;:181842l3;3>63=1`8g=>{t:=:1<7<t=37`>1`<5;>j6<6=;|q116<72<q6>8m51908977d2m301??j:ec897472mi01?<=:e`8yv44n3:1>v3=5c87b>;5<00:4?5rs371>5<3s48>n7?72:?15`<cj279>=4k9:?167<ci2wx>>k50;0x973f2=l01?:7:0:1?xu5=80;6>u224c95=4<5;8;6io4=301>a?<uz88h7>52z?11<<3n2798:4>839~w7372908w0<:9;3;6>;5::0o563=278ge>{t::i1<7<t=37;>1`<5;>=6<6=;|q10c<72;q6>865190897412m30q~?kf;296~;6nh0?j63>e982<7=z{8nn6=4={<3e=?2a34;n;7?72:p5c6=83>p1<h6:0:1?87e<3n270?m6;fb?87e03ni7p}>de83>7}:9o218k521d495=4<uz;nj7>53z?2b=<60;16=o85dc9>5g>=lh1v<jl:18187a?3>m70?j5;3;6>{t9lo1<7<t=0d4>4>534;i47j6;|q2`g<72;q6=k854g9>5`2=9180q~?jd;291~;6n?0:4?521cc9`<=:9ki1hl521cg9`f=:9j:1ho5rs0fb>5<5s4;m97:i;<3f7?7?:2wx=hm50;6x94`2282970?mc;fa?87em3n270?l0;fb?xu6l00;6?u21g690c=:9l81=5<4}r3ff?6=;r7:j94>839>5gc=lh16=n>5d89~w4b?2909w0?i3;6e?87b93;3>6s|1dc94?5|58l86<6=;<3`5?b>34;h87jn;|q2`2<72;q6=k<54g9>5`6=9180q~?j9;296~;6n;0:4?521b69`<=z{;9;6=4={<07a?2a3488m7?72:p67`=838p1?:k:5d8975>28297p}=2d83>7}::=i18k5222:95=4<uz89h7>52z?10g<3n279?:4>839~w74d2909w0<;a;6e?844>3;3>6s|23`94?4|5;>269h4=316>4>53ty9>l4?:3y>61>=<o16>>:51908yv4513:1>v3=4687b>;5;:0:4?5rs30;>5<5s48?:7:i;<006?7?:2wx>?950;0x97222=l01?=>:0:1?xu5;k0;6<u225795=4<uz;hh7>52z?2a=<3n27:h;4>839~w4ed2909w0?j7;6e?87c=3;3>6s|1b`94?4|58o=69h4=0f7>4>53ty:ol4?:3y>5`3=<o16=i=51908yv7d13:1>v3>e587b>;6l;0:4?5rs0a;>5<5s4;n?7:i;<3g5?7?:2wx=n950;0x94c52=l01<j?:0:1?xu6k?0;6?u21d390c=:9jl1=5<4}r3`1?6=:r7:i=4;f:?2g`<60;1v?k?:18687c>3>m70<j9;3;6>;6190o563=8`8ge>;3=10?<6s|1g`94?4|58n>69h4=0;3>41e3ty:jn4?:3y>5a2=<o16=4?516`8yv7al3:1>v3>d287b>;61;0:;o5rs0df>5<5s4;o>7:i;<3:7?70j2wx=kh50;0x94b62=l01<7;:05a?xu5890;6?u21e290c=:90?1=:l4}r035?6=:r7:ok4;f:?2=3<6?k1v?>=:18187dm3>m70?67;34f>{t;l:1<7:t=31b>1`<5:oj6<6=;<3:<?b>34>>47=9;|q124<72;q6>>754g9>5<>=9>h0q~<92;296~;5;10?j63>98823g=z{;<86=4={<003?2a34;2m7?8b:p632=838p1?=9:5d894?e28=i7p}=6483>7}:::?18k5218a952d<uz8=:7>52z?171<3n27:5i4>7c9~w7002909w0<<3;6e?87>m3;<n6s|27:94?4|5;9969h4=0;e>41e3ty9:44?:3y>667=<o16=l>516`8yv4bi3:1=8u22e5903=::m<18;522e7903=::m>18;522e1903=::m818;522e2903=::jl18;522e3903=::l318;522d:903=::l=18;522d4903=::l?18;522d6903=::l918;522d0903=::l;18;5244c9`g=::?k1=:l4=3c1>ag<uz8jn7>52z?1`2<3n279o94>7c9~w7eb290?w0<k7;3;6>;5m00?j63=9e8ge>;5k<0o56s|2`c94?4|5;n=69h4=3a0>41e3ty9oi4?:5y>6a0=91801?k7:5d897?d2m301?lm:e;8yv4f13:1>v3=d487b>;5k;0:;o5rs3a`>5<3s48o97?72:?1a2<3n2795n4kb:?1f<<c12wx>l650;0x97b32=l01?m>:05a?xu5kk0;69u22e695=4<5;o=69h4=3;a>a?<5;h<6i74}r0b3?6=:r79h>4;f:?1g5<6?k1v?mn:18784c;3;3>63=e487b>;51k0on63=b48g=>{t:h<1<7<t=3f1>1`<5;hm6<9m;|q1g<<72=q6>i<5190897c32=l01?7n:e;897d42m30q~<n4;296~;5l90?j63=be823g=z{;i<6=4;{<0g4?7?:279i?4;f:?1=<<c1279mk4k9:p6d5=838p1?mi:5d897dd28=i7p}=c783>1}::jl1=5<4=3g2>1`<5;326il4=3cg>a?<uz8j97>52z?1`4<3n279nh4>7c9~w7e?290?w0<k1;3;6>;5m:0?j63=9`8gf>;5j80o56s|2cc94?4|5;i?6964=3`b>41e3ty9o84?:3y>6f2=9;301?m::05a?xu5j10;6>u22b190==::kk185522c:952d<uz8in7>53z?1g6<6:016>oo519:897de28=i7p}=b783>6}::j8185522c:90==::k<1=:l4}r0a=?6=;r79o?4>289>6g>=91201?l6:05a?xu5j=0;6>u22b390==::k<185522c6952d<uz8i;7>53z?1g4<6:016>o8519:897d028=i7p}=b383>6}::j:185522c690==::k81=:l4}r0a1?6=;r79o=4>289>6g2=91201?l::05a?xu5j90;6>u22cd90==::k8185522c2952d<uz8i?7>53z?1fc<6:016>o<519:897d428=i7p}=ad83>6}::ko185522c290==::ho1=:l4}r0a5?6=;r79nh4>289>6g6=91201?l>:05a?xu5ij0;6>u22cf90==::ho185522`a952d<uz8jj7>53z?1fa<6:016>lk519:897ga28=i7p}=ae83>6}::ki1=?74=3c`>4>?348jh7?8b:p6a`=83?p1?k7:0:1?87>93n270?60;fb?84?13n270::8;1f?xu5ll0;68u22d595=4<58396i74=0;2>ag<5;226il4=57;>6b<uz8oh7>55z?1a3<60;16=4=5d89>5<4=lh16>565d89>00>=;j1v?jl:18684b=3;3>63>958g=>;61:0om63=898gf>;3=108n6s|2e`94?3|5;o?6<6=;<3:1?b>34;287jn;<0;3?b>34>>47=n;|q1`d<72<q6>h=5190894?12m301<7::ec897>02mh019;7:2;8yv4c13:19v3=e382<7=:90=1h4521849`d=::1<1h45244:97==z{;n36=4;{<0f5?7?:27:5:4ka:?1<3<cj27?954<7:p620=839p1?9;:5d897122=l01?98:05a?xu5?=0;6?u226695=4<5;=<6i74}r044?6=:r79:k4;f:?134<6?k1v?8k:185841n3;3>63=728gf>;5?80on63=768gf>;5>k0o563=6`8gg>{t:>81<7<t=34f>1`<5;=86<9m;|q12f<72?q6>;k5190897142m301?9>:ec897102mk01?8m:ec8970f2mh0q~<i4;296~;4890?463=f5823g=z{;l>6=4={<134?751279j84>7c9~w67b2909w0=?0;34f>;49<0?j6s|2g194?5|5::26964=3d7>1><5;l86<9m;|q1bc<72:q6?=7513;897`3282370<if;34f>{t;;=1<7<t=22:>41e349:h7:i;|q0gg<72<q6>k:5509>7a3=91801>k6:5d896272mi01?hi:e;8yv4a:3:1?v3<0987<>;5n:0?463=f3823g=z{;ln6=4<{<13<?751279j>4>899>6cc=9>h0q~==6;296~;4810:;o5230a90c=z{:ij6=4:{<0e7?36349o87?72:?0a=<3n278?k4ka:?1b`<c12wx>k?50;1x96602=201?h=:5:897`628=i7p}=fe83>6}:;9=1=?74=3d1>4>?348mh7?8b:p773=838p1>>8:05a?856j3>m7p}<c883>0}::o819<523e195=4<5:o<69h4=21e>ae<5;lo6i74}r0e4?6=;r78<;4;8:?1b4<30279j=4>7c9~w7`d2908w0=?6;31=>;5n80:45522ga952d<uz9987>52z?043<6?k16?<o54g9~w6e?290>w0<i1;72?85c:3;3>63<e787b>;4;l0om63=fb8g=>{t:ll1<7=t=226>1><5;l;6964=3ge>41e3ty9jo4?:2y>753=9;301?h?:0:;?84aj3;<n6s|33194?4|5::>6<9m;<12=?2a3ty8o:4?:4y>6c6==816?i?5190896c22=l01>=j:ea897`e2m30q~<je;297~;48=0?463=eg87<>;5ml0:;o5rs3db>5<4s49;87?=9:?1ac<60116>ko516`8yv55:3:1>v3<05823g=:;8218k5rs2a5>5<2s48nj7;>;<1g4?7?:278i94;f:?07a<ci279jl4k9:p6`b=839p1>><:5:897cb2=201?kk:05a?xu5n00;6>u2311957?<5;on6<67;<0e=?70j2wx???50;0x966428=i70=>7;6e?xu4k<0;68u22dg914=:;jl1=5<4=2g0>1`<5:9o6im4=3d:>a?<uz8no7>53z?047<30279ii4;8:?1af<6?k1v?h7:180857:3;9563=ee82<==::o21=:l4}r114?6=:r78<?4>7c9>740=<o1v>m;:18684bl3?:70=le;3;6>;4m;0?j63<3b8ge>;5n10o56s|2d`94?5|5:::6964=3g`>1><5;oi6<9m;|q1b3<72:q6?=?513;897cd282370<i7;34f>{t;8l1<7<t=222>41e349:87:i;|q037<72;kp1?km:43896de2=<01>l6:54896df2=<01>ll:54896dc2=<01>m?:54896db2=<01>li:54896e62=<01>m=:54896ea2=<01>mk:54896eb2=<01>j?:54896b62=<01>j;:54896b52=<01>j<:54896b22=<01>j9:54896gc2=<01>ol:54896gb2=<01>on:54896g>2=<01>om:54896g02=<01>o9:54896g?2=<01>o::54896cf2=<01>k6:54896c?2=<01>k8:54896c12=<01>k::54896c32=<01>k<:54896c52=<01>k>:548961428=i7p}<0`83>7}:;8?1=5<4=20b>ae<uz9:?7>52z?05a<60;16??o5dc9~w6752909w0=>c;3;6>;4:h0om6s|30394?4|5:;i6<6=;<11e?b>3ty8==4?:3y>74g=91801><m:ec8yv57n3:1>v3<1882<7=:;;h1h45rs22f>5<5s49:47?72:?06f<ck2wx?=j50;0x9670282970==c;fa?xu48j0;6?u230495=4<5:8h6io4}r13f?6=:r78=94>839>77e=l01v><k:18085503>=70=9a;65?851l3;<n6s|33;94?4|5:8369h4=20a>41e3ty94h4?:3y>6<5=<116>4<516`8yv4>03:1>v3=9282<==::0n1=:l4}r0:b?6=:r795>4>7c9>6d4=l01v?6k:18184>:3>370<61;34f>{t:0=1<7<t=3;1>4>?3482o7?8b:p6=e=838p1?7>:5:897?728=i7p}=9783>7}::0;1=564=3;a>41e3ty94o4?:3y>6<6=<116>5h516`8yv4>=3:1>v3=9182<==::0k1=:l4}r0:0?6=:r794k4>899>6<?=9>h0q~<8b;296~;5090?463=7g823g=z{;2>6=4={<0;4?7?02794l4>7c9~w7?b2909w0<70;34f>;5i;0on6s|26c94?4|5;=m6964=35f>41e3ty9494?:3y>62`=91201?66:05a?xu5?00;6?u226g90==::>n1=:l4}r0;7?6=:r79;h4>899>6=>=9>h0q~<88;296~;5?m0?463=7b823g=z{;296=4={<04`?7?02794:4>7c9~w7>62909w0<8c;3;<>;50?0:;o5rs2;g>5<3s49in7:i;<1b3?7?:278:;4kc:?0<6<c12wx?o?50;1x96de282970=lf;6e?85283nh7p}<9c83>1}:;k318k523`795=4<5:<>6il4=25e>a?<uz9jj7>53z?0f<<60;16?nj54g9>71`=lk1v>7l:18785ei3>m70=n6;3;6>;4><0om63<808g=>{t;k:1<7=t=2`b>4>5349hi7:i;<17b?bf3ty85h4?:5y>7ge=<o16?l65190896012mk01>6::e;8yv5e:3:1?v3<bb82<7=:;m:18k523429`d=z{:3m6=4;{<1a`?2a349j57?72:?022<ck2784:4k9:p7g5=839p1>lk:0:1?85c93>m70=:1;f`?xu4i;0;69u23b290c=:;hi1=5<4=24;>ag<5:2o6i74}r1a2?6=;r78o=4>839>7a2=<o16?8<5d`9~w6g7290?w0=me;6e?85fi3;3>63<668ge>;4000o56s|3c694?5|5:hn6<6=;<1g6?2a349>=7jn;|q0e4<72=q6?oh54g9>7dd=91801>87:ea896>e2m30q~=m5;297~;4jo0:4?523e190c=:;<81hn5rs2c0>5<3s49h=7:i;<1b`?7?:278:44kc:?0<c<c12wx?o950;1x96e6282970=k5;6e?852;3nh7p}<a583>1}:;j818k523`g95=4<5:<26io4=2;b>a?<uz9i47>53z?0g7<60;16?i854g9>705=lh1v>m<:18785dl3;3>63<e087b>;4;j0on63=f68g<>{t;ji1<7:t=2f5>4>5349nm7:i;<174?bf348m97j6;|q03f<72;q6?lj54g9>7<>=9>h0q~=8b;296~;4ij0?j63<96823g=z{:=o6=4={<1ba?2a349257?8b:p72?=838p1>on:5d896?228=i7p}<7983>7}:;h318k52386952d<uz9<m7>52z?0eg<3n2785;4>7c9~w6112909w0=n7;6e?85>:3;<n6s|36794?4|5:k=69h4=2;2>41e3ty8;:4?:3y>7d>=<o16?4=516`8yv50<3:1>v3<a487b>;4190:;o5rs2:f>5<5s49257:7;<1;a?70j2wx?4o50;0x96?>288270=6a;34f>{t;1i1<7=t=2;;>1><5:2n6964=2:`>41e3ty84k4?:2y>7<>=9;301>6j:0:;?85?n3;<n6s|39c94?5|5:3<6964=2:`>1><5:2j6<9m;|q0<a<72:q6?49513;896>d282370=7d;34f>{t;121<7=t=2;5>1><5:2j6964=2:;>41e3ty84o4?:2y>7<0=9;301>6n:0:;?85?j3;<n6s|39494?5|5:3>6964=2:;>1><5:2=6<9m;|q0<<<72:q6?4;513;896>?282370=79;34f>{t;1>1<7=t=2;7>1><5:2=6964=2:7>41e3ty84:4?:2y>7<2=9;301>69:0:;?85??3;<n6s|39094?5|5:386964=2:7>1><5:296<9m;|q0<0<72:q6?4=513;896>3282370=75;34f>{t;1:1<7=t=2;1>1><5:296964=2:3>41e3ty84>4?:2y>7<4=9;301>6=:0:;?85?;3;<n6s|36g94?5|5:3:6964=2:3>1><5:=n6<9m;|q0<4<72:q6?4?513;896>7282370=71;34f>{t;>l1<7=t=2;3>44>349<i7?78:?03c<6?k1v>ji:18785b13;3>63>988g=>;6110om63;59800>{t;mo1<7:t=2g;>4>534;2m7j6;<3:=?bf34>>47=<;|q0`a<72=q6?h95190894?e2m301<7n:ec8913?2:80q~=kc;290~;4m?0:4?5218a9`<=:90h1hl5244:974=z{:ni6=4;{<1f1?7?:27:5i4k9:?2=f<ci27?954<0:p7ag=83>p1>k;:0:1?87>m3n270?6d;fb?822038m7p}<d883>1}:;l91=5<4=0;e>a?<583n6io4=57;>7c<uz9o47>54z?0a7<60;16=l>5d89>5<`=lh1688652e9~w6b02908w0=j1;3;6>;6i90om63;5981g>{t;:=1<7<t=211>4>?3498o7?8b:p77c=838p1>==:05a?854;3>37p}<3983>7}:;:91=564=21g>41e3ty8>k4?:3y>765=9>h01>=;:5:8yv5413:1>v3<3582<==:;:o1=:l4}r104?6=:r78?94>7c9>763=<11v>=n:181854=3;3463<3g823g=z{:9:6=4={<101?70j278?;4;8:p76d=838p1>=9:0:;?85383;<n6s|34694?4|5:9=6<9m;<145?be3ty88l4?:3y>713=91201>:i:05a?xu4<80;6?u2357952d<5:>=6964}r17f?6=:r788;4>899>706=9>h0q~=;2;296~;4<?0:;o5235590==z{:>h6=4={<173?7?02789<4>7c9~w6242909w0=;7;34f>;4<10?46s|35f94?4|5:>36<67;<166?70j2wx?9:50;0x962?28=i70=;9;6;?xu4<l0;6?u235;95=><5:?86<9m;|q010<72:q6?97516`896162m301>8l:e`8yv5183:1>v3<5c82<==:;??1=:l4}r163?6=:r789o4>7c9>70e=<11v>8>:181852k3;3463<67823g=z{:?36=4={<16g?70j2789i4;8:p734=838p1>;k:0:;?851?3;<n6s|34;94?4|5:?o6<9m;<16a?2?3ty8:>4?:3y>70c=91201>87:05a?xu4=h0;6?u234g952d<5:?m6964}r150?6=:r789k4>899>73?=9>h0q~=:6;296~;4=o0:;o5237a9`<=z{:=;6=4<{<15a?2a349=j7:i;<145?70j2wx?;k50;6x960b282970=82;fb?850;3nj70=9d;f;?xu4>k0;6?u237c90c=:;?i1=:l4}r66f?6=:<q68?j5479>07e=<?168?l5479>07g=<?168?75479>07>=<?168?85479>073=<?168?:5479>075=<?168?<5479>077=<?168?>5479>04`=<?168<k5479>04b=<?168<l5479>04g=<?168<75479>04>=<?168<95479>040=<?168<;5479>042=<?168<=5479>044=<?168>=5479>064=<?168>?5479>066=<?168?h5479>07c=<?168?95479>04e=<?168<?5479>046=<?16>;l516`8yv2283:1>v3;2e87b>;3=10h;6s|45d94?4|5=8h69h4=57;>g1<uz>?i7>52z?76g<3n27?954m5:p01b=838p19<n:5d8913?2k90q~:;c;296~;3:00?j63;598a6>{t<=h1<7<t=50;>1`<5=?36o?4}r67=?6=:r7?>;4;f:?71=<e82wx89650;0x91422=l019;7:`d8yv23?3:1>v3;2587b>;3=10ji6s|45494?4|5=8869h4=57;>f3<uz>?97>52z?767<3n27?954nd:p012=838p19<>:5d8913?2hi0q~:;3;296~;3:90?j63;598bf>{t<=81<7<t=53e>1`<5=?36lo4}r675?6=:r7?=h4;f:?71=<f02wx89>50;0x917c2=l019;7:`58yv24m3:1>v3;1c87b>;3=10j:6s|42f94?4|5=;j69h4=57;>d3<uz>8o7>52z?75<<3n27?954l4:p06d=838p19?7:5d8913?2h>0q~:<a;296~;39>0?j63;598b7>{t<:31<7<t=535>1`<5=?36l<4}r60<?6=:r7?=84;f:?71=<f92wx8>950;0x91732=l019;7:`28yv24>3:1>v3;1287b>;3=102j6s|42794?4|5=;969h4=57;>gc<uz>>;7>52z?776<3n27?954md:p000=838p19==:5d8913?2j90q~::5;296~;3;80?j63;598ag>{t<<>1<7<t=513>1`<5=?36ol4}r667?6=:r7?>k4;f:?71=<ei2wx88<50;0x914b2=l019;7:c;8yv2293:1>v3;2687b>;3=10i46s|45c94?4|5=;h69h4=57;>g2<uz>8j7>52z?754<3n27?954n9:p062=838p19??:5d8913?20o0q~==a;296~;4:h0:;o5233`9`g=z{=?26=4={<66e?70j27?954l9:p7`d=83?p1>9>:ec8960d2mk01>9=:05a?82203><863;598`<>{t9?:1<7<t=300>ag<5;896<<n;|q22g<72;q6=n?5d`9>5f6=9;k0q~<=4;296~;5:?0on63=23823g=z{8i96=4={<3`0?be34;h<7?8b:p560=838p1><l:05a?855j3nh7ps|54d94?4|V<?m70:<:47e?!2083;=h6s|57594?4|V<<<70:<:444?!2083;=i6s|54394?4|V<?:70:<:472?!2083;=j6s|4c294?4|V=3n70:<:5;f?!2083;?>6s|4`g94?4|V=3o70:<:5;g?!2083;?h6s|4`f94?4|V=3h70:<:5;`?!2083;>;6s|4`a94?4|V=3i70:<:5;a?!2083;>56s|4``94?4|V=3j70:<:5;b?!2083;>m6s|4`c94?4|V=3270:<:5;:?!2083;>n6s|4`;94?4|V=3370:<:5;;?!2083;>h6s|4`:94?4|V=3<70:<:5;4?!2083;>i6s|4c;94?4|V=k=70:<:5c5?!2083;>j6s|4c:94?4|V=k>70:<:5c6?!2083;==6s|4c594?4|V=k?70:<:5c7?!2083;=>6s|4c494?4|V=k870:<:5c0?!2083;=?6s|4c794?4|V=k970:<:5c1?!2083;=86s|4c694?4|V=k:70:<:5c2?!2083;=96s|4c194?4|V=k;70:<:5c3?!2083;=:6s|4c094?4|V=3m70:<:5;e?!2083;=;6s|4c394?4|V=3=70:<:5;5?!2083;=46s|4`594?4|V=3>70:<:5;6?!2083;=56s|56194?4|V<=870:<:450?!2083;=m6s|54f94?4|V<?o70:<:47g?!2083;=o6s|4g`94?4|V=n<70:<:5f4?!2083;<<6s|4g;94?4|V=n=70:<:5f5?!2083;<=6s|4g:94?4|V=n>70:<:5f6?!2083;<>6s|4g594?4|V=n?70:<:5f7?!2083;<?6s|4g494?4|V=n870:<:5f0?!2083;<86s|4g794?4|V=n970:<:5f1?!2083;<96s|4g194?4|V=n;70:<:5f3?!2083;<:6s|4g094?4|V=im70:<:5ae?!2083;<;6s|4g394?4|V=in70:<:5af?!2083;<46s|4g294?4|V=io70:<:5ag?!2083;846s|4dd94?4|V=ih70:<:5a`?!2083;856s|4dg94?4|V=ii70:<:5aa?!2083;8m6s|4df94?4|V=ij70:<:5ab?!2083;8n6s|4da94?4|V=i270:<:5a:?!2083;8o6s|4d`94?4|V=i370:<:5a;?!2083;8h6s|4dc94?4|V=i<70:<:5a4?!2083;8i6s|4d:94?4|V=i>70:<:5a6?!2083;8j6s|4d594?4|V=i?70:<:5a7?!2083;?<6s|4d494?4|V=i870:<:5a0?!2083;?=6s|4d794?4|V=i970:<:5a1?!2083;??6s|4d694?4|V=i:70:<:5a2?!2083;?86s|4d194?4|V=i;70:<:5a3?!2083;?96s|4d094?4|V=hm70:<:5`e?!2083;?:6s|4d394?4|V=hn70:<:5`f?!2083;?;6s|4d294?4|V=ho70:<:5`g?!2083;?46s|4ed94?4|V=hh70:<:5``?!2083;?56s|51094?4|V=no70:<:5fg?!2083;?m6s|51394?4|V=nh70:<:5f`?!2083;?n6s|51294?4|V=ni70:<:5fa?!2083;?o6s|4gd94?4|V=nj70:<:5fb?!2083;?i6s|4gg94?4|V=n270:<:5f:?!2083;?j6s|4gf94?4|V=n370:<:5f;?!2083;><6s|4ga94?4|V=n:70:<:5f2?!2083;>=6s|4g694?4|V=i=70:<:5a5?!2083;>>6s|4d;94?4|V=hi70:<:5`a?!2083;>?6s|4eg94?4|V=hj70:<:5`b?!2083;>86s|51c94?4|V<:j70:<:42b?!2083;>96s|49794?4|V=2>70:<:5:6?!2083;>:6s|51694?4|V<:?70:<:427?!2083;>46s|53d94?4|V<8m70:<:40e?!2083;>o6srn`f:>5<5sA><=6saaec94?4|@==:7p`ndc83>7}O<>;0qcokc;296~N3?81vbljk:181M2092wemik50;0xL1163tdjhk4?:3yK027<ugkn<7>52zJ734=zfho:6=4={I645>{iil81<7<tH552?xhfm:0;6?uG4638ykgb<3:1>vF;709~jdc22909wE:81:me`0=838pD99>;|lba2<72;qC8:?4}ocf<?6=:rB?;<5rn`g:>5<5sA><=6saadc94?4|@==:7p`nec83>7}O<>;0qcojc;296~N3?81vblkk:181M2092wemhk50;0xL1163tdjik4?:3yK027<ugkm<7>52zJ734=zfhl:6=4={I645>{iio81<7<tH552?xhfn:0;6?uG4638ykga<3:1>vF;709~jd`22909wE:81:mec0=838pD99>;|lbb2<72;qC8:?4}oce<?6=:rB?;<5rn`d:>5<5sA><=6saagc94?4|@==:7p`nfc83>7}O<>;0qcoic;296~N3?81vblhk:181M2092wemkk50;0xL1163tdjjk4?:3yK027<ugh;<7>52zJ734=zfk::6=4={I645>{ij981<7<tH552?xhe8:0;6?uG4638ykd7<3:1>vF;709~jg622909wE:81:mf50=838pD99>;|la42<72;qC8:?4}o`3<?6=:rB?;<5rnc2:>5<5sA><=6sab1c94?4|@==:7p`m0c83>7}O<>;0qcl?c;296~N3?81vbo>k:181M2092wen=k50;0xL1163tdi<k4?:3yK027<ugh:<7>52zJ734=zfk;:6=4={I645>{ij881<7<tH552?xhe9:0;6?uG4638ykd6<3:1>vF;709~jg722909wE:81:mf40=838pD99>;|la52<72;qC8:?4}o;2e?6=9rB?;<5rn87:>5<6sA><=6sa94c94?7|@==:7p`65c83>4}O<>;0qc7:c;295~N3?81vb4;k:182M2092we58k50;3xL1163td29k4?:0yK027<ug3=<7>51zJ734=zf0<:6=4>{I645>{i1?81<7?tH552?xh>>:0;6<uG4638yk?1<3:1=vF;709~j<02290:wE:81:m=30=83;pD99>;|l:22<728qC8:?4}o;5<?6=9rB?;<5rn84:>5<6sA><=6sa97c94?7|@==:7p`66c83>4}O<>;0qc79c;295~N3?81vb48k:182M2092we5;k50;3xL1163td2:k4?:0yK027<ug3<<7>51zJ734=zf0=:6=4>{I645>{i1>81<7?tH552?xh>?:0;6<uG4638yk?0<3:1=vF;709~j<12290:wE:81:m=20=83;pD99>;|l:32<728qC8:?4}o;4<?6=9rB?;<5rn85:>5<6sA><=6sa96c94?7|@==:7p`67c83>4}O<>;0qc78c;295~N3?81vb49k:182M2092we5:k50;3xL1163td2;k4?:0yK027<ug33<7>51zJ734=zf02:6=4>{I645>{i1181<7?tH552?xh>0:0;6<uG4638yk??<3:1=vF;709~j<>2290:wE:81:m==0=83;pD99>;|l:<2<728qC8:?4}o;;<?6=9rB?;<5rn8::>5<6sA><=6sa99c94?7|@==:7p`68c83>4}O<>;0qc77c;295~N3?81vb46k:182M2092we55k50;3xL1163td24k4?:0yK027<ug32<7>51zJ734=zf03:6=4>{I645>{i1081<7?tH552?xh>1:0;6<uG4638yk?><3:1=vF;709~j<?2290:wE:81:m=<0=83;pD99>;|l:=2<728qC8:?4}o;:<?6=9rB?;<5rn8;:>5<6sA><=6sa98c94?7|@==:7p`69c83>4}O<>;0qc76c;295~N3?81vb47k:182M2092we54k50;3xL1163td25k4?:0yK027<ug3j<7>51zJ734=zf0k:6=4>{I645>{i1h81<7?tH552?xh>i:0;6<uG4638yk?f<3:1=vF;709~j<g2290:wE:81:m=d0=83;pD99>;|l:e2<728qC8:?4}o;b<?6=9rB?;<5rn8c:>5<6sA><=6sa9`c94?7|@==:7p`6ac83>4}O<>;0qc7nc;295~N3?81vb4ok:182M2092we5lk50;3xL1163td2mk4?:0yK027<ug3i<7>51zJ734=zf0h:6=4>{I645>{i1k81<7?tH552?xh>j:0;6<uG4638yk?e<3:1=vF;709~j<d2290:wE:81:m=g0=83;pD99>;|l:f2<728qC8:?4}o;a<?6=9rB?;<5rn8`:>5<6sA><=6sa9cc94?7|@==:7p`6bc83>4}O<>;0qc7mc;295~N3?81vb4lk:182M2092we5ok50;3xL1163td2nk4?:0yK027<ug3h<7>51zJ734=zf0i:6=4>{I645>{i1j81<7?tH552?xh>k:0;6<uG4638yk?d<3:1=vF;709~j<e2290:wE:81:m=f0=83;pD99>;|l:g2<728qC8:?4}o;`<?6=9rB?;<5rn8a:>5<6sA><=6sa9bc94?7|@==:7p`6cc83>4}O<>;0qc7lc;295~N3?81vb4mk:182M2092we5nk50;3xL1163td2ok4?:0yK027<ug3o<7>51zJ734=zf0n:6=4>{I645>{i1m81<7?tH552?xh>l:0;6<uG4638yk?c<3:1=vF;709~j<b2290:wE:81:m=a0=83;pD99>;|l:`2<728qC8:?4}o;g<?6=9rB?;<5rn8f:>5<6sA><=6sa9ec94?7|@==:7p`6dc83>4}O<>;0qc7kc;295~N3?81vb4jk:182M2092we5ik50;3xL1163td2hk4?:0yK027<ug3n<7>51zJ734=zf0o:6=4>{I645>{i1l81<7?tH552?xh>m:0;6<uG4638yk?b<3:1=vF;709~j<c2290:wE:81:m=`0=83;pD99>;|l:a2<728qC8:?4}o;f<?6=9rB?;<5rn8g:>5<6sA><=6sa9dc94?7|@==:7p`6ec83>4}O<>;0qc7jc;295~N3?81vb4kk:182M2092we5hk50;3xL1163td2ik4?:0yK027<ug3m<7>51zJ734=zf0l:6=4>{I645>{i1o81<7?tH552?xh>n:0;6<uG4638yk?a<3:1=vF;709~j<`2290:wE:81:m=c0=83;pD99>;|l:b2<728qC8:?4}o;e<?6=9rB?;<5rn8d:>5<6sA><=6sa9gc94?7|@==:7p`6fc83>4}O<>;0qc7ic;295~N3?81vb4hk:182M2092we5kk50;3xL1163td2jk4?:0yK027<ugk;<7>51zJ734=zfh::6=4>{I645>{ii981<7?tH552?xhf8:0;6<uG4638ykg7<3:1=vF;709~jd62290:wE:81:me50=83;pD99>;|lb42<728qC8:?4}oc3<?6=9rB?;<5rn`2:>5<6sA><=6saa1c94?7|@==:7p`n0c83>4}O<>;0qco?c;295~N3?81vbl>k:182M2092wem=k50;3xL1163tdj<k4?:0yK027<ugk:<7>51zJ734=zfh;:6=4>{I645>{ii881<7?tH552?xhf9:0;6<uG4638ykg6<3:1=vF;709~jd72290:wE:81:me40=83;pD99>;|lb52<728qC8:?4}oc2<?6=9rB?;<5rn`3:>5<6sA><=6saa0c94?7|@==:7p`n1c83>4}O<>;0qco>c;295~N3?81vbl?k:182M2092wem<k50;3xL1163tdj=k4?:0yK027<ugk9<7>51zJ734=zfh8:6=4>{I645>{ii;81<7?tH552?xhf::0;6<uG4638ykg5<3:1=vF;709~jd42290:wE:81:me70=83;pD99>;|lb62<728qC8:?4}oc1<?6=9rB?;<5rn`0:>5<6sA><=6saa3c94?7|@==:7p`n2c83>4}O<>;0qco=c;295~N3?81vbl<k:182M2092wem?k50;3xL1163tdj>k4?:0yK027<ugk8<7>51zJ734=zfh9:6=4>{I645>{ii:81<7?tH552?xhf;:0;6<uG4638ykg4<3:1=vF;709~jd52290:wE:81:me60=83;pD99>;|lb72<728qC8:?4}oc0<?6=9rB?;<5rn`1:>5<6sA><=6saa2c94?7|@==:7p`n3c83>4}O<>;0qco<c;295~N3?81vbl=k:182M2092wem>k50;3xL1163tdj?k4?:0yK027<ugk?<7>51zJ734=zfh>:6=4>{I645>{ii=81<7?tH552?xhf<:0;6<uG4638ykg3<3:1=vF;709~jd22290:wE:81:me10=83;pD99>;|lb02<728qC8:?4}oc7<?6=9rB?;<5rn`6:>5<6sA><=6saa5c94?7|@==:7p`n4c83>4}O<>;0qco;c;295~N3?81vbl:k:182M2092wem9k50;3xL1163tdj8k4?:0yK027<ugk><7>51zJ734=zfh?:6=4>{I645>{ii<81<7?tH552?xhf=:0;6<uG4638ykg2<3:1=vF;709~jd32290:wE:81:me00=83;pD99>;|lb12<728qC8:?4}oc6<?6=9rB?;<5rn`7:>5<6sA><=6saa4c94?7|@==:7p`n5c83>4}O<>;0qco:c;295~N3?81vbl;k:182M2092wem8k50;3xL1163tdj9k4?:0yK027<ugk=<7>51zJ734=zfh<:6=4>{I645>{ii?81<7?tH552?xhf>:0;6<uG4638ykg1<3:1=vF;709~jd02290:wE:81:me30=83;pD99>;|lb22<728qC8:?4}oc5<?6=9rB?;<5rn`4:>5<6sA><=6saa7c94?7|@==:7p`n6c83>4}O<>;0qco9c;295~N3?81vbl8k:182M2092wem;k50;3xL1163tdj:k4?:0yK027<ugk<<7>51zJ734=zfh=:6=4>{I645>{ii>81<7?tH552?xhf?:0;6<uG4638ykg0<3:1=vF;709~jd12290:wE:81:me20=83;pD99>;|lb32<728qC8:?4}oc4<?6=9rB?;<5rn`5:>5<6sA><=6saa6c94?7|@==:7p`n7c83>4}O<>;0qco8c;295~N3?81vbl9k:182M2092wem:k50;3xL1163tdj;k4?:0yK027<ugk3<7>51zJ734=zfh2:6=4>{I645>{ii181<7?tH552?xhf0:0;6<uG4638ykg?<3:1=vF;709~jd>2290:wE:81:me=0=83;pD99>;|lb<2<728qC8:?4}oc;<?6=9rB?;<5rn`::>5<6sA><=6saa9c94?7|@==:7p`n8c83>4}O<>;0qco7c;295~N3?81vbl6k:182M2092wem5k50;3xL1163tdj4k4?:0yK027<ugk2<7>51zJ734=zfh3:6=4>{I645>{ii081<7?tH552?xhf1:0;6<uG4638ykg><3:1=vF;709~jd?2290:wE:81:me<0=83;pD99>;|lb=2<728qC8:?4}oc:<?6=9rB?;<5rn`;:>5<6sA><=6saa8c94?7|@==:7p`n9c83>4}O<>;0qco6c;295~N3?81vbl7k:182M2092wem4k50;3xL1163tdj5k4?:0yK027<ugkj<7>51zJ734=zfhk:6=4>{I645>{iih81<7?tH552?xhfi:0;6<uG4638ykgf<3:1=vF;709~jdg2290:wE:81:med0=83;pD99>;|lbe2<728qC8:?4}ocb<?6=9rB?;<5rn`c:>5<6sA><=6saa`c94?7|@==:7p`nac83>4}O<>;0qconc;295~N3?81vblok:182M2092wemlk50;3xL1163tdjmk4?:0yK027<ugki<7>51zJ734=zfhh:6=4>{I645>{iik81<7?tH552?xhfj:0;6<uG4638ykge<3:1=vF;709~jdd2290:wE:81:meg0=83;pD99>;|lbf2<728qC8:?4}oca<?6=9rB?;<5rn``:>5<6sA><=6saacc94?7|@==:7p`nbc83>4}O<>;0qcomc;295~N3?81vbllk:182M2092wemok50;3xL1163tdjnk4?:0yK027<ugkh<7>51zJ734=zfhi:6=4>{I645>{iij81<7?tH552?xhfk:0;6<uG4638ykgd<3:1=vF;709~jde2290:wE:81:mef0=83;pD99>;|lbg2<728qC8:?4}oc`<?6=9rB?;<5rn`a:>5<6sA><=6saabc94?7|@==:7p`ncc83>4}O<>;0qcolc;295~N3?81vblmk:182M2092wemnk50;3xL1163tdjok4?:0yK027<ugko<7>51zJ734=zfhn:6=4>{I645>{iim81<7?tH552?xhfl:0;6<uG4638ykgc<3:1=vF;709~jdb2290:wE:81:mea0=83;pD99>;|lb`2<728qC8:?4}ocg<?6=9rB?;<5r}|CDF}dl10<jh:ke93~DED|8tJK\vsO@
\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v new file mode 100644 index 000000000..25ac9779e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating +// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_18to36( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + almost_full, + empty, + prog_full); + + +input rst; +input wr_clk; +input rd_clk; +input [17 : 0] din; +input wr_en; +input rd_en; +output [35 : 0] dout; +output full; +output almost_full; +output empty; +output prog_full; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(10), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(18), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(0), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(1), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("1kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(1015), + .C_PROG_FULL_THRESH_NEGATE_VAL(1014), + .C_PROG_FULL_TYPE(1), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(1024), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(10), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .ALMOST_FULL(almost_full), + .EMPTY(empty), + .PROG_FULL(prog_full), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .RD_DATA_COUNT(), + .WR_DATA_COUNT(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo new file mode 100644 index 000000000..db2795098 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_18to36 YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [17 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .almost_full(almost_full), + .empty(empty), + .prog_full(prog_full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating +// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco new file mode 100644 index 000000000..f888ba5f4 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Wed Aug 18 17:27:35 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=true +CSET component_name=fifo_xlnx_512x36_2clk_18to36 +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=1015 +CSET full_threshold_negate_value=1014 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=18 +CSET input_depth=1024 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=10 +# END Parameters +GENERATE +# CRC: 77234081 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise new file mode 100644 index 000000000..04acaf578 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise @@ -0,0 +1,72 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="fifo_xlnx_512x36_2clk_18to36.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation"/> + <association xil_pn:name="Implementation"/> + </file> + <file xil_pn:name="fifo_xlnx_512x36_2clk_18to36.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation"/> + <association xil_pn:name="Implementation"/> + <association xil_pn:name="PostMapSimulation"/> + <association xil_pn:name="PostRouteSimulation"/> + <association xil_pn:name="PostTranslateSimulation"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_18to36.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-08-18T10:27:37" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="224FA43C81F32871F9E1930EA6CDD6AD" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt new file mode 100644 index 000000000..2f8d522f6 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt @@ -0,0 +1,12 @@ +# Output products list for <fifo_xlnx_512x36_2clk_18to36> +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_18to36.gise +fifo_xlnx_512x36_2clk_18to36.ngc +fifo_xlnx_512x36_2clk_18to36.v +fifo_xlnx_512x36_2clk_18to36.veo +fifo_xlnx_512x36_2clk_18to36.xco +fifo_xlnx_512x36_2clk_18to36.xise +fifo_xlnx_512x36_2clk_18to36_flist.txt +fifo_xlnx_512x36_2clk_18to36_readme.txt +fifo_xlnx_512x36_2clk_18to36_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt new file mode 100644 index 000000000..03829e876 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt @@ -0,0 +1,47 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_18to36.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_18to36.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_18to36.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_18to36.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_18to36.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_18to36.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_18to36_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_18to36_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_512x36_2clk_18to36_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl new file mode 100644 index 000000000..9b9b1f37a --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_xlnx_512x36_2clk_18to36_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_xlnx_512x36_2clk_18to36_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_18to36 +} +# ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_18to36 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise new file mode 100644 index 000000000..d0c862319 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_36to18.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_36to18.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc new file mode 100644 index 000000000..00814f02e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$5a540<,[o}e~g`n;"2*726&;$:,)<6;.vnt*Ydo&lbjbQwloz\144;?U9oaeP37vl5=(iof;0<85?0123=>6789:;<=>;0:23456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?013856=6&9;87<>5IORVP?GCL[K757>11g924?OIX\^1|ah_dosp|Ys`{oxd1750?05?46=AGZ^X7~}of]fiur~W}byi~fParqfvq:>2949:6??:HLSQQ<wzfmTi`~{y^vkv`uoWgolmyk39;2=5f=683E^X][[:sf\`drfWje~by26:1<26>712@D[YY4KI@>21?699:1::7AZTQWW>AIF48?1<3?;;0:9KPRW]]0ocxz31683:4=5:28:86<<3232?7<NFY__6IG_A=394;753;0DYY^ZT;FLTD:6294:>6==:HLSQQ<CAK68=7>112906?IR\Y__6IAM<2394;753:<1EC^ZT;fjj952294o7>}=012ec131%<;0895;0GD25>2=AGZ^X7JFPC>0>586:2>1CXZ_UU8GKUD;;3:5=68=;7;7?3?>>=138??;;9G;E4=><23;<4<49768=30>9;126D@_UU8B@ATE410;2<j49;KMTPR=x{elSk{cl^vkv`uo410;2?:49;KMTPR=x{elSk{cl^vkv`uoWhyxiz38;2=61=>2@D[YY4rne\bpjkW}byi~fPndebp`:?294:4675OTVSQQ<ci}kTob{at=:94;7e300DYY^ZT;uq[agsiVidycz38;2=6>G502KOH_O30?:8EABUI5;546OKDSC?6;><IMNYM1=18:CG@WG;<720MIJ]A=7=<>GCL[K7:364AEFQE91902KOH_O38?c8EABUI531<364AEFQE9?902KOH_L30?:8EABUJ5;546OKDS@?6;><IMNYN1=18:CG@WD;<720MIJ]B=7=<>GCL[H7:364AEFQF919i2KOH_L38;2=<>GCL[H743=4AMN:?DU^FJUYIJ=4BT0;?GSTW@DMC<5L2:AF57=D@LI@SAGLEOQF[Q_WM;1HE95LLJC7?FJLJ:1H@_74CNONMQRBL8>0OB\J_FGMAWGSAFDTECH@7:AQADRBL81O>6JL2:FJ2>BNI5:5;6JFA=33:2=CAH6:=394DHC?57803MCJ0<=17:FJE973601OEL2>5;2=3>BNI5;>2;5KI@>2:3=CAH692;5KI@>0:3=CAH6?2;5KI@>6:3=CAH6=2;5KI@>4:3=CAH632;5KI@>::3=CAK6;2:5KIC>24;1<L@H7=<08;EKA8449?2NBN1?<>69GMG:6<7=0HDL314<4?AOE48<5;6JFB=34:2=CAK6:4394DH@?5<813MCI0<08;EKA8769?2NBN1<>>69GMG:5:7=0HDL322<4?AOE4;>5;6JFB=06:2=CAK69:394DH@?62803MCI0?617:FJF94>6?1OEO2=>69GMG:48730HDL33083:2=CAK68=384DH@?7;0<L@H78384DH@?1;0<L@H7:384DH@?3;0<L@H74384DH@?=;1<L@ZJ0=06;EKSE97=87=0HD^N<0<4?AOWJ5:5;6JFPC>2:2=CAYH7>374DHRA86<76>1OE]L33?48@JG;87=0HBO311<4?AIF48;5;6J@A=31:2=CGH6:?394DNC?518>3MEJ0<;50?58@JG;9<4=7IAN<0<5?AIF4;4=7IAN<2<5?AIF4=4=7IAN<4<5?AIF4?4=7IAN<6<5?AIF414=7IAN<8<4?AIFW[OL:6J@B=2=3>BHJ5;;2:5KOC>25;1<LFH7=?08;EMA8459?2NDN1?;>69GKG:6=7=0HBL317<4?AIE48=5;6J@B=3;:2=CGK6:5384DN@?5;1<LFH7>=08;EMA8779?2NDN1<=>69GKG:5;7=0HBL325<4?AIE4;?5;6J@B=05:2=CGK69;394DN@?6=803MEI0?716:FLF949?2NDN1=?>89GKG:493:5;6J@B=12:3=CGK682;5KOC>7:3=CGK6>2;5KOC>5:3=CGK6<2;5KOC>;:3=CGK622:5KOC]QAB1<LFZJ0=06;EMSE97=87=0HB^N<0<4?AIWJ5:5;6J@PC>2:2=CGYH7>374DNRA86<76>1OC]L33?18AKG43LDIn6KA_DA@[WCFLj1NBRKLC^UQMQC53O8?7K<I039E<0=AIEYN>6HK3:DGG1=ALJO87KJ_4:DGT@2<NMXN=6I<;FLG6>O7:2C:>6G=2:K0<>OIA]ZT<=64IOKWTZ6602CEEY^P03:8MKOSXV:846GAIUR\41><AGC_\R>:8:KMMQVX8?20ECG[P^24=>OIA]Y_MYK8;HLJPZ67?2CEEYQ?169JJLRX8;=0ECG[_114?LHN\V:?;6GAIU]312=NF@^T<;94IOKW[5103@DBXR>77:KMMQY71>1BBDZP0@58MKOSW9H<7D@FT^2@3>OIA]U;H:5FNHV\4@1<AGC_S=H8;HLJPZ77?2CEEYQ>169JJLRX9;=0ECG[_014?LHN\V;?;6GAIU]212=NF@^T=;94IOKW[4103@DBXR?77:KMMQY61>1BBDZP1@58MKOSW8H<7D@FT^3@3>OIA]U:H:5FNHV\5@1<AGC_S<H8;HLJPZ47?2CEEYQ=169JJLRX:;=0ECG[_314?LHN\V8?;6GAIU]112=NF@^T>;94IOKW[7103@DBXR<77:KMMQY51>1BBDZP2@58MKOSW;H<7D@FT^0@3>OIA]U9H:5FNHV\6@1<AGC_S?H8;HLJPZ57?2CEEYQ<169JJLRX;;=0ECG[_214?LHN\V9?;6GAIU]012=NF@^T?;94IOKW[6103@DBXR=77:KMMQY41>1BBDZP3@58MKOSW:H<7D@FT^1@3>OIA]U8H:5FNHV\7@1<AGC_S>H9;HLJPZG13@DBXRL=;MK1?II13EEJHHJ8;MMDMFGK<2F^X<:4LTV10>JR\:>0@XZ;6:NVP1YC=2GXKB@:;LW[G\e<Eh`d~[k}shmmg>Knffx]i}foo08J42<F8:2?6@>159M54633G;:=95A1007?K76;=1E=<:;;O3211=I98<?7C?>759M54>33G;:5>5A1368J447<2D:><:4N0010>H6::>0B<<;4:L2602<F88=86@>2618J4533G;8=>5A1518J4343G;=?6@>729M5=5<F8397C<<;O037>H59:1E>?=4N310?K43;2D99>5A2718J7143G83?6@=929M755<F:;87C==3:L076=I;=90B>;<;O157>H4?:1E?5=4N2;0?K27;2D?=>5A4318J1543G>??6@;529M035<F==87C:72:L66>H0:2D2j6@M_CWPTLHXX[E[_:5AEUULVN7<G;1DG<5_4:RBVQg<X@DTNX]FDY`8TLHXJ\YEM@K<;QPF5>W63[o0^LCM17]P5=YT;?k0^HOK_GKQWQe<ZLKOSZGKTI]Bg>TBIMU\EIZG_C38W45<[@GTOBBCIRKLJZEOMJA=7^AZRBG4?VTQIEUJ;6]]V@N\F1=T[[K?7^]]B59W]UC4:2_;#j|i.sd,cf~)keas#@v`r^pg[uhszVmhSua}0123[Wct}e~:??5Z0.eqb+ta'nis"nbdx.O{kwYulVzexQhc^zlv5679VXnxb{1208Q5)`zo$yj"ilx/aoo})JpfxT~iQnup\cfYg{:;<?Q]erwop4553\:$kh!rg-dg}(ddbr$Aua}_sf\tkruWniTtb|?011\V`urd};8>6[?/fpe*w`(ojr%oaew/LzlvZtcWyd~Ril_ymq4563W[oxyaz>339V4*aun'xm#jmw.bnh|*Kg{UyhR~ats]dgZ~hz9:;9R\jstnw564<]9%l~k }f.e`|+ekcq%Ftb|Pre]sjqtXojUsc>?07]Qavsk|8997X> gsd-vc)`kq$h`fv Mymq[wbXxg~ySjmPxnp3451XZly~`y?<2:W3+bta&{l$knv!cmi{+H~hzVxoS}`{r^e`[}iu89:3S_k|umv277=R8&myj#|i/fa{*fjlp&GscQxr^rmpwY`kVrd~=>?0^Pfwpjs9:80Y=!hrg,qb*adp'iggu!Bxnp\swYwf}xTknQwos2344YUmzgx<==;T2,cw`)zo%lou lljz,I}iuW~xT|cz}_fa\|jt7898T^h}zlu306>S7'nxm"h gbz-gim'Drd~Ry}_qlwvZadWqey<=><_Sgpqir6;;1^<"i}f/pe+be&jf`t"Cwos]tvZvi|{UloRv`r1230ZTb{|f=><4U1-dvc(un&mht#mcky-N|jtX{U{by|Pgb]{kw678<UYi~{ct011?P6(o{l%~k!hcy,`hn~(EqeySz|Ppovq[beXpfx;<=8PRdqvhq74:2_;#j|i.sd,cf~)keas#@v`r^uq[uhszVmhSua}0124[Wct}e~:><5Z0.eqb+ta'nis"nbdx.pg[uhszVhbb1?1209V4*aun'xm#jmw.bnh|*tcWyd~Rlfn=0=64=R8&myj#|i/fa{*fjlp&xoS}`{r^`jj959:81^<"i}f/pe+be&jf`t"|k_qlwvZdnf5>5><5Z0.eqb+ta'nis"nbdx.pg[uhszVhbb1;1209V4*aun'xm#jmw.bnh|*tcWyd~Rlfn=4=64=R8&myj#|i/fa{*fjlp&xoS}`{r^`jj919:81^<"i}f/pe+be&jf`t"|k_qlwvZdnf525><5Z0.eqb+ta'nis"nbdx.pg[uhszVhbb171219V4*aun'xm#jmw.bnh|*tcWyd~Rlfn^314>S7'nxm"h gbz-gim'{nT|cz}_ckm[7473\:$kh!rg-dg}(ddbr$~iQnup\flhX;;:0Y=!hrg,qb*adp'iggu!}d^rmpwYeagU?>=5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbR;=0:W3+bta&{l$knv!cmi{+wbXxg~ySoga_703?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\376<]9%l~k }f.e`|+ekcq%yhR~ats]amkY?:91^<"i}f/pe+be&jf`t"|k_qlwvZdnfV39:6[?/fpe*w`(ojr%oaew/sf\tkruWkceSua}012362=R8&myj#|i/fa{*fjlp&xoS}`{r^`jjZ~hz9:;<<<9;T2,cw`)zo%lou lljz,vaYwf}xTnd`Pxnp34575?2_;#j|i.sd,cf~)keas#jPpovq[goiWqey<=>>1348Q5)`zo$yj"ilx/aoo})ulVzexQmio]{kw678;8<7X> gsd-vc)`kq$h`fv re]sjqtXj`dTtb|?010263=R8&myj#|i/fa{*fjlp&xoS}`{r^`jjZ~hz9:;??94U1-dvc(un&mht#mcky-q`Zvi|{UiecQwos234645>2_;#j|i.sd,cf~)keas#jPpovq[goiWqey<=>;269V4*aun'xm#jmw.bnh|*tcWyd~Rlfn^zlv567<88=7X> gsd-vc)`kq$h`fv re]sjqtXj`dTtb|?01713>S7'nxm"h gbz-gim'{nT|cz}_ckm[}iu89:>=?84U1-dvc(un&mht#mcky-q`Zvi|{UiecQwos23434?3\:$kh!rg-dg}(ddbr$~iQnup\flhXpfx;<=8>1358Q5)`zo$yj"ilx/aoo})ulVzexQmio]{kw678?89n6[?/fpe*w`(ojr%oaew/sf\tkruWkceSua}0125[gbc8;<0Y=!hrg,qb*adp'iggu!}d^rmpwYeagUsc>?0604?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\|jt789=:>=5Z0.eqb+ta'nis"nbdx.pg[uhszVmh0=0=0:W3+bta&{l$knv!cmi{+wbXxg~ySjm31?03?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb>1:76<]9%l~k }f.e`|+ekcq%yhR~ats]dg959:91^<"i}f/pe+be&jf`t"|k_qlwvZad4=49<6[?/fpe*w`(ojr%oaew/sf\tkruWni793<?;T2,cw`)zo%lou lljz,vaYwf}xTkn29>328Q5)`zo$yj"ilx/aoo})ulVzexQhc=5=65=R8&myj#|i/fa{*fjlp&xoS}`{r^e`8=8582_;#j|i.sd,cf~)keas#jPpovq[be;17;m7X> gsd-vc)`kq$h`fv re]sjqtXojU;=k5Z0.eqb+ta'nis"nbdx.pg[uhszVmhS<?i;T2,cw`)zo%lou lljz,vaYwf}xTknQ=1g9V4*aun'xm#jmw.bnh|*tcWyd~Ril_23e?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb]75c=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[07a3\:$kh!rg-dg}(ddbr$~iQnup\cfY19o1^<"i}f/pe+be&jf`t"|k_qlwvZadW>;m7X> gsd-vc)`kq$h`fv re]sjqtXojU3=k5Z0.eqb+ta'nis"nbdx.pg[uhszVmhS4<9;T2,cw`)zo%lou lljz,vaYwf}xTknQnssgd8585>2_;#j|i.sd,cf~)keas#jPpovq[beXizxnk1?1279V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqab:56;<0Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hi33?05?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb]bwwc`4=49:6[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg=7=63=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumn6=2?84U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde?3;413\:$kh!rg-dg}(ddbr$~iQnup\cfYf{{ol050=6:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfc9?9:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ?249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY6:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ=249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY4:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ;249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY2:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ9249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY0:<1^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQ7249V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabY>:01^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQk1=3=6<=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=1<1289V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc9595>45Z0.eqb+ta'nis"nbdx.pg[uhszVmhSl}}ef]g5929:01^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQk1=7=6<=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=181289V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc95=5>45Z0.eqb+ta'nis"nbdx.pg[uhszVmhSl}}ef]g59>9:01^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQk1=;=6==R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=R?=8:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb6W;837X> gsd-vc)`kq$h`fv re]sjqtXojUjkh_e3\77><]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<Q;299V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc9V?946[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^f2[34?3\:$kh!rg-dg}(ddbr$~iQnup\cfYf{{olSi?P73:8Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`aXl8U3>55Z0.eqb+ta'nis"nbdx.pg[uhszVmhSl}}ef]g5Z?5=2_;#j|i.sd,cf~)keas#jPpovq[beXpfx;<=>=5:W3+bta&{l$knv!cmi{+wbXxg~ySjmPxnp34575=2_;#j|i.sd,cf~)keas#jPpovq[beXpfx;<=<=5:W3+bta&{l$knv!cmi{+wbXxg~ySjmPxnp34555=2_;#j|i.sd,cf~)keas#jPpovq[beXpfx;<=:=5:W3+bta&{l$knv!cmi{+wbXxg~ySjmPxnp34535=2_;#j|i.sd,cf~)keas#jPpovq[beXpfx;<=8=5:W3+bta&{l$knv!cmi{+wbXxg~ySjmPxnp34515=2_;#j|i.sd,cf~)keas#jPpovq[beXpfx;<=6=1:W3+bta&{l$knv!cmi{+rtXxg~ySoga<1<15>S7'nxm"h gbz-gim'~xT|cz}_ckm848592_;#j|i.sd,cf~)keas#z|Ppovq[goi4;49=6[?/fpe*w`(ojr%oaew/vp\tkruWkce0>0=1:W3+bta&{l$knv!cmi{+rtXxg~ySoga<5<15>S7'nxm"h gbz-gim'~xT|cz}_ckm808592_;#j|i.sd,cf~)keas#z|Ppovq[goi4?49=6[?/fpe*w`(ojr%oaew/vp\tkruWkce0:0=1:W3+bta&{l$knv!cmi{+rtXxg~ySoga<9<14>S7'nxm"h gbz-gim'~xT|cz}_ckm[5473\:$kh!rg-dg}(ddbr${Qnup\flhX9;:0Y=!hrg,qb*adp'iggu!xr^rmpwYeagU9>=5Z0.eqb+ta'nis"nbdx.uq[uhszVhbbR==0:W3+bta&{l$knv!cmi{+rtXxg~ySoga_503?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\176<]9%l~k }f.e`|+ekcq%|~R~ats]amkY1:91^<"i}f/pe+be&jf`t"y}_qlwvZdnfV=9<6[?/fpe*w`(ojr%oaew/vp\tkruWkceS5<9;T2,cw`)zo%lou lljz,swYwf}xTnd`Pxnp34565?2_;#j|i.sd,cf~)keas#z|Ppovq[goiWqey<=>?1348Q5)`zo$yj"ilx/aoo})pzVzexQmio]{kw67888<7X> gsd-vc)`kq$h`fv ws]sjqtXj`dTtb|?013263=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ~hz9:;>?94U1-dvc(un&mht#mcky-tvZvi|{UiecQwos234775>2_;#j|i.sd,cf~)keas#z|Ppovq[goiWqey<=><269V4*aun'xm#jmw.bnh|*quWyd~Rlfn^zlv567;;8=7X> gsd-vc)`kq$h`fv ws]sjqtXj`dTtb|?01613>S7'nxm"h gbz-gim'~xT|cz}_ckm[}iu89:?=?84U1-dvc(un&mht#mcky-tvZvi|{UiecQwos2340403\:$kh!rg-dg}(ddbr${Qnup\flhXpfx;<=;>279V4*aun'xm#jmw.bnh|*quWyd~Rlfn^zlv567>;20Y=!hrg,qb*adp'iggu!xr^rmpwYeagUsc>?073262=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ~hz9:;:?<m;T2,cw`)zo%lou lljz,swYwf}xTnd`Pxnp3450Xjmn;>;5Z0.eqb+ta'nis"nbdx.uq[uhszVhbbRv`r123371<]9%l~k }f.e`|+ekcq%|~R~ats]amkYg{:;<:?=0:W3+bta&{l$knv!cmi{+rtXxg~ySjm30?03?P6(o{l%~k!hcy,`hn~({U{by|Pgb>2:76<]9%l~k }f.e`|+ekcq%|~R~ats]dg949:91^<"i}f/pe+be&jf`t"y}_qlwvZad4:49<6[?/fpe*w`(ojr%oaew/vp\tkruWni783<?;T2,cw`)zo%lou lljz,swYwf}xTkn2:>328Q5)`zo$yj"ilx/aoo})pzVzexQhc=4=65=R8&myj#|i/fa{*fjlp&}yS}`{r^e`828582_;#j|i.sd,cf~)keas#z|Ppovq[be;07;m7X> gsd-vc)`kq$h`fv ws]sjqtXojU;=k5Z0.eqb+ta'nis"nbdx.uq[uhszVmhS<?i;T2,cw`)zo%lou lljz,swYwf}xTknQ=1g9V4*aun'xm#jmw.bnh|*quWyd~Ril_23e?P6(o{l%~k!hcy,`hn~({U{by|Pgb]75c=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[07a3\:$kh!rg-dg}(ddbr${Qnup\cfY19o1^<"i}f/pe+be&jf`t"y}_qlwvZadW>;m7X> gsd-vc)`kq$h`fv ws]sjqtXojU3>;5Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef>3:70<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlm7=3<9;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd8785>2_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnk1=1279V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqab:36;<0Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hi35?05?P6(o{l%~k!hcy,`hn~({U{by|Pgb]bwwc`4?49:6[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg=5=63=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumn632?;4U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\473<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmT=?;4U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\673<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmT??;4U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\073<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmT9?;4U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\273<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmT;?;4U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\<7?<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmTh<2?>3;8Q5)`zo$yj"ilx/aoo})pzVzexQhc^cpv`aXl86:2?74U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\`4:56;30Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hiPd0>0:7?<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmTh<2;>3;8Q5)`zo$yj"ilx/aoo})pzVzexQhc^cpv`aXl86>2?74U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\`4:16;30Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hiPd0>4:7?<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmTh<27>3:8Q5)`zo$yj"ilx/aoo})pzVzexQhc^cpv`aXl8U;>55Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g5Z7502_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnkRj>_30;?P6(o{l%~k!hcy,`hn~({U{by|Pgb]bwwc`Wm;T??64U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\`4Y3:11^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1^71<>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboVn:S;<7;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[a7X?;20Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hiPd0];60=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[}iu89:;>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSua}012260=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[}iu89:9>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSua}012060=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[}iu89:?>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSua}012660=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[}iu89:=>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSua}012475=R8&myj#|i/fn3*wb(o{;%~kyit.Onq}YUIDUYHRKA_GUEP775n2_;#j|i.sd,ci6)zm%l~< }fvdw+HkrpVXJAR\JGNWW[@H69;n0Y=!hrg,qb*ak8'xo#j|>.sdtbq)d}{xTjzh{_rvbp`:76;n0Y=!hrg,qb*ak8'xo#j|>.sdtbq)d}{xTjzh{_rvbp`:66;i0Y=!hrg,qb*ak8'xo#j|>.sdtbq)d}{xTjzh{_rvbp`Y7:j1^<"i}f/pe+bj7&{n$k?!rguep*erz{Um{kzPsucwaZ74=2_;#j|i.sd,ci6)zm%l~< }fvdw+fsuzVl|jyQ|t`vf[hs89::0=0<6:W3+bta&{l$ka>!re-dv4(un~l#n{}r^dtbqYt|h~nS`{w01228586;<1^<"i}f/pe+bj7&{n$k?!rguep*erz{Um{kzPsucwaZkrp9:;=1?1379V4*aun'xm#jb?.sf,cw7)zo}mx"mzrs]escrX{}kiRczx12359799;20Y=!hrg,qb*ak8'xo#j|>.sdtbq)bey~rSkyit^da62=R8&myj#|i/fn3*wb(o{;%~kyit.gntqXn~lSd<i;T2,cw`)zo%l`= }d.eq5+tao~$i`~{y^dtbqYnWds<=>?319V4*aun'xm#jb?.sf,cw7)zo}mx"kbpu{\br`sW`Ufyu>?0131=>S7'nxm"h gm2-va)`zhy%~~z|/b2,gdtuqgo0=0=9:W3+bta&{l$ka>!re-dvdu)zz~x#n> c`pq}kcs484956[?/fpe*w`(oe:%~i!hr`q-vvrt'j:$ol|}yogw878512_;#j|i.sd,ci6)zm%l~l}!rrvp+f6(khxyuck{<2<1b>S7'nxm"h gm2-va)`zhy%~~z|/b2,chs&ngP<P hm0,n57`<]9%l~k }f.eo4+tc'nxj#||tr-`4*aj}q$laV?R.fop*hu5n2_;#j|i.sd,ci6)zm%l~l}!rrvp+f6(ods"jcT2\,div(j{;l0Y=!hrg,qb*ak8'xo#j|ns/pppv)d8&mfyu hmZ1^*bkt&dy9j6[?/fpe*w`(oe:%~i!hr`q-vvrt'j:$k`{w.foX0X(`ez$f?=4U1-dvc(un&mg<#|k/fpbw+tt|z%h<"x><1<17>S7'nxm"h gm2-va)`zhy%~~z|/b2,r4:66;90Y=!hrg,qb*ak8'xo#j|ns/pppv)d8&|:0?0=3:W3+bta&{l$ka>!re-dvdu)zz~x#n> v0>0:75<]9%l~k }f.eo4+tc'nxj#||tr-`4*p64=49n6[?/fpe*w`(oe:%~i!hr`q-vvrt'j:$z<Q?_`lg45679;h0Y=!hrg,qb*ak8'xo#j|ns/pppv)d8&|:S<Qnne234575j2_;#j|i.sd,ci6)zm%l~l}!rrvp+f6(~8U9Sl`k012357d<]9%l~k }f.eo4+tc'nxj#||tr-`4*p6W:Ujbi>?0131f>S7'nxm"h gm2-va)`zhy%~~z|/b2,r4Y3Whdo<=>?13;8Q5)`zo$yj"ic0/pg+btf{'xxx~!l1.abvwim}6;2?74U1-dvc(un&mg<#|k/fpbw+tt|z%h="mnrs{maq:66;30Y=!hrg,qb*ak8'xo#j|ns/pppv)d9&ij~waeu>1:7?<]9%l~k }f.eo4+tc'nxj#||tr-`5*efz{seiy2<>3d8Q5)`zo$yj"ic0/pg+btf{'xxx~!l1.enq}(`eR:V"jc>.l31b>S7'nxm"h gm2-va)`zhy%~~z|/b3,chs&ngP=P hmr,nw7`<]9%l~k }f.eo4+tc'nxj#||tr-`5*aj}q$laV<R.fop*hu5n2_;#j|i.sd,ci6)zm%l~l}!rrvp+f7(ods"jcT3\,div(j{;l0Y=!hrg,qb*ak8'xo#j|ns/pppv)d9&mfyu hmZ6^*bkt&dy9?6[?/fpe*w`(oe:%~i!hr`q-vvrt'j;$z<2?>318Q5)`zo$yj"ic0/pg+btf{'xxx~!l1.t28485;2_;#j|i.sd,ci6)zm%l~l}!rrvp+f7(~8692?=4U1-dvc(un&mg<#|k/fpbw+tt|z%h="x><2<17>S7'nxm"h gm2-va)`zhy%~~z|/b3,r4:36;h0Y=!hrg,qb*ak8'xo#j|ns/pppv)d9&|:S=Qnne234575j2_;#j|i.sd,ci6)zm%l~l}!rrvp+f7(~8U:Sl`k012357d<]9%l~k }f.eo4+tc'nxj#||tr-`5*p6W;Ujbi>?0131f>S7'nxm"h gm2-va)`zhy%~~z|/b3,r4Y4Whdo<=>?13`8Q5)`zo$yj"ic0/pg+btf{'xxx~!l1.t2[1Yffm:;<=?=0:W3+bta&{l$ka>!re-dvdu)zz~x#nabp103?P6(o{l%~k!hl1,q`*auiz$yy} cnos57?<]9%l~k }f.eo4+tc'nxj#||tr-qehYbey~rSklPi228Q5)`zo$yj"ic0/pg+btf{'xxx~!}al]fiur~WohTeRa}012374=R8&myj#|i/fn3*wb(o{kx"}{s.pbiZcjx}sTjoQf_np34566::1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~by<;;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw572<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~9>95Z0.eqb+ta'nf;"j rqlwv*Kdg|dSnaznu110>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|=8?7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{5368Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkr1:=1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~by9=4:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmp=433\:$kh!rg-dh5(ul&x{by| MbmvjqYdg|d5?74U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\g|:76;i0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPcx>3:Zts:01^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQly=3=6f=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Uhu1?1_sv1=>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vir0?0=c:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmpZe~4;4T~y<6;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[f;;78h7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_b{?7;Yu|;30Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPcx>7:7e<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~Tot2;>^pw6<=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Uhu1;12b9V4*aun'xm#jb?.sf,vuhsz&Ghcx`{_bmvjqYdq5?5Sz=9:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmpZe~4?49o6[?/fpe*w`(oe:%~i!}povq+Heh}g~Tob{at^az838Xz}827X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_b{?3;4d3\:$kh!rg-dh5(ul&x{by| MbmvjqYdg|dSnw37?]qp7?<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~Tot27>3a8Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkrXkp632R|{2`9V4*aun'xm#jb?.sf,vuhsz&Ghcx`{_bmvjqYg{6;2?o4U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\|jt;978j7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_ymq8785i2_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfexRv`r=1=6d=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Usc2;>3c8Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkrXpfx793<n;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[}iu4?49m6[?/fpe*w`(oe:%~i!}povq+Heh}g~Tob{at^zlv919:h1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQwos>;:7g<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~Ttb|39?0g?P6(o{l%~k!hl1,q`*twf}x$Anaznu]`kphsWqey040Pru3e?P6(o{l%~k!hl1,q`*twf}x$ob{at=2=5c=R8&myj#|i/fn3*wb(zyd~"m`uov?5;7a3\:$kh!rg-dh5(ul&x{by| cnwmp9499o1^<"i}f/pe+bj7&{n$~}`{r.alqkr;;7;m7X> gsd-vc)`d9$yh"|nup,gjsi|5>5=k5Z0.eqb+ta'nf;"j rqlwv*eh}g~793?i;T2,cw`)zo%l`= }d.psjqt(kfex1811g9V4*aun'xm#jb?.sf,vuhsz&idycz37?3e?P6(o{l%~k!hl1,q`*twf}x$ob{at=:=5c=R8&myj#|i/fn3*wb(zyd~"m`uov?=;7b3\:$kh!rg-dh5(ul&x{by| cnwmpZ66m2_;#j|i.sd,ci6)zm%y|cz}/bmvjqY69l1^<"i}f/pe+bj7&{n$~}`{r.alqkrX:8o0Y=!hrg,qb*ak8'xo#~ats-`kphsW:;n7X> gsd-vc)`d9$yh"|nup,gjsi|V>:i6[?/fpe*w`(oe:%~i!}povq+firf}U>=h5Z0.eqb+ta'nf;"j rqlwv*eh}g~T:<k4U1-dvc(un&mg<#|k/srmpw)dg|dS:?j;T2,cw`)zo%l`= }d.psjqt(kfexR6>e:W3+bta&{l$ka>!re-qtkru'je~byQ6239V4*aun'xm#jb?.sf,vuhsz&idyczPd0>3:74<]9%l~k }f.eo4+tc'{zex!lotlw[a7;97897X> gsd-vc)`d9$yh"|nup,gjsi|Vn:0?0=2:W3+bta&{l$ka>!re-qtkru'je~byQk1=1=67=R8&myj#|i/fn3*wb(zyd~"m`uov\`4:36;80Y=!hrg,qb*ak8'xo#~ats-`kphsWm;793<=;T2,cw`)zo%l`= }d.psjqt(kfexRj><7<16>S7'nxm"h gm2-va)uxg~y#naznu]g5919:;1^<"i}f/pe+bj7&{n$~}`{r.alqkrXl8632?<4U1-dvc(un&mg<#|k/srmpw)dg|dSi?39?02?P6(o{l%~k!hl1,q`*twf}x$ob{at^f2[5463\:$kh!rg-dh5(ul&x{by| cnwmpZb6W88:7X> gsd-vc)`d9$yh"|nup,gjsi|Vn:S?<>;T2,cw`)zo%l`= }d.psjqt(kfexRj>_202?P6(o{l%~k!hl1,q`*twf}x$ob{at^f2[1463\:$kh!rg-dh5(ul&x{by| cnwmpZb6W<8:7X> gsd-vc)`d9$yh"|nup,gjsi|Vn:S;<>;T2,cw`)zo%l`= }d.psjqt(kfexRj>_602?P6(o{l%~k!hl1,q`*twf}x$ob{at^f2[=463\:$kh!rg-dh5(ul&x{by| cnwmpZb6W08?7X> gsd-vc)`d9$yh"|nup,gjsi|Vddx=>?13;8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.abvwim}6;2?74U1-dvc(un&mg<#y}/fubw+qt|z%h="mnrs{maq:66;30Y=!hrg,qb*ak8'}y#jyns/uppv)d9&ij~waeu>1:7?<]9%l~k }f.eo4+qu'n}j#y|tr-`5*efz{seiy2<>3d8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.enq}(`eR:V"jc>.l31b>S7'nxm"h gm2-sw)`hy%{~z|/b3,chs&ngP=P hmr,nw7`<]9%l~k }f.eo4+qu'n}j#y|tr-`5*aj}q$laV<R.fop*hu5n2_;#j|i.sd,ci6){%l{l}!wrvp+f7(ods"jcT3\,div(j{;l0Y=!hrg,qb*ak8'}y#jyns/uppv)d9&mfyu hmZ6^*bkt&dy9?6[?/fpe*w`(oe:%{!hw`q-svrt'j;$z<2?>318Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.t28485;2_;#j|i.sd,ci6){%l{l}!wrvp+f7(~8692?=4U1-dvc(un&mg<#y}/fubw+qt|z%h="x><2<17>S7'nxm"h gm2-sw)`hy%{~z|/b3,r4:36;h0Y=!hrg,qb*ak8'}y#jyns/uppv)d9&|:S=Qnne234575j2_;#j|i.sd,ci6){%l{l}!wrvp+f7(~8U:Sl`k012357d<]9%l~k }f.eo4+qu'n}j#y|tr-`5*p6W;Ujbi>?0131f>S7'nxm"h gm2-sw)`hy%{~z|/b3,r4Y4Whdo<=>?13`8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.t2[1Yig}:;<=?=9:W3+bta&{l$ka>!ws-dsdu)z~x#n< c`pq}kcs494956[?/fpe*w`(oe:%{!hw`q-svrt'j8$ol|}yogw848512_;#j|i.sd,ci6){%l{l}!wrvp+f4(khxyuck{<3<1=>S7'nxm"h gm2-sw)`hy%{~z|/b0,gdtuqgo0>0=f:W3+bta&{l$ka>!ws-dsdu)z~x#n< glw{*bk\8T$la< b13d8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.enq}(`eR;V"jc|.lq1b>S7'nxm"h gm2-sw)`hy%{~z|/b0,chs&ngP>P hmr,nw7`<]9%l~k }f.eo4+qu'n}j#y|tr-`6*aj}q$laV=R.fop*hu5n2_;#j|i.sd,ci6){%l{l}!wrvp+f4(ods"jcT4\,div(j{;90Y=!hrg,qb*ak8'}y#jyns/uppv)d:&|:0=0=3:W3+bta&{l$ka>!ws-dsdu)z~x#n< v0>2:75<]9%l~k }f.eo4+qu'n}j#y|tr-`6*p64;49?6[?/fpe*w`(oe:%{!hw`q-svrt'j8$z<2<>318Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.t28185j2_;#j|i.sd,ci6){%l{l}!wrvp+f4(~8U;Sl`k012357d<]9%l~k }f.eo4+qu'n}j#y|tr-`6*p6W8Ujbi>?0131f>S7'nxm"h gm2-sw)`hy%{~z|/b0,r4Y5Whdo<=>?13`8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l2.t2[6Yffm:;<=?=b:W3+bta&{l$ka>!ws-dsdu)z~x#n< v0]7[kis89:;=?>4U1-dvc(un&mg<#y}/fubw+qt|z%hc`~>219V4*aun'xm#jb?.vp,crgt&~y"m`mq01<>S7'nxm"h gm2-sw)`hy%{~z|/scn[cskdVliSd<:;T2,cw`)zo%l`= xr.etev(p{}y$~lcPftno[l4c3\:$kh!rg-dh5(pz&m|m~ xsuq,vdkXn|fgSdQbuy23454b3\:$kh!rg-dh5(pz&m|m~ xsuq,vdkXn|fgSdQbuy234576l2_;#j|i.sd,ci6){%ym`Qxr^gm[l75;2_;#j|i.sd,ci6){%||cz}/LalqkrXkfex?:4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov261=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}8986[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at207?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphs<;>0Y=!hrg,qb*ak8'}y#z~ats-Ngjsi|Vidycz:259V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjq05<2_;#j|i.sd,ci6){%||cz}/LalqkrXkfex:<;;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw<7?<]9%l~k }f.eo4+qu'~zex!BcnwmpZeh}g~Tot2?>3a8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXkp6;2R|{289V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYdq5;5>n5Z0.eqb+ta'nf;"z| wqlwv*Kdg|dSnaznu]`}979W{~956[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^az8785k2_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRmv<3<\vq4>3\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|dSnw33?0`?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphsWjs7?3Q}t3;8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXkp6?2?m4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov\g|:36Vx>45Z0.eqb+ta'nf;"z| wqlwv*Kdg|dSnaznu]`}939:j1^<"i}f/pe+bj7&~x${}`{r.O`kphsWje~byQly=7=[wr512_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRmv<7<1g>S7'nxm"h gm2-sw)pxg~y#@m`uov\gjsi|Vir0;0Pru0:?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphsWjs7;3<l;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw[f;?7Uyx?o4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov\|jt;878j7X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{_ymq8485i2_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRv`r=0=6d=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}Usc2<>3c8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXpfx783<n;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw[}iu4<49m6[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^zlv909:h1^<"i}f/pe+bj7&~x${}`{r.O`kphsWje~byQwos>4:7g<]9%l~k }f.eo4+qu'~zex!BcnwmpZeh}g~Ttb|38?0g?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphsWqey050Pru3e?P6(o{l%~k!hl1,tv*qwf}x$ob{at=2=5c=R8&myj#|i/fn3*rt(yd~"m`uov?5;7a3\:$kh!rg-dh5(pz&}{by| cnwmp9499o1^<"i}f/pe+bj7&~x${}`{r.alqkr;;7;m7X> gsd-vc)`d9$|~"ynup,gjsi|5>5=k5Z0.eqb+ta'nf;"z| wqlwv*eh}g~793?i;T2,cw`)zo%l`= xr.usjqt(kfex1811g9V4*aun'xm#jb?.vp,suhsz&idycz37?3e?P6(o{l%~k!hl1,tv*qwf}x$ob{at=:=5`=R8&myj#|i/fn3*rt(yd~"m`uov\44c<]9%l~k }f.eo4+qu'~zex!lotlw[47b3\:$kh!rg-dh5(pz&}{by| cnwmpZ46m2_;#j|i.sd,ci6){%||cz}/bmvjqY49l1^<"i}f/pe+bj7&~x${}`{r.alqkrX<8o0Y=!hrg,qb*ak8'}y#z~ats-`kphsW<;n7X> gsd-vc)`d9$|~"ynup,gjsi|V<:i6[?/fpe*w`(oe:%{!xpovq+firf}U<=h5Z0.eqb+ta'nf;"z| wqlwv*eh}g~T4?<4U1-dvc(un&mg<#y}/vrmpw)dg|dSi?30?01?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f28485:2_;#j|i.sd,ci6){%||cz}/bmvjqYc9585>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th<2<>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e3?0;453\:$kh!rg-dh5(pz&}{by| cnwmpZb64<49>6[?/fpe*w`(oe:%{!xpovq+firf}Uo=181239V4*aun'xm#jb?.vp,suhsz&idyczPd0>4:74<]9%l~k }f.eo4+qu'~zex!lotlw[a7;078:7X> gsd-vc)`d9$|~"ynup,gjsi|Vn:S=<>;T2,cw`)zo%l`= xr.usjqt(kfexRj>_002?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f2[7463\:$kh!rg-dh5(pz&}{by| cnwmpZb6W:8:7X> gsd-vc)`d9$|~"ynup,gjsi|Vn:S9<>;T2,cw`)zo%l`= xr.usjqt(kfexRj>_402?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f2[3463\:$kh!rg-dh5(pz&}{by| cnwmpZb6W>8:7X> gsd-vc)`d9$|~"ynup,gjsi|Vn:S5<=;T2,cw`)zo%l`= xr.usjqt(kfexRj=<1<16>S7'nxm"h gm2-sw)pxg~y#naznu]g6979:;1^<"i}f/pe+bj7&~x${}`{r.alqkrXl;692?<4U1-dvc(un&mg<#y}/vrmpw)dg|dSi<33?01?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f18185:2_;#j|i.sd,ci6){%||cz}/bmvjqYc:5?5>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th?29>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e0?3;453\:$kh!rg-dh5(pz&}{by| cnwmpZb54149=6[?/fpe*w`(oe:%{!xpovq+firf}Uo>R>=1:W3+bta&{l$ka>!ws-ttkru'je~byQk2^315>S7'nxm"h gm2-sw)pxg~y#naznu]g6Z4592_;#j|i.sd,ci6){%||cz}/bmvjqYc:V99=6[?/fpe*w`(oe:%{!xpovq+firf}Uo>R:=1:W3+bta&{l$ka>!ws-ttkru'je~byQk2^715>S7'nxm"h gm2-sw)pxg~y#naznu]g6Z0592_;#j|i.sd,ci6){%||cz}/bmvjqYc:V=9=6[?/fpe*w`(oe:%{!xpovq+firf}Uo>R6=4:W3+bta&{l$ka>!ws-ttkru'je~byQaou2344703\:$kh!rg-nah)cg|~Te1>1199V4*aun'xm#`kb/emvpZo;994:46[?/fpe*w`(elg$hb{{_h>25;7?3\:$kh!rg-nah)cg|~Te1?=>0:8Q5)`zo$yj"cjm.flqqYn4895=55Z0.eqb+ta'dof#iazt^k?518602_;#j|i.sd,i`k(lfSd2>5?3;?P6(o{l%~k!bel-gkprXa5;=2<64U1-dvc(un&gna"j`uu]j84199>1^<"i}f/pe+hcj'me~xRg31?34?P6(o{l%~k!bel-gkprXa585=:5Z0.eqb+ta'dof#iazt^k?7;703\:$kh!rg-nah)cg|~Te1:1169V4*aun'xm#`kb/emvpZo;=7;<7X> gsd-vc)jmd%ocxzPi=4=52=R8&myj#|i/lgn+air|Vc7;3?8;T2,cw`)zo%fi`!kotv\m9>99>1^<"i}f/pe+hcj'me~xRg39?35?P6(o{l%~k!bel-gkprXaV:::6[?/fpe*w`(elg$hb{{_h]252=R8&myj#|i/lgn+air|VcT==?8;T2,cw`)zo%fi`!kotv\mZ769>1^<"i}f/pe+hcj'me~xRgP1334?P6(o{l%~k!bel-gkprXaV;8=:5Z0.eqb+ta'dof#iazt^k\51703\:$kh!rg-nah)cg|~TeR?:169V4*aun'xm#`kb/emvpZoX9?;<7X> gsd-vc)jmd%ocxzPi^3453=R8&myj#|i/lgn+air|VcT><84U1-dvc(un&gna"j`uu]j[6713\:$kh!rg-nah)cg|~TeR:>6:W3+bta&{l$ahc dnww[lY29?1^<"i}f/pe+hcj'me~xRgP6048Q5)`zo$yj"cjm.flqqYnW>;=7X> gsd-vc)jmd%ocxzPi^:22>S7'nxm"h mdo,`jssW`U2=45Z0.eqb+ta'dof#iazt^ofi9699h1^<"i}f/pe+hcj'me~xRcjm=33:4g<]9%l~k }f.ofi*bh}}Ufi`2>1?3b?P6(o{l%~k!bel-gkprXelg7=?0>a:W3+bta&{l$ahc dnww[hcj4895=l5Z0.eqb+ta'dof#iazt^ofi97368k0Y=!hrg,qb*kbe&ndyyQbel>21;7f3\:$kh!rg-nah)cg|~Tahc317<2e>S7'nxm"h mdo,`jssWdof0<91189V4*aun'xm#`kb/emvpZkbe5;5=45Z0.eqb+ta'dof#iazt^ofi949901^<"i}f/pe+hcj'me~xRcjm=1=5<=R8&myj#|i/lgn+air|Vgna1:1189V4*aun'xm#`kb/emvpZkbe5?5=45Z0.eqb+ta'dof#iazt^ofi909901^<"i}f/pe+hcj'me~xRcjm=5=5<=R8&myj#|i/lgn+air|Vgna161189V4*aun'xm#`kb/emvpZkbe535;95Z0.eqb+ta'dof#jlb.f`nc+aeenk%bjklc/`nc*dkcVgnaRijndpbpjt(~hfbh#m|ts-qehjhgyQ;Q#|nm/p,w6Yig`dbx#|nm.fsvdk)ly9=t<6!r`o2f>S7'nxm"h mdo,phvXzhgT~iQjn0a8Q5)`zo$yj"cjm.vntZtfeVxoSh`>169V4*aun'xm#ob_sgdkprXmg;o7X> gsd-vc)u{}hgg"|k_sqw[duumn8;7X> gsd-vc)u{}hgg"|k_sqw[duumnUo=?>4U1-dvc(un&xxxobd/sf\vvrXizxnkRj=1b9V4*aun'xm#}{bmi,vaYu{}Uhc`l>d:W3+bta&{l$~~zmlj-q`Ztt|Vidao?>e:W3+bta&{l$~~zmlj-q`Ztt|Vxnk1>11d9V4*aun'xm#}{bmi,vaYu{}Uyij2>>0g8Q5)`zo$yj"||tcnh+wbXzz~T~hi32?3g?P6(o{l%~k!}su`oo*tcW{ySkh_13g?P6(o{l%~k!}su`oo*tcW{ySkh_03g?P6(o{l%~k!}su`oo*tcW{ySkh_33g?P6(o{l%~k!}su`oo*quW{ySl}}ef03?P6(o{l%~k!}su`oo*quW{ySl}}ef]g576<]9%l~k }f.pppgjl'~xT~~zParpfcZb59j1^<"i}f/pe+wusjea${Q}su]`khd6l2_;#j|i.sd,vvredb%|~R||t^alig76m2_;#j|i.sd,vvredb%|~R||t^pfc9699l1^<"i}f/pe+wusjea${Q}su]qab:668n0Y=!hrg,qb*tt|kf`#z|Prrv\v`aX88n0Y=!hrg,qb*tt|kf`#z|Prrv\v`aX9h1^_H\PAMKBWf=R[LXTZD]FBMG0?SED12\BIZQ[YQG0?RCF;2]NNn5XRHVF[HICMVKh7Z\FTD]NKACXJm1\^DZJ_VKGPMYFl2]YEYKPWHFWLZD6l2RB@D@W-YFA$5(6(Z^^N->!1!CPGLO23QEYOT84XRVOMG1<PZ^TKCJ8;YQW[SEDj2RTOB\J_HLEK3=_lkUBhk5Wdi]SvlkQm{ybcc??;Yfn[Hgmg{\n~~g`n028\akXE`dd~[k}shmmg>gkefyShctx`8eikh{}Umyab9;cc`opvc3kkhgx~Pm`phaw5<keao7io{a^alqkr/8 n0hlzn_bmvjq.6!m1omyoPcnwmp-4.l2njxlQlotlw,6/c3mkmRm`uov+0,b<lh~jSnaznu*6-a=ci}kTob{at)4*`>bf|hUhcx`{(6+g?agsiVidycz'8(d8`drfWje~by27:1<4?adn|lxy:6jfn)2*2>bnf!;";6jfn)33-2=cag":=$94dhl+57/03mce$<=&7:fjj-73!>1oec&>5(58`lh/9?#<7iga(05*3>bnf!;3%:5kio*2=,0<l`d#>$94dhl+65/03mce$??&7:fjj-45!>1oec&=3(58`lh/:=#<7iga(37*3>bnf!8=%:5kio*13,1<l`d#>5'8;ekm,7?.>2nbb%=&7:fjj-57!>1oec&<1(58`lh/;;#<7iga(21*3>bnf!9?%:5kio*01,0<l`d#8$84dhl+1,0<l`d#:$84dhl+3,0<l`d#4$84dhl+=,0<l`d7<394dhl?55803mce0<?17:fjj9756>1oec2>3?58`lh;9=4<7iga<07=3>bnf5;=2:5kio>23;1<l`d7=508;ekm84?9>2nbb1?17:fjj9476>1oec2=1?58`lh;:;4<7iga<31=3>bnf58?2:5kio>11;1<l`d7>;08;ekm8719?2nbb1<7>69gmk:517<0hd`32?58`lh;;94<7iga<23=3>bnf5992:5kio>07;1<l`d7?906;ekm863=87=0hd`334<5?aoi4:4=7iga<5<5?aoi4<4=7iga<7<5?aoi4>4=7iga<9<5?aoi404<7iazt)2*3>bh}}":%55kotv+55/?3me~x%?>)99gkpr/9;#37iazt)30-==cg|~#=9'7;emvp-72!11ocxz'17+;?air|!;<%:5kotv+6,1<lf$>'8;emvp-2.?2ndyy&:)69gkpr/> =0hb{{(6+4?air|!2";6j`uu*:-2=cg|~7<364dnww846902ndyy2>1?:8`jss488546j`uu>27;><lf0<:18:flqq:6=720hb{{<04=e>bh}}6:;7>18:flqq:6?7=0hb{{<0<4?air|585;6j`uu>0:2=cg|~78394dnww80803me~x1817:flqq:06>1ocxz38?58`jss40437hjff3ld`0=bey~r>k5iigm\c`hbzh~d~Rx9_0.#\ljnfq*HC_K/Gdlfvdrhz);9"<?l;gkekZ~kfqU>=?v<6^0`hnY4>}e:4>o4fhdl[}jipV?:>u=9_3aooZ51|f;3 kgio^efj`tf|fxTz;Q>,OMMA)HHFL>;=6hffn]{hk~X=88s?;Q=cmi\73rh91&mekaPgdlfvdrhzV|=S<"tc^jbwZoi|Vigg0>#c^jbwZuu{}7; nQ}d^dqat;6$jUnbllce^pppZu~fj7: nQgar]q`Zbf|hUhcx`{=1.`[aoiW~coxe3<6-a\lduX{UomyoPcnwmp86+kVl~`aQil`ep[wusWkg1="l_hosh`kbf}keb`Ptxrf97*dW|ynShcmeeff`Ztbo4:'oRy}_gpfu87+kVxiRj`uu]qwq;6$jU~bik}fmmt[iip59&hSeo|_ntfvcjh4:'oR~}emmb`Zjf|ldhu0>#c^flqqYpam~c1<6#c^opcjhX~hf6=!mPre]gauro58:98!mPesplvZoiblieb`Ptxrf95*dWakxSx`kesdokr;7$jUcm~QnllmppZ`rde7; nQgar]qwq;6$jUomyoPcnwmpZqnl}b65!mPh`q\swYfkb7; nQzsd]fgf;7$jUhc`c`n^aokfm:8%iT{Qncj]okr;7$jUyhR~ats]tmaro58:'oR{|e^dtbqYci}kTob{at<2/gZnf{Vkgab}{_dosp|;7$jUyhRjnt`]`kphsW~coxe3>0-a\kscunee|Saax=1.`[rtXxg~ySzgkti?:(fYwzfmTi`~{y^vzt`;7$jU|~Rjnt`]`kphsW~coxe36,b]sv`jhimUyij}21-a\`jssW{yS{oc=1.`[mgtWmkmRm`uov>4)eXx{elSk{cl^vkv`uoWgolmykPv`n>15>+kV}ySikti?657*dWyxdkRkbpu{\pmtb{aUeijo{e^tbh83+kVzycjQjmqvz[qnumzbTm~}jru]uei;3$jUcm~Qyamkg95*dWyxdkRhzlm]wlwct`Vkxh|{_wco906>$jef|b`jnu]mehc:n`ldSubax^726}51W;iggR=9tn3;(fYqiecoSaax=1.`[utneVlbjbQ{yqg>144;?&hS}|`g^dvhiYsqyo6<!mPmdolv|Ysqyo6=!s<6:djbjYdgrT9<<w37]1gimX;?~d=5Qiigm\c`hbzh~d~Rx9_0]{wqY6<2l~`aj4iohfgqbea}oy~i5fnkg`pvdn|lxy;6gat^aoo==iojh~eaj7;ntfvcjhh1{~biPelrw}42<x{elShctx]wlwct`!:"=95rne\ahvsqV~c~h}g(0+20>vugnUna}zv_ujqavn/: ;?7}|`g^gntqX|axne&<)068twi`Wlg{xtQ{hsgpl-2.9=1{~biPelrw}Zrozlyc$8'>4:rqkbYbey~rSyf}erj+2,733yxdkRkbpu{\pmtb{a"<%<:4psmd[`kw|pUdk|h):*51=wzfmTi`~{y^vkv`uo 0#::6~}of]fiur~W}byi~f39;2=5g=wzfmTi`~{y^vkv`uoWhyxiz'0(3a?uthoVof|ywPtipfwmYf{zoyx%?&1c9svjaXmdzuRzgrdqk[dutm{~#>$?m;qplcZcjx}sTxe|jsi]bwvcu|!9"=o5rne\ahvsqV~c~h}g_`qpawr/< ;i7}|`g^gntqX|axneQnsrgqp-3.9k1{~biPelrw}ZrozlycSl}|esv+2,7e3yxdkRkbpu{\pmtb{aUj~k}t)5*5g=wzfmTi`~{y^vkv`uoWhyxiz'8(3a?uthoVof|ywPtipfwmYf{zoyx%7&1e9svjaXmdzuRzgrdqk[dutm{~757>11c9svjaXmdzuRzgrdqk[kc`i}o#<$?m;qplcZcjx}sTxe|jsi]mabgsm!;"=o5rne\ahvsqV~c~h}g_ogdeqc/: ;i7}|`g^gntqX|axneQaefcwa-5.9k1{~biPelrw}ZrozlycSckhaug+0,7e3yxdkRkbpu{\pmtb{aUeijo{e)7*5g=wzfmTi`~{y^vkv`uoWgolmyk'6(3a?uthoVof|ywPtipfwmYimnki%9&1c9svjaXmdzuRzgrdqk[kc`i}o#4$?m;qplcZcjx}sTxe|jsi]mabgsm!3"=i5rne\ahvsqV~c~h}g_ogdeqc;13:556~}of]eqij6;2zycjQiumn\pmtb{a";%<=4psmd[cskdV~c~h}g(0+27>vugnUmyabPtipfwm.5!890|ah_gwohZrozlyc$>'>3:rqkbYa}efTxe|jsi*7-45<x{elSk{cl^vkv`uo <#:?6~}of]eqijX|axne&9)018twi`Wog`Rzgrdqk,2/6;2zycjQiumn\pmtb{a"3%<;4psmd[cskdV~c~h}g<983:4g<x{elSk{cl^vkv`uoWhyxiz'0(3b?uthoVl~`aQ{hsgplZgt{lx$<'>a:rqkbYa}efTxe|jsi]bwvcu|!8"=l5rne\bpjkW}byi~fParqfvq.4!8k0|ah_gwohZrozlycSl}|esv+0,7f3yxdkRhzlm]wlwct`Vkxh|{(4+2e>vugnUmyabPtipfwmYf{zoyx%8&1`9svjaXn|fgSyf}erj\evubz}"<%<o4psmd[cskdV~c~h}g_`qpawr/0 ;h7}|`g^dvhiYs`{oxdRo|sdpw8=<768k0|ah_gwohZrozlycSckhaug+4,7f3yxdkRhzlm]wlwct`Vdnklzj(0+2e>vugnUmyabPtipfwmYimnki%<&1`9svjaXn|fgSyf}erj\j`af|l"8%<o4psmd[cskdV~c~h}g_ogdeqc/< ;j7}|`g^dvhiYs`{oxdR`jg`vf,0/6i2zycjQiumn\pmtb{aUeijo{e)4*5d=wzfmTjxbc_ujqavnXflmjxh&8)0c8twi`Wog`Rzgrdqk[kc`i}o#4$?l;qplcZ`rdeUdk|h^lfcdrb410;2;5}d^aoo46<zmUomyoPcnwmp-6.991yhRjnt`]`kphs 8#:<6|k_ecweZeh}g~#>$??;sf\`drfWje~by&<)028vaYci}kTob{at)6*55=ulVnjxlQlotlw,0/682xoSio{a^alqkr/> ;;7jPd`vb[firf}"<%<>4re]geqgXkfex%6&119q`Zbf|hUhcx`{(8+24>tcWmkmRm`uov?4;753{nThlzn_bmvjq:>294>7jPeo48vaYu{}90~~z8;r`jp`tu<2yyy:4tswf=>sillxm`by:;wcoma0<{Ujof84ws]`hn773~xThlzn_bmvjq.7!8:0{Qkauc\gjsi|!;"==5xr^fbpdYdg|d$?'>0:uq[agsiVidycz'3(33?rtXlh~jSnaznu*7-46<{UomyoPcnwmp-3.991|~Rjnt`]`kphs ?#:<6y}_ecweZeh}g~#;$??;vp\`drfWje~by&7)008swYci}kTob{at=:94;3<{Unb;5xr^pppxFGxh<>7MNw1;D90?7|[=l188;57;306g0dk398:ljtn2f6>4=i;m<1:6*<d280ga=z[=n188;57;306g0dk398:lj4S00b>107290:??l9cb8073gb3Z>o698?:18277d1kj08?;oi;e66<?6=93;p_9h544793?74:k<ho7=<6`f8rQ7?=3:1=7?517;xW1`=<<?1;7?<2c4`g?54>hn0(>m9:00a?S5c<38py<=<:09v562=82w/=:75199a00>=839o6>4<dzJ0g1=]<<09wk4>7;'5=g=<<20(>j=:574?l2e83:17d:l4;29?j22k3:17b::6;29?l2e13:17d:m2;29?j2413:1(<9m:56b?k70i3:07b:<8;29 41e2=>j7c?8a;38?j24?3:1(<9m:56b?k70i3807b:<6;29 41e2=>j7c?8a;18?j24=3:1(<9m:56b?k70i3>07b:<4;29 41e2=>j7c?8a;78?j24;3:1(<9m:56b?k70i3<07b:<2;29 41e2=>j7c?8a;58?j2393:1(<9m:56b?k70i3207b:;0;29 41e2=>j7c?8a;;8?j24n3:1(<9m:56b?k70i3k07b:<e;29 41e2=>j7c?8a;`8?j24l3:1(<9m:56b?k70i3i07b:<c;29 41e2=>j7c?8a;f8?j24j3:1(<9m:56b?k70i3o07b:<a;29 41e2=>j7c?8a;d8?j2493:1(<9m:56b?k70i3;;76a;3183>!70j3>?m6`>7`825>=n<9>1<7*>7c8762=i9>k1<65f41194?"6?k0?>:5a16c95>=n<981<7*>7c8762=i9>k1>65f41394?"6?k0?>:5a16c97>=n<9:1<7*>7c8762=i9>k1865f3gd94?"6?k0?>:5a16c91>=n;on1<7*>7c8762=i9>k1:65f3ga94?"6?k0?>:5a16c93>=n;oh1<7*>7c8762=i9>k1465f3gc94?"6?k0?>:5a16c9=>=n;o31<7*>7c8762=i9>k1m65f3g:94?"6?k0?>:5a16c9f>=n;o=1<7*>7c8762=i9>k1o65f3g494?"6?k0?>:5a16c9`>=n;o?1<7*>7c8762=i9>k1i65f3g694?"6?k0?>:5a16c9b>=n;o81<7*>7c8762=i9>k1==54i2d2>5<#9>h18?94n05b>47<3`9m<7>5$05a>1403g;<m7?=;:k0ac<72-;<n7:=7:l23d<6;21b?hk50;&23g<3:>1e=:o51598m6cc290/=:l54358j41f28?07d=jc;29 41e2=8<7c?8a;35?>o4mk0;6)?8b;613>h6?h0:;65f3dc94?"6?k0?>:5a16c95==<a:o26=4+16`9071<f8=j6<74;h63e?6=,8=i69<8;o34e?7f32c?<44?:%34f?25?2d:;l4>b:9j05>=83.:;o4;269m52g=9j10e9>8:18'52d=<;=0b<9n:0f8?l27>3:1(<9m:504?k70i3;n76g;0483>!70j3>9;6`>7`82b>=n;oo1<7*>7c8762=i9>k1>=54i2d0>5<#9>h18?94n05b>77<3`9n47>5$05a>1403g;<m7<=;:k0a2<72-;<n7:=7:l23d<5;21b8l=50;9a7f3=83;1<7>tH2a7?!7?i39h96a>7983>>{el10;6<4?:1yK7f2<,82j6i64oe594?=zj=>1<7o::00g>40>sA9h86T;5;35d<>2k09m7<8:3:96<<a28=1o7<m:3c96g<a2j0j6<952881<?402k026p*>8`871g=#<10?945+4d871d=#9>>1=:94i554>5<#9>h18:64n05b>5=<a===6=4+16`902><f8=j6<54i556>5<#9>h18:64n05b>7=<a==?6=4+16`902><f8=j6>54i550>5<#9>h18:64n05b>1=<a==96=4+16`902><f8=j6854i552>5<#9>h18:64n05b>3=<a==;6=4+16`902><f8=j6:54i54e>5<#9>h18:64n05b>==<a=<n6=4+16`902><f8=j6454i57f>5<<a=h:6=44i5`7>5<<g=h<6=44i54`>5<#9>h18;j4n05b>5=<a=<i6=4+16`903b<f8=j6<54i54b>5<#9>h18;j4n05b>7=<a=<26=4+16`903b<f8=j6>54i54;>5<#9>h18;j4n05b>1=<a=<<6=4+16`903b<f8=j6854i545>5<#9>h18;j4n05b>3=<a=<>6=4+16`903b<f8=j6:54i547>5<#9>h18;j4n05b>==<a=<86=4+16`903b<f8=j6454i5`3>5<<g=<:6=44i5:1>5<#9>h185=4n05b>5=<a=2:6=4+16`90=5<f8=j6<54i5:3>5<#9>h185=4n05b>7=<a==m6=4+16`90=5<f8=j6>54i55f>5<#9>h185=4n05b>1=<a==o6=4+16`90=5<f8=j6854i55`>5<#9>h185=4n05b>3=<a==i6=4+16`90=5<f8=j6:54i55b>5<#9>h185=4n05b>==<a==26=4+16`90=5<f8=j6454o2f;>5<<g:o?6=4+16`97`3<f8=j6=54o2g0>5<#9>h1?h;4n05b>4=<g:o96=4+16`97`3<f8=j6?54o2g2>5<#9>h1?h;4n05b>6=<g:o;6=4+16`97`3<f8=j6954o2fe>5<#9>h1?h;4n05b>0=<g:nn6=4+16`97`3<f8=j6;54o2fg>5<#9>h1?h;4n05b>2=<g:nh6=4+16`97`3<f8=j6554o5:7>5<<a=i?6=44i5:g>5<#9>h185k4n05b>5=<a=2h6=4+16`90=c<f8=j6<54i5:a>5<#9>h185k4n05b>7=<a=2j6=4+16`90=c<f8=j6>54i5::>5<#9>h185k4n05b>1=<a=236=4+16`90=c<f8=j6854i5:4>5<#9>h185k4n05b>3=<a=2=6=4+16`90=c<f8=j6:54i5:6>5<#9>h185k4n05b>==<g=?h6=44o575>5<<a=h26=44i2fb>5<<a=3<6=4+16`90<><f8=j6=54i5;5>5<#9>h18464n05b>4=<a=3>6=4+16`90<><f8=j6?54i5;7>5<#9>h18464n05b>6=<a=386=4+16`90<><f8=j6954i5;1>5<#9>h18464n05b>0=<a=3:6=4+16`90<><f8=j6;54i5;3>5<#9>h18464n05b>2=<a=2m6=4+16`90<><f8=j6554i5c2>5<#9>h18l<4n05b>5=<a=k;6=4+16`90d4<f8=j6<54i5;e>5<#9>h18l<4n05b>7=<a=3n6=4+16`90d4<f8=j6>54i5;g>5<#9>h18l<4n05b>1=<a=3h6=4+16`90d4<f8=j6854i5;a>5<#9>h18l<4n05b>3=<a=3j6=4+16`90d4<f8=j6:54i5;:>5<#9>h18l<4n05b>==<g:n<6=44i57e>5<<a:ni6=44i5a6>5<<g=h86=44o5`;>5<<a=h96=44o51:>5<#9>h189o4n05b>5=<g=936=4+16`901g<f8=j6<54o514>5<#9>h189o4n05b>7=<g=9=6=4+16`901g<f8=j6>54o516>5<#9>h189o4n05b>1=<g=9?6=4+16`901g<f8=j6854o510>5<#9>h189o4n05b>3=<g=996=4+16`901g<f8=j6:54o562>5<#9>h189o4n05b>==<g=>;6=4+16`901g<f8=j6454o51e>5<#9>h189o4n05b>d=<g=9n6=4+16`901g<f8=j6o54o51g>5<#9>h189o4n05b>f=<g=9h6=4+16`901g<f8=j6i54o51a>5<#9>h189o4n05b>`=<g=9j6=4+16`901g<f8=j6k54o512>5<#9>h189o4n05b>46<3f>8<7>5$05a>12f3g;<m7?>;:k741<72-;<n7:=7:l23d<732c?<>4?:%34f?25?2d:;l4>;:k747<72-;<n7:=7:l23d<532c?<<4?:%34f?25?2d:;l4<;:k745<72-;<n7:=7:l23d<332c8jk4?:%34f?25?2d:;l4:;:k0ba<72-;<n7:=7:l23d<132c8jn4?:%34f?25?2d:;l48;:k0bg<72-;<n7:=7:l23d<?32c8jl4?:%34f?25?2d:;l46;:k0b<<72-;<n7:=7:l23d<f32c8j54?:%34f?25?2d:;l4m;:k0b2<72-;<n7:=7:l23d<d32c8j;4?:%34f?25?2d:;l4k;:k0b0<72-;<n7:=7:l23d<b32c8j94?:%34f?25?2d:;l4i;:k0b7<72-;<n7:=7:l23d<6821b?k?50;&23g<3:>1e=:o51098m6`7290/=:l54358j41f28807d=jf;29 41e2=8<7c?8a;30?>o4ml0;6)?8b;613>h6?h0:865f3df94?"6?k0?>:5a16c950=<a:oh6=4+16`9071<f8=j6<84;h1ff?6=,8=i69<8;o34e?7032c8il4?:%34f?25?2d:;l4>8:9j7`?=83.:;o4;269m52g=9010e9>n:18'52d=<;=0b<9n:0c8?l2713:1(<9m:504?k70i3;i76g;0983>!70j3>9;6`>7`82g>=n<9=1<7*>7c8762=i9>k1=i54i525>5<#9>h18?94n05b>4c<3`>;97>5$05a>1403g;<m7?i;:k0b`<72-;<n7:=7:l23d<5821b?k=50;&23g<3:>1e=:o52098m6c?290/=:l54358j41f2;807d=j7;29 41e2=8<7c?8a;00?>o4l00;66a;ae83>!70j3>jj6`>7`83?>i3ij0;6)?8b;6bb>h6?h0:76a;ac83>!70j3>jj6`>7`81?>i3ih0;6)?8b;6bb>h6?h0876a;a883>!70j3>jj6`>7`87?>i3i10;6)?8b;6bb>h6?h0>76a;a683>!70j3>jj6`>7`85?>i3i?0;6)?8b;6bb>h6?h0<76a;a483>!70j3>jj6`>7`8;?>i3i=0;6)?8b;6bb>h6?h0276a;c383>!70j3>h?6`>7`83?>i3k80;6)?8b;6`7>h6?h0:76a;c183>!70j3>h?6`>7`81?>i3jo0;6)?8b;6`7>h6?h0876a;bd83>!70j3>h?6`>7`87?>i3jm0;6)?8b;6`7>h6?h0>76a;bb83>!70j3>h?6`>7`85?>i3jk0;6)?8b;6`7>h6?h0<76a;b`83>!70j3>h?6`>7`8;?>i3>;0;66g;5e83>>i4m?0;66g;a283>>i3j?0;66l<d183>4<729q/=5o5d99K7f`<@:i?7bj8:188yg5c93:1=7>50z&2<d<4k<1C?nh4H2a7?j7003:17pl=9c83>1<729q/=5o5d59K7f`<@:i?7)k::79j03<722c><7>5;h34g?6=3f;<h7>5;|`052<72=0;6=u+19c9`7=O;jl0D>m;;%g6>7=n<?0;66g;c;29?l372900c<9k:188yg56>3:187>50z&2<d<c:2B8ok5G3b68 `3=:2c?:7>5;h6`>5<<a<:1<75`16f94?=zj:h:6=4<:183!7?i3n:7E=lf:J0g1=O<:1/=>?54c78 `3=:2c?:7>5;h73>5<<g8=o6=44}c1ag?6=;3:1<v*>8`8g5>N4ko1C?n:4H518 4562=h>7)k::39j03<722c><7>5;n34`?6=3th8n=4?:283>5}#91k1h<5G3bd8L6e33A>87)?<1;6a1>"b=380e9850;9j15<722e:;i4?::a7gg=83?1<7>t$0:b>a3<@:im7E=l4:J77>"6;80?n85f4783>>o3?3:17d;?:188m41d2900c<9k:188yg5ej3:1?7>50z&2<d<c92B8ok5G3b68L15<,89:69l:;%g6>7=n<?0;66g:0;29?j70l3:17pl<ag83>0<729q/=5o5d49K7f`<@:i?7E:<;%305?2e=2c?:7>5;h64>5<<a<:1<75f16a94?=h9>n1<75rb2`:>5<3290;w)?7a;f7?M5dn2B8o95+e485?l212900e8>50;9j52e=831d=:j50;9~f6d?290?6=4?{%3;e?b33A9hj6F<c59'a0<13`>=6=44i4294?=n9>i1<75`16f94?=zj:h<6=4;:183!7?i3n?7E=lf:J0g1=#m<0=7d:9:188m06=831b=:m50;9l52b=831vn>m=:187>5<7s-;3m7j;;I1`b>N4k=1/i849;h65>5<<a<:1<75f16a94?=h9>n1<75rb2a2>5<3290;w)?7a;f7?M5dn2B8o95+e485?l212900e8>50;9j52e=831d=:j50;9~f4gc290?6=4?{%3;e?b53A9hj6F<c59'a0<53`>=6=44i5a94?=n=90;66a>7e83>>{e9hi1<7:50;2x 4>f2m80D>mi;I1`0>"b=380e9850;9j0f<722c><7>5;n34`?6=3th:mo4?:583>5}#91k1h?5G3bd8L6e33-o>6?5f4783>>o3k3:17d;?:188k41c2900qo?na;290?6=8r.:4l4k2:J0gc=O;j>0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0c:>5<3290;w)?7a;f1?M5dn2B8o95+e481?l212900e9m50;9j15<722e:;i4?::a5d>=83>1<7>t$0:b>a4<@:im7E=l4:&f1?4<a=<1<75f4b83>>o283:17b?8d;29?xd6i>0;694?:1y'5=g=l;1C?nh4H2a7?!c22;1b8;4?::k7g?6=3`?;6=44o05g>5<<uk;j:7>54;294~"60h0o>6F<cg9K7f2<,l?1>6g;6;29?l2d2900e8>50;9l52b=831vn<o::187>5<7s-;3m7j=;I1`b>N4k=1/i84=;h65>5<<a=i1<75f5183>>i6?m0;66sm20694?2=83:p(<6n:e08L6ea3A9h86*j5;08m10=831b8n4?::k64?6=3f;<h7>5;|`156<72=0;6=u+19c9`7=O;jl0D>m;;%g6>7=n<?0;66g;c;29?l372900c<9k:188yg46:3:187>50z&2<d<c:2B8ok5G3b68 `3=:2c?:7>5;h6`>5<<a<:1<75`16f94?=zj;;:6=4;:183!7?i3n97E=lf:J0g1=#m<097d:9:188m1e=831b9=4?::m23a<722wi><>50;694?6|,82j6i<4H2ae?M5d<2.n97<4i5494?=n<j0;66g:0;29?j70l3:17pl=0g83>1<729q/=5o5d39K7f`<@:i?7)k::39j03<722c?o7>5;h73>5<<g8=o6=44}c03a?6=<3:1<v*>8`8g6>N4ko1C?n:4$d796>o3>3:17d:l:188m06=831d=:j50;9~f76c290?6=4?{%3;e?b53A9hj6F<c59'a0<53`>=6=44i5a94?=n=90;66a>7e83>>{e:9i1<7:50;2x 4>f2m80D>mi;I1`0>"b=380e9850;9j0f<722c><7>5;n34`?6=3th99n4?:583>5}#91k1h?5G3bd8L6e33-o>6?5f4783>>o3k3:17d;?:188k41c2900qo<:b;290?6=8r.:4l4k2:J0gc=O;j>0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb37b>5<3290;w)?7a;f1?M5dn2B8o95+e481?l212900e9m50;9j15<722e:;i4?::a60?=83>1<7>t$0:b>a4<@:im7E=l4:&f1?4<a=<1<75f4b83>>o283:17b?8d;29?xd5=10;694?:1y'5=g=l;1C?nh4H2a7?!c22;1b8;4?::k7g?6=3`?;6=44o05g>5<<uk8>;7>54;294~"60h0o>6F<cg9K7f2<,l?1>6g;6;29?l2d2900e8>50;9l52b=831vn?;9:187>5<7s-;3m7j=;I1`b>N4k=1/i84=;h65>5<<a=i1<75f5183>>i6?m0;66sm24794?2=83:p(<6n:e08L6ea3A9h86*j5;08m10=831b8n4?::k64?6=3f;<h7>5;|`111<72=0;6=u+19c9`7=O;jl0D>m;;%g6>7=n<?0;66g;c;29?l372900c<9k:188yg7a13:187>50z&2<d<c:2B8ok5G3b68 `3=:2c?:7>5;h6`>5<<a<:1<75`16f94?=zj8l36=4;:183!7?i3n97E=lf:J0g1=#m<097d:9:188m1e=831b9=4?::m23a<722wi=k950;694?6|,82j6i<4H2ae?M5d<2.n97<4i5494?=n<j0;66g:0;29?j70l3:17pl>f783>1<729q/=5o5d39K7f`<@:i?7)k::39j03<722c?o7>5;h73>5<<g8=o6=44}c3e1?6=<3:1<v*>8`8g6>N4ko1C?n:4$d796>o3>3:17d:l:188m06=831d=:j50;9~f4`3290?6=4?{%3;e?b53A9hj6F<c59'a0<53`>=6=44i5a94?=n=90;66a>7e83>>{e9o91<7:50;2x 4>f2m80D>mi;I1`0>"b=380e9850;9j0f<722c><7>5;n34`?6=3th:j?4?:583>5}#91k1h?5G3bd8L6e33-o>6?5f4783>>o3k3:17d;?:188k41c2900qo?i1;290?6=8r.:4l4k2:J0gc=O;j>0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb36b>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb36:>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb36;>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb364>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb365>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb366>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb367>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb360>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb361>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0g4>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0g5>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0g6>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0g7>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0g0>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0g1>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0g2>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0g3>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0fe>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0ff>5<3290;w)?7a;f1?M5dn2B8o95G429'567=<k?0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb0f0>5<3290;w)?7a;f1?M5dn2B8o95+e481?l212900e9m50;9j15<722e:;i4?::a5a4=83>1<7>t$0:b>a4<@:im7E=l4:&f1?4<a=<1<75f4b83>>o283:17b?8d;29?xd6l80;694?:1y'5=g=l;1C?nh4H2a7?!c22;1b8;4?::k7g?6=3`?;6=44o05g>5<<uk;o<7>54;294~"60h0o>6F<cg9K7f2<,l?1>6g;6;29?l2d2900e8>50;9l52b=831vn<mi:187>5<7s-;3m7j=;I1`b>N4k=1/i84=;h65>5<<a=i1<75f5183>>i6?m0;66sm1bg94?2=83:p(<6n:e08L6ea3A9h86*j5;08m10=831b8n4?::k64?6=3f;<h7>5;|`2ga<72=0;6=u+19c9`7=O;jl0D>m;;%g6>7=n<?0;66g;c;29?l372900c<9k:188yg7dk3:187>50z&2<d<c:2B8ok5G3b68 `3=:2c?:7>5;h6`>5<<a<:1<75`16f94?=zj8ii6=4;:183!7?i3n97E=lf:J0g1=#m<097d:9:188m1e=831b9=4?::m23a<722wi=no50;694?6|,82j6i<4H2ae?M5d<2.n97<4i5494?=n<j0;66g:0;29?j70l3:17pl=3983>1<729q/=5o5d39K7f`<@:i?7)k::39j03<722c?o7>5;h73>5<<g8=o6=44}c003?6=<3:1<v*>8`8g6>N4ko1C?n:4$d796>o3>3:17d:l:188m06=831d=:j50;9~f751290?6=4?{%3;e?b53A9hj6F<c59'a0<53`>=6=44i5a94?=n=90;66a>7e83>>{e::?1<7:50;2x 4>f2m80D>mi;I1`0>"b=380e9850;9j0f<722c><7>5;n34`?6=3th9?94?:583>5}#91k1h?5G3bd8L6e33-o>6?5f4783>>o3k3:17d;?:188k41c2900qo<<3;290?6=8r.:4l4k2:J0gc=O;j>0(h;52:k72?6=3`>h6=44i4294?=h9>n1<75rb311>5<3290;w)?7a;f1?M5dn2B8o95+e481?l212900e9m50;9j15<722e:;i4?::a667=83>1<7>t$0:b>a4<@:im7E=l4:&f1?4<a=<1<75f4b83>>o283:17b?8d;29?xd5;90;694?:1y'5=g=l;1C?nh4H2a7?!c22;1b8;4?::k7g?6=3`?;6=44o05g>5<<uk8o47>55;294~"60h0o?6F<cg9K7f2<,l?1>6g;6;29?l202900e9m50;9j15<722e:;i4?::a6a1=83?1<7>t$0:b>a5<@:im7E=l4:&f1?4<a=<1<75f4683>>o3k3:17d;?:188k41c2900qo<k5;291?6=8r.:4l4k3:J0gc=O;j>0(h;52:k72?6=3`><6=44i5a94?=n=90;66a>7e83>>{e:m>1<7;50;2x 4>f2m90D>mi;I1`0>"b=380e9850;9j02<722c?o7>5;h73>5<<g8=o6=44}c0g2?6==3:1<v*>8`8g7>N4ko1C?n:4$d796>o3>3:17d:8:188m1e=831b9=4?::m23a<722wi>i=50;794?6|,82j6i=4H2ae?M5d<2.n97<4i5494?=n<>0;66g;c;29?l372900c<9k:188yg4c:3:197>50z&2<d<c;2B8ok5G3b68 `3=:2c?:7>5;h64>5<<a=i1<75f5183>>i6?m0;66sm2e294?3=83:p(<6n:e18L6ea3A9h86*j5;08m10=831b8:4?::k7g?6=3`?;6=44o05g>5<<uk8hj7>55;294~"60h0o96F<cg9K7f2<,l?1:6g;6;29?l202900e8>50;9j52e=831d=:j50;9~f7b6290>6=4?{%3;e?b43A9hj6F<c59'a0<53`>=6=44i5594?=n<j0;66g:0;29?j70l3:17pl=c283>6<729q/=5o53bg8L6ea3A9h86g;9;29?l7503:17b?86;29?xd5k;0;6>4?:1y'5=g=;jo0D>mi;I1`0>o313:17d?=8;29?j70>3:17pl=b983>1<729q/=5o51208L6ea3A9h86g;9;29?l352900e<6<:188k4112900qo<l1;297?6=8r.:4l4<cd9K7f`<@:i?7d:6:188m44?2900c<99:188yg4e>3:187>50z&2<d<6;;1C?nh4H2a7?l2>2900e8<50;9j5=5=831d=:850;9~f7e729086=4?{%3;e?5dm2B8ok5G3b68m1?=831b=?650;9l520=831vn?l;:187>5<7s-;3m7?<2:J0gc=O;j>0e9750;9j17<722c:4>4?::m233<722wi>oh50;194?6|,82j6>mj;I1`b>N4k=1b844?::k26=<722e:;;4?::a6g4=83>1<7>t$0:b>4553A9hj6F<c59j0<<722c>>7>5;h3;7?6=3f;<:7>5;|`1f`<72:0;6=u+19c97fc<@:im7E=l4:k7=?6=3`;947>5;n342?6=3th9n=4?:583>5}#91k1=><4H2ae?M5d<2c?57>5;h71>5<<a8286=44o055>5<<uk8ih7>53;294~"60h08oh5G3bd8L6e33`>26=44i00;>5<<g8==6=44}c0ba?6=<3:1<v*>8`8277=O;jl0D>m;;h6:>5<<a<81<75f19194?=h9><1<75rb3``>5<4290;w)?7a;1`a>N4ko1C?n:4i5;94?=n9;21<75`16494?=zj;kh6=4;:183!7?i3;8>6F<cg9K7f2<a=31<75f5383>>o60:0;66a>7783>>{e:kh1<7=50;2x 4>f2:in7E=lf:J0g1=n<00;66g>2983>>i6??0;66sm2`c94?2=83:p(<6n:011?M5dn2B8o95f4883>>o2:3:17d?73;29?j70>3:17pl=b`83>6<729q/=5o53bg8L6ea3A9h86g;9;29?l7503:17b?86;29?xd5i10;694?:1y'5=g=9:80D>mi;I1`0>o313:17d;=:188m4>42900c<99:188yg4bk3:197>50z&2<d<c;2B8ok5G3b68 `3=:2c?:7>5;h64>5<<a=i1<75f5183>>i6?m0;66sm2d`94?3=83:p(<6n:e18L6ea3A9h86*j5;08m10=831b8:4?::k7g?6=3`?;6=44o05g>5<<uk8nm7>55;294~"60h0o?6F<cg9K7f2<,l?1>6g;6;29?l202900e9m50;9j15<722e:;i4?::a6`?=83?1<7>t$0:b>a5<@:im7E=l4:&f1?4<a=<1<75f4683>>o3k3:17d;?:188k41c2900qo<j8;291?6=8r.:4l4k3:J0gc=O;j>0(h;52:k72?6=3`><6=44i5a94?=n=90;66a>7e83>>{e:l=1<7;50;2x 4>f2m90D>mi;I1`0>"b=380e9850;9j02<722c?o7>5;h73>5<<g8=o6=44}c0f2?6==3:1<v*>8`8g7>N4ko1C?n:4$d796>o3>3:17d:8:188m1e=831b9=4?::m23a<722wi>h;50;794?6|,82j6i=4H2ae?M5d<2.n97<4i5494?=n<>0;66g;c;29?l372900c<9k:188yg4b<3:197>50z&2<d<c;2B8ok5G3b68 `3=:2c?:7>5;h64>5<<a=i1<75f5183>>i6?m0;66sm2d194?3=83:p(<6n:e18L6ea3A9h86*j5;08m10=831b8:4?::k7g?6=3`?;6=44o05g>5<<uk8=j7>54;294~"60h0o86F<cg9K7f2<,l?1:6g;6;29?l372900e<9l:188k41c2900qo<80;290?6=8r.:4l4k4:J0gc=O;j>0(h;56:k72?6=3`?;6=44i05`>5<<g8=o6=44}c05e?6=<3:1<v*>8`8g6>N4ko1C?n:4$d796>o3>3:17d:l:188m06=831d=:j50;9~f70>290?6=4?{%3;e?b53A9hj6F<c59'a0<53`>=6=44i5a94?=n=90;66a>7e83>>{e:1o1<7:50;2x 4>f28997E=lf:J0g1=n<00;66g:2;29?l7?;3:17b?86;29?xd50m0;694?:1y'5=g=9:80D>mi;I1`0>o313:17d;=:188m4>42900c<99:188yg4?k3:187>50z&2<d<6;;1C?nh4H2a7?l2>2900e8<50;9j5=5=831d=:850;9~f7>e290?6=4?{%3;e?74:2B8ok5G3b68m1?=831b9?4?::k2<6<722e:;;4?::a6=g=83>1<7>t$0:b>4553A9hj6F<c59j0<<722c>>7>5;h3;7?6=3f;<:7>5;|`13g<72=0;6=u+19c9564<@:im7E=l4:k7=?6=3`?96=44i0:0>5<<g8==6=44}c04e?6=<3:1<v*>8`8277=O;jl0D>m;;h6:>5<<a<81<75f19194?=h9><1<75rb35:>5<3290;w)?7a;306>N4ko1C?n:4i5;94?=n=;0;66g>8283>>i6??0;66sm26:94?2=83:p(<6n:011?M5dn2B8o95f4883>>o2:3:17d?73;29?j70>3:17pl=7683>1<729q/=5o51208L6ea3A9h86g;9;29?l352900e<6<:188k4112900qo=?9;290?6=8r.:4l4>339K7f`<@:i?7d:6:188m04=831b=5=50;9l520=831vn>>7:187>5<7s-;3m7?<2:J0gc=O;j>0e9750;9j17<722c:4>4?::m233<722wi?=950;694?6|,82j6<==;I1`b>N4k=1b844?::k66?6=3`;3?7>5;n342?6=3th8<;4?:583>5}#91k1=><4H2ae?M5d<2c?57>5;h71>5<<a8286=44o055>5<<uk9;97>54;294~"60h0:??5G3bd8L6e33`>26=44i4094?=n9191<75`16494?=zj;l=6=4;:183!7?i3;8>6F<cg9K7f2<a=31<75f5383>>o60:0;66a>7783>>{e:o?1<7:50;2x 4>f28997E=lf:J0g1=n<00;66g:2;29?l7?;3:17b?86;29?xd5n=0;694?:1y'5=g=9:80D>mi;I1`0>o313:17d;=:188m4>42900c<99:188yg4a;3:187>50z&2<d<6;;1C?nh4H2a7?l2>2900e8<50;9j5=5=831d=:850;9~f7`5290?6=4?{%3;e?74:2B8ok5G3b68m1?=831b9?4?::k2<6<722e:;;4?::a70d=83?1<7>t$0:b>a5<@:im7E=l4:&f1?4<a=<1<75f4683>>o3k3:17d;?:188k41c2900qo=:9;291?6=8r.:4l4k5:J0gc=O;j>0(h;56:k72?6=3`><6=44i4294?=n9>i1<75`16f94?=zj:?j6=4::183!7?i3n87E=lf:J0g1=#m<097d:9:188m11=831b8n4?::k64?6=3f;<h7>5;|`01f<72<0;6=u+19c9`6=O;jl0D>m;;%g6>7=n<?0;66g;7;29?l2d2900e8>50;9l52b=831vn>;k:186>5<7s-;3m7j<;I1`b>N4k=1/i84=;h65>5<<a==1<75f4b83>>o283:17b?8d;29?xd4=l0;684?:1y'5=g=l:1C?nh4H2a7?!c22;1b8;4?::k73?6=3`>h6=44i4294?=h9>n1<75rb27e>5<2290;w)?7a;f0?M5dn2B8o95+e481?l212900e9950;9j0f<722c><7>5;n34`?6=3th8:=4?:483>5}#91k1h>5G3bd8L6e33-o>6?5f4783>>o3?3:17d:l:188m06=831d=:j50;9~f606290>6=4?{%3;e?b43A9hj6F<c59'a0<53`>=6=44i5594?=n<j0;66g:0;29?j70l3:17pl<4g83>0<729q/=5o5d29K7f`<@:i?7)k::39j03<722c?;7>5;h6`>5<<a<:1<75`16f94?=zj:>n6=4::183!7?i3n87E=lf:J0g1=#m<097d:9:188m11=831b8n4?::k64?6=3f;<h7>5;|`00f<72<0;6=u+19c9`6=O;jl0D>m;;%g6>7=n<?0;66g;7;29?l2d2900e8>50;9l52b=831vn>:m:186>5<7s-;3m7j<;I1`b>N4k=1/i84=;h65>5<<a==1<75f4b83>>o283:17b?8d;29?xd4<m0;684?:1y'5=g=l:1C?nh4H2a7?!c22;1b8;4?::k73?6=3`>h6=44i4294?=h9>n1<75rb26b>5<2290;w)?7a;f0?M5dn2B8o95+e481?l212900e9950;9j0f<722c><7>5;n34`?6=3th8844?:483>5}#91k1h>5G3bd8L6e33-o>6?5f4783>>o3?3:17d:l:188m06=831d=:j50;9~f620290>6=4?{%3;e?b43A9hj6F<c59'a0<53`>=6=44i5594?=n<j0;66g:0;29?j70l3:17pl<4983>0<729q/=5o5d49K7f`<@:i?7)k::79j03<722c?;7>5;h73>5<<a8=h6=44o05g>5<<uk98o7>53;294~"60h08oh5G3bd8L6e33`>26=44i00;>5<<g8==6=44}c10f?6=;3:1<v*>8`80g`=O;jl0D>m;;h6:>5<<a8836=44o055>5<<uk98>7>54;294~"60h0:??5G3bd8L6e33`>26=44i4094?=n9191<75`16494?=zj:9j6=4<:183!7?i39hi6F<cg9K7f2<a=31<75f13:94?=h9><1<75rb213>5<3290;w)?7a;306>N4ko1C?n:4i5;94?=n=;0;66g>8283>>i6??0;66sm32;94?5=83:p(<6n:2af?M5dn2B8o95f4883>>o6:10;66a>7783>>{e;;o1<7:50;2x 4>f28997E=lf:J0g1=n<00;66g:2;29?l7?;3:17b?86;29?xd4;10;6>4?:1y'5=g=;jo0D>mi;I1`0>o313:17d?=8;29?j70>3:17pl<2b83>1<729q/=5o51208L6ea3A9h86g;9;29?l352900e<6<:188k4112900qo=<7;297?6=8r.:4l4<cd9K7f`<@:i?7d:6:188m44?2900c<99:188yg55i3:187>50z&2<d<6;;1C?nh4H2a7?l2>2900e8<50;9j5=5=831d=:850;9~f65129086=4?{%3;e?5dm2B8ok5G3b68m1?=831b=?650;9l520=831vn><7:187>5<7s-;3m7?<2:J0gc=O;j>0e9750;9j17<722c:4>4?::m233<722wi?>;50;194?6|,82j6>mj;I1`b>N4k=1b844?::k26=<722e:;;4?::a770=83>1<7>t$0:b>4553A9hj6F<c59j0<<722c>>7>5;h3;7?6=3f;<:7>5;|`071<72:0;6=u+19c97fc<@:im7E=l4:k7=?6=3`;947>5;n342?6=3th8>94?:583>5}#91k1=><4H2ae?M5d<2c?57>5;h71>5<<a8286=44o055>5<<uk9<?7>55;294~"60h0o?6F<cg9K7f2<,l?1>6g;6;29?l202900e9m50;9j15<722e:;i4?::a724=83?1<7>t$0:b>a5<@:im7E=l4:&f1?4<a=<1<75f4683>>o3k3:17d;?:188k41c2900qo=81;291?6=8r.:4l4k3:J0gc=O;j>0(h;52:k72?6=3`><6=44i5a94?=n=90;66a>7e83>>{e;>:1<7;50;2x 4>f2m90D>mi;I1`0>"b=380e9850;9j02<722c?o7>5;h73>5<<g8=o6=44}c15b?6==3:1<v*>8`8g7>N4ko1C?n:4$d796>o3>3:17d:8:188m1e=831b9=4?::m23a<722wi?;k50;794?6|,82j6i=4H2ae?M5d<2.n97<4i5494?=n<>0;66g;c;29?l372900c<9k:188yg51l3:197>50z&2<d<c;2B8ok5G3b68 `3=:2c?:7>5;h64>5<<a=i1<75f5183>>i6?m0;66sm37a94?3=83:p(<6n:e18L6ea3A9h86*j5;08m10=831b8:4?::k7g?6=3`?;6=44o05g>5<<uk9=n7>55;294~"60h0o?6F<cg9K7f2<,l?1>6g;6;29?l202900e9m50;9j15<722e:;i4?::a7<6=83?1<7>t$0:b>a0<@:im7E=l4:&f1?4<a=<1<75f4683>>o283:17d?8e;29?j70l3:17pl<8g83>0<729q/=5o5d79K7f`<@:i?7)k::39j03<722c?;7>5;h73>5<<a8=n6=44o05g>5<<uk93i7>55;294~"60h0o:6F<cg9K7f2<,l?1>6g;6;29?l202900e8>50;9j52c=831d=:j50;9~f6>c290>6=4?{%3;e?b13A9hj6F<c59'a0<53`>=6=44i5594?=n=90;66g>7d83>>i6?m0;66sm39a94?3=83:p(<6n:e48L6ea3A9h86*j5;08m10=831b8:4?::k64?6=3`;<i7>5;n34`?6=3th84o4?:483>5}#91k1h;5G3bd8L6e33-o>6?5f4783>>o3?3:17d;?:188m41b2900c<9k:188yg5?i3:197>50z&2<d<c>2B8ok5G3b68 `3=:2c?:7>5;h64>5<<a<:1<75f16g94?=h9>n1<75rb2::>5<2290;w)?7a;f5?M5dn2B8o95+e481?l212900e9950;9j15<722c:;h4?::m23a<722wi?4650;794?6|,82j6i84H2ae?M5d<2.n97<4i5494?=n<>0;66g:0;29?l70m3:17b?8d;29?xd41>0;684?:1y'5=g=l?1C?nh4H2a7?!c22;1b8;4?::k73?6=3`?;6=44i05f>5<<g8=o6=44}c1:2?6==3:1<v*>8`8g2>N4ko1C?n:4$d796>o3>3:17d:8:188m06=831b=:k50;9l52b=831vn>7::186>5<7s-;3m7j9;I1`b>N4k=1/i84=;h65>5<<a==1<75f5183>>o6?l0;66a>7e83>>{e;0>1<7;50;2x 4>f2m<0D>mi;I1`0>"b=380e9850;9j02<722c><7>5;h34a?6=3f;<h7>5;|`0=6<72<0;6=u+19c9`3=O;jl0D>m;;%g6>7=n<?0;66g;7;29?l372900e<9j:188k41c2900qo=62;291?6=8r.:4l4k6:J0gc=O;j>0(h;52:k72?6=3`><6=44i4294?=n9>o1<75`16f94?=zj:3:6=4::183!7?i3n=7E=lf:J0g1=#m<097d:9:188m11=831b9=4?::k23`<722e:;i4?::a7=>=83?1<7>t$0:b>a0<@:im7E=l4:&f1?4<a=<1<75f4683>>o283:17d?8e;29?j70l3:17pl<8683>0<729q/=5o5d79K7f`<@:i?7)k::39j03<722c?;7>5;h73>5<<a8=n6=44o05g>5<<uk9ii7>53;294~"60h0:>i5G3bd8L6e33-o>6<74ie;94?=nlh0;66a>7783>>{e;k91<7=50;2x 4>f288o7E=lf:J0g1=#m<0:56gk9;29?lbf2900c<99:188yg46>3:1?7>50z&2<d<6:m1C?nh4H2a7?!c228n0ei750;9j`d<722e:;;4?::a5d`=8391<7>t$0:b>44c3A9hj6F<c59'a0<6l2co57>5;hfb>5<<g8==6=44}c3:f?6=;3:1<v*>8`826a=O;jl0D>m;;%g6>4b<am31<75fd`83>>i6??0;66sm18c94?5=83:p(<6n:00g?M5dn2B8o95+e482`>oc13:17djn:188k4112900qo?69;297?6=8r.:4l4>2e9K7f`<@:i?7)k::0f8ma?=831bhl4?::m233<722wi=4650;194?6|,82j6<<k;I1`b>N4k=1/i84>d:kg=?6=3`nj6=44o055>5<<uk;2;7>53;294~"60h0:>i5G3bd8L6e33-o>6<j4ie;94?=nlh0;66a>7783>>{e90<1<7=50;2x 4>f288o7E=lf:J0g1=#m<0:h6gk9;29?lbf2900c<99:188yg7>=3:1?7>50z&2<d<6:m1C?nh4H2a7?!c228n0ei750;9j`d<722e:;;4?::a5<2=8391<7>t$0:b>44c3A9hj6F<c59'a0<6l2co57>5;hfb>5<<g8==6=44}c3:7?6=;3:1<v*>8`826a=O;jl0D>m;;%g6>4b<am31<75fd`83>>i6??0;66sm18094?5=83:p(<6n:00g?M5dn2B8o95+e482`>oc13:17djn:188k4112900qo?61;297?6=8r.:4l4>2e9K7f`<@:i?7)k::0f8ma?=831bhl4?::m233<722wi=4>50;194?6|,82j6<<k;I1`b>N4k=1/i84>d:kg=?6=3`nj6=44o055>5<<uk;3j7>53;294~"60h0:>i5G3bd8L6e33-o>6<j4ie;94?=nlh0;66a>7783>>{e91o1<7=50;2x 4>f288o7E=lf:J0g1=#m<0:h6gk9;29?lbf2900c<99:188yg7?l3:1?7>50z&2<d<6:m1C?nh4H2a7?!c228n0ei750;9j`d<722e:;;4?::a5=e=8391<7>t$0:b>44c3A9hj6F<c59'a0<6l2co57>5;hfb>5<<g8==6=44}c3;f?6=;3:1<v*>8`826a=O;jl0D>m;;%g6>4b<am31<75fd`83>>i6??0;66sm27g94?2=83:p(<6n:00f?M5dn2B8o95+e48``>oc13:17djn:188mad=831d=:850;9~f77?290?6=4?{%3;e?75m2B8ok5G3b68 `3=:=1bh44?::kge?6=3`ni6=44o055>5<<uk;i=7>54;294~"60h0:>h5G3bd8L6e33-o>6?:4ie;94?=nlh0;66gkb;29?j70>3:17pl=6b83>0<729q/=5o513d8L6ea3A9h86*j5;3b?lb>2900eio50;9j`g<722coo7>5;n342?6=3th9=l4?:483>5}#91k1=?h4H2ae?M5d<2.n97?i;hf:>5<<amk1<75fdc83>>ock3:17b?86;29?xd6j:0;684?:1y'5=g=9;l0D>mi;I1`0>"b=3;m7dj6:188mag=831bho4?::kgg?6=3f;<:7>5;|`137<72<0;6=u+19c957`<@:im7E=l4:&f1?463`n26=44iec94?=nlk0;66gkc;29?j70>3:17pl<1`83>6<729q/=5o513f8L6ea3A9h86*j5;33?lb>2900eio50;9l520=831vn?89:187>5<7s-;3m7?=e:J0gc=O;j>0(h;52b9j`<<722com7>5;hfa>5<<g8==6=44}c02g?6=;3:1<v*>8`826a=O;jl0D>m;;%g6>4b<am31<75fd`83>>i6??0;66sm1c794?5=83:p(<6n:00g?M5dn2B8o95+e482`>oc13:17djn:188k4112900qo<>e;290?6=8r.:4l4>2d9K7f`<@:i?7)k::368ma?=831bhl4?::kgf?6=3f;<:7>5;|`2f2<72=0;6=u+19c957c<@:im7E=l4:&f1?433`n26=44iec94?=nlk0;66a>7783>>{e:;:1<7;50;2x 4>f288m7E=lf:J0g1=#m<0:j6gk9;29?lbf2900eil50;9j`f<722e:;;4?::a5g?=83?1<7>t$0:b>44a3A9hj6F<c59'a0<6n2co57>5;hfb>5<<amh1<75fdb83>>i6??0;66sm3`f94?2=83:p(<6n:00f?M5dn2B8o95+e4865>oc13:17djn:188mad=831d=:850;9~f702290>6=4?{%3;e?75n2B8ok5G3b68 `3=9;1bh44?::kge?6=3`ni6=44iea94?=h9><1<75rb230>5<4290;w)?7a;31`>N4ko1C?n:4$d7967=nl00;66gka;29?j70>3:17pl<0183>6<729q/=5o513f8L6ea3A9h86*j5;01?lb>2900eio50;9l520=831vn?77:186>5<7s-;3m7?=f:J0gc=O;j>0(h;5219j`<<722com7>5;hfa>5<<ami1<75`16494?=zj;2>6=4::183!7?i3;9j6F<cg9K7f2<,l?1>>5fd883>>oci3:17djm:188mae=831d=:850;9~f675290>6=4?{%3;e?75n2B8ok5G3b68 `3=::1bh44?::kge?6=3`ni6=44iea94?=h9><1<75rb3de>5<2290;w)?7a;31b>N4ko1C?n:4$d7966=nl00;66gka;29?lbe2900eim50;9l520=831vn?78:186>5<7s-;3m7?=f:J0gc=O;j>0(h;5219j`<<722com7>5;hfa>5<<ami1<75`16494?=zj;2?6=4::183!7?i3;9j6F<cg9K7f2<,l?1>=5fd883>>oci3:17djm:188mae=831d=:850;9~f676290>6=4?{%3;e?75n2B8ok5G3b68 `3=::1bh44?::kge?6=3`ni6=44iea94?=h9><1<75rb3df>5<2290;w)?7a;31b>N4ko1C?n:4$d7966=nl00;66gka;29?lbe2900eim50;9l520=831vn?79:186>5<7s-;3m7?=f:J0gc=O;j>0(h;5219j`<<722com7>5;hfa>5<<ami1<75`16494?=zj;286=4::183!7?i3;9j6F<cg9K7f2<,l?1>=5fd883>>oci3:17djm:188mae=831d=:850;9~f677290>6=4?{%3;e?75n2B8ok5G3b68 `3=::1bh44?::kge?6=3`ni6=44iea94?=h9><1<75rb3dg>5<2290;w)?7a;31b>N4ko1C?n:4$d7966=nl00;66gka;29?lbe2900eim50;9l520=831vn?7::186>5<7s-;3m7?=f:J0gc=O;j>0(h;5219j`<<722com7>5;hfa>5<<ami1<75`16494?=zj;296=4::183!7?i3;9j6F<cg9K7f2<,l?1>=5fd883>>oci3:17djm:188mae=831d=:850;9~f7?c290?6=4?{%3;e?75m2B8ok5G3b68 `3=ko1bh44?::kge?6=3`ni6=44o055>5<<uk8287>54;294~"60h0:>h5G3bd8L6e33-o>6<?4ie;94?=nlh0;66gkb;29?j70>3:17pl=8083>1<729q/=5o513g8L6ea3A9h86*j5;32?lb>2900eio50;9j`g<722e:;;4?::a74?=83?1<7>t$0:b>44a3A9hj6F<c59'a0<dm2co57>5;hfb>5<<amh1<75fdb83>>i6??0;66sm31d94?3=83:p(<6n:00e?M5dn2B8o95+e4817>oc13:17djn:188mad=831bhn4?::m233<722wi>km50;794?6|,82j6<<i;I1`b>N4k=1/i84=3:kg=?6=3`nj6=44ie`94?=nlj0;66a>7783>>{e:;91<7=50;2x 4>f288o7E=lf:J0g1=#m<09>6gk9;29?lbf2900c<99:188yg7ek3:1?7>50z&2<d<6:m1C?nh4H2a7?!c22;80ei750;9j`d<722e:;;4?::a670=83>1<7>t$0:b>44b3A9hj6F<c59'a0<6m2co57>5;hfb>5<<amh1<75`16494?=zj8hm6=4;:183!7?i3;9i6F<cg9K7f2<,l?1=h5fd883>>oci3:17djm:188k4112900qo<m9;296?6=8r.:4l4>2b9K7f`<@:i?7)k::028ma?=831d=:850;9~f7d029096=4?{%3;e?75k2B8ok5G3b68 `3=991bh44?::m233<722wi>o;50;094?6|,82j6<<l;I1`b>N4k=1/i84>0:kg=?6=3f;<:7>5;|`1f6<72;0;6=u+19c957e<@:im7E=l4:&f1?773`n26=44o055>5<<uk8i=7>52;294~"60h0:>n5G3bd8L6e33-o>6<>4ie;94?=h9><1<75rb3ce>5<5290;w)?7a;31g>N4ko1C?n:4$d7955=nl00;66a>7783>>{e:hn1<7<50;2x 4>f288h7E=lf:J0g1=#m<0:<6gk9;29?j70>3:17pl=ac83>7<729q/=5o513a8L6ea3A9h86*j5;33?lb>2900c<99:188yg4f13:1>7>50z&2<d<6:j1C?nh4H2a7?!c228:0ei750;9l520=831vn>=<:181>5<7s-;3m7?=c:J0gc=O;j>0(h;5119j`<<722e:;;4?::a767=8381<7>t$0:b>44d3A9hj6F<c59'a0<682co57>5;n342?6=3th8>k4?:383>5}#91k1=?m4H2ae?M5d<2.n97??;hf:>5<<g8==6=44}c11`?6=:3:1<v*>8`826f=O;jl0D>m;;%g6>46<am31<75`16494?=zj:8i6=4=:183!7?i3;9o6F<cg9K7f2<,l?1==5fd883>>i6??0;66sm33;94?4=83:p(<6n:00`?M5dn2B8o95+e4824>oc13:17b?86;29?xd4:>0;6?4?:1y'5=g=9;i0D>mi;I1`0>"b=3;;7dj6:188k4112900qo==5;296?6=8r.:4l4>2b9K7f`<@:i?7)k::028ma?=831d=:850;9~f7e329096=4?{%3;e?75k2B8ok5G3b68 `3=991bh44?::m233<722wi?>j50;094?6|,82j6<<l;I1`b>N4k=1/i84>0:kg=?6=3f;<:7>5;|`167<72?0;6=u+19c9566<@:im7E=l4:&f1?423`n26=44iec94?=nlk0;66gkc;29?j7513:17b?86;29?xd6jk0;6;4?:1y'5=g=9::0D>mi;I1`0>"b=38>7dj6:188mag=831bho4?::kgg?6=3f;957>5;n342?6=3th8mo4?:9594?6|@:i?7)?7a;34b>\3=3kp47<9:e821?7428h1i7?9:0695f<z,88<695+de86?!bb2<1/hk4:;%g3>0=#m80>7)k=:49'a6<23-ii6i>4$d491>"b?3?0(h655:&f=?3<,lk196*jb;78 `e==2.nh7;4$dg91>"bn3?0(k>55:&e5?3<,o8196*i3;78 c2==2.m97;4$g491>"a?3?0(k655:&e=?3<,ok196*ib;78 ce==2.mh7;4$gg91>"an3?0(<>?:49'557==2.:<?4:;%337?3<,8:?685+11791>"68?0>7)??7;78 46?2<1/==755:&24d<23-;;n7;4$02`>0=#99n196*>0d86?!77n3?0(<??:49'547==2.:=?4:;%327?3<,8;?685+10791>"69?0>7)?>7;78 47?2<1/=<755:&25d<23-;:n7;4$03`>0=#98n196*>1d86?!76n3?0(<<?:49'577==2.:>?4:;%317?3<,88?685+13791>"6:?087)?74;61?!c32<1/=5853:&0g<<6091/?no51928j<c=82dh<7>4n0:2>44<f8296?:4n2aa>44<f:ih6?:4$ba9`5=#91=186g;a;29?l2e2900en750;9j7f>=831b=5650;9j<0<72-;<n769;o34e?7<3`9<6=4+16`973=i9>k1<65f3483>!70j39=7c?8a;38?l53290/=:l5379m52g=:21b?>4?:%34f?513g;<m7=4;h11>5<#9>h1?;5a16c90>=n;80;6)?8b;15?k70i3?07d=?:18'52d=;?1e=:o56:9j6c<72-;<n7=9;o34e?1<3`8n6=4+16`973=i9>k1465f2e83>!70j39=7c?8a;;8?l26290/=:l5419m52g=821b?k4?:%34f?273g;<m7?4;h1f>5<#9>h18=5a16c96>=n;m0;6)?8b;63?k70i3907d=l:18'52d=<91e=:o54:9j7g<72-;<n7:?;o34e?3<3`9j6=4+16`905=i9>k1:65f3883>!70j3>;7c?8a;58?l5?290/=:l5419m52g=021b;i4?:%34f?1d3g;<m7>4;h5a>5<#9>h1;n5a16c95>=n?00;6)?8b;5`?k70i3807d97:18'52d=?j1e=:o53:9j32<72-;<n79l;o34e?2<3`==6=4+16`93f=i9>k1965f7483>!70j3=h7c?8a;48?l13290/=:l57b9m52g=?21b;>4?:%34f?1d3g;<m764;h51>5<#9>h1;n5a16c9=>=n?80;6)?8b;5`?k70i3k07d9?:18'52d=?j1e=:o5b:9j2`<72-;<n79l;o34e?e<3`<o6=4+16`93f=i9>k1h65f6b83>!70j3=h7c?8a;g8?l0e290/=:l57b9m52g=n21b:l4?:%34f?1d3g;<m7??;:k5=?6=,8=i6:m4n05b>47<3`<36=4+16`93f=i9>k1=?54i7594?"6?k0<o6`>7`827>=n>?0;6)?8b;5`?k70i3;?76g95;29 41e2>i0b<9n:078?l>3290/=:l57b9m52g=9?10e5=50;&23g<0k2d:;l4>7:9j<7<72-;<n79l;o34e?7?32c3=7>5$05a>2e<f8=j6<74;h:3>5<#9>h1;n5a16c95d=<a>l1<7*>7c84g>h6?h0:n65f7d83>!70j3=h7c?8a;3`?>o0i3:1(<9m:6a8j41f28n07d8i:18'52d=?j1e=:o51d98m32=83.:;o48c:l23d<6n21b4n4?:%34f?>e3g;<m7>4;h:b>5<#9>h14o5a16c95>=n000;6)?8b;:a?k70i3807d67:18'52d=0k1e=:o53:9l=1<72-;<n77<;o34e?6<3f396=4+16`9=6=i9>k1=65`9083>!70j3387c?8a;08?j?7290/=:l5929m52g=;21d4k4?:%34f??43g;<m7:4;n:f>5<#9>h15>5a16c91>=h1m0;6)?8b;;0?k70i3<07b7l:18'52d=1:1e=:o57:9l=g<72-;<n77<;o34e?><3f3j6=4+16`9=6=i9>k1565`9883>!70j3387c?8a;c8?j??290/=:l5929m52g=j21d5:4?:%34f??43g;<m7m4;n;5>5<#9>h15>5a16c9`>=h1<0;6)?8b;;0?k70i3o07b6k:18'52d=1:1e=:o5f:9lg6<72-;<n7m=;o34e?6<3fi:6=4+16`9g7=i9>k1=65fc`83>>o6000;66g<c683>>o2i3:1(<9m:4;8j41f2910e8650;&23g<212d:;l4>;:k63?6=,8=i6874n05b>7=<a<<1<7*>7c86=>h6?h0876g:5;29 41e2<30b<9n:598m02=83.:;o4:9:l23d<232c=?7>5$05a>0?<f8=j6;54i7094?"6?k0>56`>7`84?>o193:1(<9m:4;8j41f2110e;>50;&23g<212d:;l46;:k6b?6=,8=i6874n05b>d=<a<o1<7*>7c86=>h6?h0i76g:d;29 41e2<30b<9n:b98m0e=83.:;o4:9:l23d<c32c>n7>5$05a>0?<f8=j6h54i4194?"6?k0>56`>7`8e?>o??3:1(<9m:948j41f2910co650;&23g<e?2d:;l4?;:ma2?6=,8=i6o94n05b>4=<gk>1<7*>7c8a3>h6?h0976am3;29 41e2k=0b<9n:298kg4=83.:;o4m7:l23d<332ei=7>5$05a>g1<f8=j6854oc294?"6?k0i;6`>7`85?>ifn3:1(<9m:c58j41f2>10clk50;&23g<e?2d:;l47;:mb`?6=,8=i6o94n05b><=<ghi1<7*>7c8a3>h6?h0j76anb;29 41e2k=0b<9n:c98kd?=83.:;o4m7:l23d<d32ej47>5$05a>g1<f8=j6i54o`594?"6?k0i;6`>7`8f?>if>3:1(<9m:c58j41f2o10cl;50;&23g<e?2d:;l4>0:9le1<72-;<n7l8;o34e?7632ej?7>5$05a>g1<f8=j6<<4;nc1>5<#9>h1n:5a16c956=<gh;1<7*>7c8a3>h6?h0:865`a183>!70j3h<7c?8a;36?>ien3:1(<9m:c58j41f28<07blj:18'52d=j>1e=:o51698kgb=83.:;o4m7:l23d<6021dnn4?:%34f?d03g;<m7?6;:maf?6=,8=i6o94n05b>4g<3fhj6=4+16`9f2=i9>k1=o54oc;94?"6?k0i;6`>7`82g>=hj<0;6)?8b;`4?k70i3;o76ana;29 41e2k=0b<9n:0g8?j?a290/=:l5b69m52g=9o10cn650;&23g<d?2d:;l4?;:m`2?6=,8=i6n94n05b>4=<gj?1<7*>7c8`3>h6?h0976al4;29 41e2j=0b<9n:298yv2e83:1:vP;b19>63c=lh16>;m5d89>624=lj16>;85dc9>633=l01v9oj:1853~X4m?1U?i64^5`;?[2e>2T8h:5Q4c18Z1063W>i;6P;639]0=2<V:o?7S=j3:\0a7=Y;l;0R>k?;_1gb>X4ll1U?ij4^2f`?[2d:2T?o<5Q4b28Z1da3W>ii6P;be9]0ge<V=hi7S:ma:\7ea=Y<hi0R9om;_6be>X3i01U8l64^5c4?[2f>2T?m85Q4`6896b72m=01>ln:42896ga2<:01>l6:42896d?2<:01>l8:42896e52<:01>m>:42897d?2<801?l9:40897d32<801?l=:40897d72<801?oj:40897gd2<801?on:40897g?2<801?6j:40897>c2<801?6l:40897>e2<801?6n:408971e2<801?9n:408971>2<801?97:40897102<801>>6:408966?2<801>>8:40896612<801>>::40897`12<801?h::40897`32<801?h<:40897`52<801>==:40896572<801><j:408964d2<801><n:408964?2<801><9:40896432<801>om:97896ge282270=nb;1`3>;4ik0>m63<ac86<>;4ik0>;63<ac862>;4ik0>963<ac860>;4ik0=?63<ac856>;4ik0==63<ac854>;4ik0>j63<ac86a>;4ik0>h63<ac86g>;4ik0>n63<ac867>;4ik03;6s|4c094?5|V=h970=ma;34g>;4io0:;n5rs353>5<5sW>>:63=71823a=z{=i?6=4<{_6`0>;49h0o563<188g=>{t<h91<7;7{_6b7>;51k0?:63<b0872>;4j90?:63<ag872>;4j00?:63<b9872>;4j>0?:63=15872>;59:0?:63=13872>;5980?:63=11872>;58o0?:63=0d872>;58m0?:63=0b872>;5=j0?:63=5c872>;5=h0?:63=58872>;5=10?:63=56872>;5=?0?:63=54872>;5==0?:63=4`872>;5<00?:63=49872>;5<>0?:63=47872>;5<<0?:63=45872>;5<:0?:63=43872>;6l:0?:63>d3872>;6l80?:63>d1872>;6ko0?:63>cd872>;6km0?:63>cb872>;6kk0?:63>c`872>;5l10?:63=d6872>;5l<0?:63=d5872>;5l?0?:63=d2872>;5l;0?:63=d1872>;5ko0?:63=d0872>;5mj0?:63=ec872>;5mh0?:63=e8872>;5m10?:63=e6872>;5m?0?:63=e4872>;5m=0?:63=e2872>;5>o0?:63=71872>;5>h0?:63=68872>;4190?:63<8g872>;40l0?:63<8e872>;40j0?:63<8c872>;40h0?:63<88872>;4110?:63<96872>;41?0?:63<94872>;41=0?:63<92872>;41;0?:63<90872>;4010?:63<86872>;4ik0?m6s|30594?4|V=?h70=>7;34`>{t<k31<7:6{_6a=>;49>0?:63<17872>;4jj0?:63<b`872>;4jk0?:63<c3872>;4k80?:63>ae872>;6ij0?:63>ac872>;6ih0?:63>a8872>;6i10?:63>a6872>;6i?0?:63>a4872>;6n00?:63>f9872>;6n>0?:63>f7872>;6n<0?:63>f5872>;6n:0?:63>f3872>;6n80?:63>e6872>;6m?0?:63>e4872>;6m=0?:63>e2872>;6m;0?:63>e0872>;6m90?:63>dg872>;6ll0?:63=39872>;5;>0?:63=37872>;5;<0?:63=35872>;5;:0?:63=33872>;5;80?:63=31872>;4=k0?:63<58872>;4=h0?:63<5b872>;4=m0?:63<5d872>;4=o0?:63<61872>;4>80?:63<4g872>;4<l0?:63<4b872>;4<k0?:63<4e872>;4<h0?:63<48872>;4<>0?:63<49872>;4?:0?:63<73872>;4?80?:63<71872>;4>o0?:63<6d872>;4>m0?:63<6b872>;4>k0?:63<ac87f>{t;>n1<7<t^51:?85>83;<h6s|36a94?4|V=9370=7f;34`>{t;>h1<7<t^514?85?m3;<h6s|36c94?4|V=9=70=7d;34`>{t;>31<7<t^516?85?k3;<h6s|36:94?4|V=9?70=7b;34`>{t;>=1<7<t^510?85?i3;<h6s|36494?4|V=9970=79;34`>{t;1<1<7<t^562?85>03;<h6s|39794?4|V=>;70=67;34`>{t;1>1<7<t^51e?85>>3;<h6s|39194?4|V=9n70=65;34`>{t;181<7<t^51g?85><3;<h6s|39394?4|V=9h70=63;34`>{t;1:1<7<t^51a?85>:3;<h6s|36d94?4|V=9j70=61;34`>{t;>o1<7<t^512?85?03;<h6s|36794?4|V=9;70=77;34`>{t<;21<7<t^527?85fj3227p};2783>7}Y<9901>om:7c8yv25=3:1>vP;039>7dd=>01v9<;:181[279278mo498:p075=838pR9>?;<1bf?003ty?>?4?:3y]7c`<5:ki6;84}r614?6=:rT8ji523``920=z{=;m6=4={_1eg>;4ik0386s|40g94?4|V:li70=nb;:0?xu39m0;6?uQ3gc896ge2120q~:>c;296~X4n016?ll5839~w17e2909wS=i8:?0eg<?92wx8<o50;0xZ6`0349jn76?;|q75<<72;qU?k84=2ca>2`<uz>:47>52z\0b0=:;hh1;h5rs534>5<5sW9m863<ac84e>{t<8?1<7<t^2d1?85fj3<m7p};1583>7}Y;o;01>om:768yv26;3:1>vP<f19>7dd=0j1v9?=:181[5bn278mo48d:p047=838pR>kj;<1bf?1e3ty?==4?:3y]7`b<5:ki6:74}r63b?6=:rT8in523``93==z{=:n6=4={_1ff>;4ik0<;6s|41f94?4|V:oj70=nb;55?xu38j0;6?uQ3d;896ge2>?0q~:=f;296~X38h16?ll5759~w14b2909wS:?9:?0eg<?i2wx8?j50;0xZ16?349jn79<;|q76f<72;qU8=94=2ca>24<uz>9n7>52z\743=:;hh1;<5rs50b>5<5sW>;963<ac844>{t<;31<7<t^2df?85fj3<n7p};2083>7}Y;o901>om:7f8yv26>3:1>vP<e99>7dd=>j1v9>m:181[5b?278mo49b:p563=833p1>j>:05;?84ei3>270<n8;6:?84?i3>270<87;6:?857=3>270<i2;6:?854<3>270==4;6:?xu51j0;6?u228`915=::0n1=:84}r1a2?6=9hq6>4l516a896d>28=o70<k8;6`?84c?3>h70<k5;6`?84c<3>h70<k6;6`?84c;3>h70<k2;6`?84c83>h70<lf;34g>;5l80?o63=eb87g>;5mk0?o63=e`87g>;5m00?o63=e987g>;5m>0?o63=e787g>;5m<0?o63=e587g>;5m:0?o63=6g823f=::>:1=:m4=34b>1e<5;<269m4}r0:f?6=<r795o4>7e9>63e=lj16?lj5d89>633=lh1v>li:181<~;49>0?o63<1787g>;4k80:;i521`f90f=:9hi18n521``90f=:9hk18n521`;90f=:9h218n521`590f=:9h<18n521`790f=:9o318n521g:90f=:9o=18n521g490f=:9o?18n521g690f=:9o918n521g090f=:9o;18n521d590f=:9l<18n521d790f=:9l>18n521d190f=:9l818n521d390f=:9l:18n521ed90f=:9mo18n5222:90f=:::=18n5222490f=:::?18n5222690f=:::918n5222090f=:::;18n5222290f=z{:;36=4<{<123?37349::7;?;<12=?70>2wx?<850;1x967128=o70=>a;fb?85613nj7p}<b183>6}:;k;19=523c2952b<5:km6994}r1a5?6=:r78n<4>7e9>7g5=l01v>lm:18085ek3?;70=ma;64?85ej3;<h6s|3ca94?4|5:hh6<9k;<1aa?b>3ty8mk4?:2y>7g6==916?lh516f896d42mk0q~=ma;297~;4jh0:;i523c`915=:;ko1hl5rs2`1>5<3s49i57?8c:?0f=<6?j16?o9516a896d428==7p}<b483>70|5:h36<9k;<020?2d348:?7:l;<026?2d348:=7:l;<024?2d348;j7:l;<03a?2d348;h7:l;<03g?2d348>o7:l;<06f?2d348>m7:l;<06=?2d348>47:l;<063?2d348>:7:l;<061?2d348>87:l;<07e?2d348?57:l;<07<?2d348?;7:l;<072?2d348?97:l;<070?2d348??7:l;<076?2d34;o?7:l;<3g6?2d34;o=7:l;<3g4?2d34;hj7:l;<3`a?2d34;hh7:l;<3`g?2d34;hn7:l;<3`e?2d3ty8n94?:07x96d028=o70=60;34a>;40o0:;h5239g952c<5:2o6<9j;<1;g?70m2784o4>7d9>7=g=9>o01>66:05f?85>03;<i63<96823`=:;0<1=:k4=2;6>41b349287?8e:?0=6<6?l16?4<516g896?628=n70=78;34a>;40>0:;h523`f9`d=:;hh1=564}r1a`?6=;r78o?4>7b9>7f7=9>i01>lj:055?xu4k90;6<mt=2a1>41c349>n7:l;<16=?70k2789l4;c:?01f<3k2789i4;c:?01`<3k2789k4;c:?025<3k278:<4;c:?00c<3k2788h4;c:?00f<3k2788o4;c:?00a<3k2788l4;c:?00<<3k2788:4;c:?00=<6?j16?:=54b9>724=<j16?:?54b9>726=<j16?;h54b9>73c=<j16?;j54b9>73e=<j16?;l54b9~w4`7290>w0?nd;73?87a13;<h63>ag8ge>;6j80o563>b28gg>{t9h>1<7=t=0cg>41c349:?7jn;<134?bf3ty:mh4?:3y>5de==916=lh51648yv7f;3:1?v3>ab823a=:;881h4522gd9`<=z{8h;6=4={<3bf?3734;i=7?86:p5d4=839p1<om:05g?856:3ni70<if;fa?xu6j;0;6;u21`c915=:9k91=:84=0`6>ag<58h<6i74=0`:>ae<58hi6im4}r3b5?6=;r7:ml4>7e9>747=l016>kk5d89~w4d32909w0?n9;73?87e=3;<:6s|1`294?5|58k26<9k;<125?be348mi7jm;|q2f3<72;q6=l65519>5g1=9><0q~?6f;297~;6i10:;i523029`<=::on1h45rs0`;>5<5s4;j;7;?;<3a=?70>2wx=4k50;1x94g028=o70=>0;fa?84al3ni7p}>b`83>7}:9h<19=521ca9520<uz;2h7>53z?2e3<6?m16?=h5d89>6ce=l01v<lj:18187f=3?;70?mf;342>{t90i1<7=t=0c6>41c349;j7jm;<0eg?be3ty99>4?:4y>642==916>8m516f897712mk01??7:e;8977f2mi0q~<?b;297~;59=0:;i5228:9`d=::1?1hl5rs336>5<5s48:?7;?;<022?70>2wx>=o50;1x977428=o70<68;f:?84?=3nh7p}=1683>7}::8819=5220:9520<uz8;57>53z?157<6?m16>495d`9>6=2=lh1v??6:18584693?;70<>a;342>;59j0om63=1d8g=>;5:90oo63=238gg>{t:921<7=t=332>41c3482;7j6;<0;0?b>3ty9=o4?:3y>646==916><m51648yv47?3:1?v3=11823a=::0<1hl522919`d=z{;;o6=4={<03b?37348:i7?86:p650=839p1?>i:05g?84>>3n270<73;f:?xu59o0;6?u221g915=::;:1=:84}r031?6=;r79<h4>7e9>6<3=lh16>5<5d`9~w7462909w0<?d;73?845;3;<:6s|21694?5|5;:o6<9k;<0:1?b>3483>7j6;|q160<72;q6>=m5519>670=9><0q~<?3;297~;58j0:;i522869`<=::1;1h45rs362>5<5s48>o7;?;<07e?70l2wx>9>50;0x973e2<:01?:6:05g?xu5=;0;69u224`952b<5;;=6i74=33;>ag<5;;j6il4}r00b?6=:r799l4:0:?10=<6?m1v?;>:180842i3;<h63=198gf>;59h0om6s|22g94?4|5;?268>4=364>41c3ty99=4?:3y>60?=9>n01??n:e;8yv44l3:1>v3=59864>;5<?0:;i5rs36e>5<2s48>47?8d:?15f<c1279=h4ka:?165<cj279>?4kb:p66e=838p1?;8:428972228=o7p}=4d83>1}::<=1=:j4=33f>ad<5;8;6io4=301>ag<uz88n7>52z?113<28279894>7e9~w72c2908w0<:6;34`>;5:90o563=238g=>{t::k1<7<t=376>06<5;>86<9k;|q10f<72:q6>8;516f897442m301?<9:ec8yv4413:1>v3=55864>;5<;0:;i5rs36a>5<5s48>87?8d:?163<c12wx=ij50;0x94`>2<:01<k8:05g?xu6lj0;6?u21g:915=:9l<1=:j4}r3fb?6=<r7:j54>7e9>5d`=l016=o?5d`9>5g5=lk1v<jm:18187a?3?;70?j5;34`>{t9lo1<7=t=0d4>41c34;i=7jm;<3a7?bf3ty:hl4?:3y>5c0==916=h:516f8yv7bl3:1>v3>f7823a=:9k91h45rs0f:>5<5s4;m97;?;<3f7?70l2wx=hm50;7x94`228=o70?m5;f:?87e?3nj70?m9;fa?87ej3ni7p}>d983>7}:9o>19=521d0952b<uz;nn7>54z?2b1<6?m16=o95dc9>5g?=lh16=ol5d`9~w4b02909w0?i3;73?87b93;<h6s|1dc94?5|58l86<9k;<3a=?b>34;in7j6;|q2`3<72;q6=k<5519>5`6=9>n0q~?j9;297~;6n;0:;i521ca9`<=:9kl1hl5rs0f6>5<5s4;m=7;?;<3gb?70l2wx=h650;0x94`628=o70?mf;f:?xu5:o0;6?u225c915=:::21=:j4}r01a?6=:r79844:0:?172<6?m1v?<k:18184303?;70<<6;34`>{t:;i1<7<t=364>06<5;9>6<9k;|q16g<72;q6>985519>662=9>n0q~<=a;296~;5<<0><63=32823a=z{;826=4={<070?373488>7?8d:p67>=838p1?:<:428975628=o7p}=2683>7}::=819=52222952b<uz;h57>52z?2a2<2827:h>4>7e9~w4e?2909w0?j6;73?87c:3;<h6s|1b594?4|58o>68>4=0f2>41c3ty:o;4?:3y>5`2==916=i>516f8yv7d=3:1>v3>e2864>;6ko0:;i5rs0a7>5<5s4;n>7;?;<3`a?70l2wx=n=50;0x94c62<:01<mk:05g?xu6k;0;6?u21d2915=:9ji1=:j4}r3`5?6=:r7:hk4:0:?2gg<6?m1v<m?:18187cm3?;70?la;34`>{t9m>1<7?t=0ff>41c3ty9i?4?:4y>5a5==916>hm516f894>e2m301?6::e;896ge2:=0q~?ia;296~;6l;0><63>8c8233=z{8li6=4={<3g5?3734;3o7?86:p5ce=838p1<j?:42894>c28==7p}>fe83>7}:9jl19=5219g9520<uz;mi7>52z?2g`<2827:4k4>779~w4`a2909w0?ld;73?87>83;<:6s|21294?4|58ih68>4=0;2>4113ty9<<4?:3y>5fd==916=4<51648yv47:3:1>v3>c`864>;61:0:;;5rs24b>5<3s48847;?;<147?70l27:594k9:?0eg<392wx>8j50;0x97502<:01<7;:055?xu5=l0;6?u2224915=:90?1=:84}r06b?6=:r79?84:0:?2=3<6??1v?8?:181844<3?;70?67;342>{t:?;1<7<t=310>06<58336<99;|q127<72;q6>><5519>5<?=9><0q~<93;296~;5;80><63>9`8233=z{;<?6=4={<004?3734;2n7?86:p6`b=83;<w0<k8;64?84c?3><70<k5;64?84c<3><70<k6;64?84c;3><70<k2;64?84c83><70<lf;64?84c93><70<jc;64?84bj3><70<ja;64?84b13><70<j8;64?84b?3><70<j6;64?84b=3><70<j4;64?84b;3><70=nd;fa?841=3;<:63=9e8g=>{t:h=1<7<t=3f;>06<5;i86<99;|q1g`<72=q6>i6516f897cd2<:01?77:ea897e32m30q~<n6;296~;5l>0><63=c38233=z{;io6=4;{<0g3?70l279io4:0:?1==<cj279n44k9:p6d2=838p1?j::42897e728==7p}=cc83>1}::m?1=:j4=3g:>06<5;3<6il4=3`6>a?<uz8j?7>52z?1`1<28279nk4>779~w7ef290?w0<k4;34`>;5m10><63=978gg>;5j:0o56s|2`794?4|5;n=68>4=3a2>4113ty9on4?:5y>6a0=9>n01?kn:42897?02mi01?l8:e;8yv4f:3:1>v3=d2864>;5jl0:;;5rs3a:>5<3s48o?7?8d:?1a2<282795;4kb:?1f4<c12wx>l?50;0x97b52<:01?lk:055?xu5k10;69u22e0952b<5;o=68>4=3;6>ae<5;km6i74}r0:b?6=:r79h=4:0:?1fg<6??1v?m9:18784c83;<h63=e5864>;51=0on63=ac8g=>{t:0o1<7<t=3ae>06<5;hj6<99;|q1g0<72=q6>nh516f897c42<:01?7;:ec897g>2m30q~<n0;296~;5l80><63=bb8233=z{;i<6=4;{<0g5?70l279i84:0:?1=0<cj279mi4k9:p6g>=838p1?m<:5;897d?28==7p}=c583>7}::j91=?64=3a7>4113ty9n;4?:2y>6f4=<016>o65489>6g0=9><0q~<m9;297~;5k;0:>5522c:95=5<5;h26<99;|q1f1<72:q6>n?5489>6g0=<016>o:51648yv4e?3:1?v3=c0826==::k<1=5=4=3`4>4113ty9n?4?:2y>6f6=<016>o:5489>6g4=9><0q~<m5;297~;5k90:>5522c695=5<5;h>6<99;|q1f5<72:q6>oh5489>6g4=<016>o>51648yv4e;3:1?v3=bg826==::k81=5=4=3`0>4113ty9mh4?:2y>6gc=<016>o>5489>6dc=9><0q~<m1;297~;5jl0:>5522c295=5<5;h:6<99;|q1ef<72:q6>oj5489>6dc=<016>lm51648yv4fn3:1?v3=be826==::ho1=5=4=3ce>4113ty9ml4?:2y>6ge=<016>lm5489>6dg=9><0q~<nd;297~;5jj0:>5522`a95=5<5;ko6<99;|q1e=<72:q6>ol5489>6dg=<016>l651648yv4fj3:1?v3=bc826==::hk1=5=4=3ca>4113ty9m44?:2y>6gg=9;201?o7:0:0?84f13;<:6s|2d394?3|5;oi6<9k;<3;g?b>34;3n7jn;<0;1?be349jn7=:;|q1a5<72<q6>ho516f894>c2m301<6l:ec897>32mi01>om:268yv4cn3:19v3=e8823a=:91o1h45219f9`d=::1>1ho523``976=z{;nn6=4:{<0f<?70l27:4k4k9:?2<`<ci2794>4kc:?0eg<4:2wx>ij50;7x97c028=o70?60;f:?87?n3nj70<73;fa?85fj39:7p}=db83>0}::l<1=:j4=0;2>a?<583;6io4=3:1>ae<5:ki6>>4}r0gf?6==r79i84>7e9>5<4=l016=4?5d`9>6=4=lk16?ll52g9~w7bf290>w0<j4;34`>;61:0o563>938ge>;5080on63<ac81a>{t:m31<7:t=3g0>41c34;2?7jn;<0;5?bf349jn7<k;|q134<72:q6>;h5519>626==916>:<51648yv41n3:1>v3=6g823a=::>81h45rs34a>5<5s48=m7;?;<05g?70>2wx>;650;4x970f28=o70<9e;fa?841k3ni70<82;fa?841>3n270<95;fa?xu5>m0;6?u227;915=::?o1=:84}r053?6=>r79:44>7e9>63c=l016>;m5d`9>624=lh16>;85d`9>633=lj1v?66:18184?m3>270<7d;342>{t:091<7<t=3:f>4>4348247?86:p6<g=838p1?6j:055?84>l3nj7p}=8983>7}::1n1845229a9520<uz82>7>52z?1<a<60:16>4951648yv4??3:1>v3=8b87=>;50k0:;;5rs3;2>5<5s483o7?73:?1=3<6??1v?69:18184?j3>270<7a;342>{t:0:1<7<t=3:a>4>4348297?86:p6=`=838p1?6n:0:0?84><3;<:6s|26494?4|5;=i6974=35b>4113ty94=4?:3y>62d=91901?6::055?xu5100;6?u226`9520<5;3o6il4}r041?6=:r79;l4;9:?13<<6??1v?9i:181840i3;3?63=858233=z{;=?6=4={<04=?2>348<47?86:p62c=838p1?96:0:0?84?;3;<:6s|26194?4|5;=36974=354>4113ty9;i4?:3y>62>=91901?6=:055?xu5?j0;6?u226595=5<5;2:6<99;|q041<72;q6?=75489>75>=9><0q~=?e;296~;4800:4>523019520<uz9:97>52z?04<<6??16?<75db9~w6642909w0=?8;6:?857?3;<:6s|31f94?4|5::36<6<;<126?70>2wx?=<50;0x96602=301>>9:055?xu48j0;6?u231595=5<5:;:6<99;|q044<72;q6?=85489>753=9><0q~=?b;296~;48?0:4>523029520<uz9;m7>52z?040<60:16?=h51648yv4a93:1>v3=f787=>;5n<0:;;5rs3da>5<5s48m:7?73:?045<6??1v>?;:18184a>3;<:63<188gf>{t:o:1<7<t=3d6>1?<5;l?6<99;|q1bd<72;q6>k;5191897`a28==7p}=eg83>7}::o>184522g19520<uz8m57>52z?1b1<60:16>kk51648yv4bm3:1>v3=f287=>;5n;0:;;5rs3d;>5<5s48m?7?73:?1ba<6??1v?h8:18184a:3;3?63=fb8233=z{:=?6=4>ez?01g<3?278944;7:?01d<3?2789n4;7:?01a<3?2789h4;7:?01c<3?278:=4;7:?024<3?2788k4;7:?00`<3?2788n4;7:?00g<3?2788i4;7:?00d<3?278844;7:?002<3?278854;7:?036<3?278;?4;7:?034<3?278;=4;7:?02c<3?278:h4;7:?02a<3?278:n4;7:?02g<3?278=l4>779>7dd=;j201>om:bc8yv5383:18v3<5c864>;4<00:;i523029`f=:;;31h45rs271>5<4s49>n7?8d:?02a<28279ji4kc:p76c=83>p1>;6:428962028=o70=?f;f`?855=3n27p}<5183>6}:;<31=:j4=24a>06<5;lh6im4}r10b?6=<r789l4:0:?00=<6?m16?=h5d`9>771=l01v>;>:180852i3;<h63<6b864>;5nj0om6s|35394?2|5:?h68>4=26b>41c349:<7jn;<11f?b>3ty89>4?:2y>70e=9>n01>8j:42897`c2mk0q~=;2;290~;4=m0><63<4c823a=:;8;1hn5233f9`<=z{:??6=4<{<16`?70l278:k4:0:?1b`<ck2wx?9=50;6x963b2<:01>:l:05g?85693nj70==f;f:?xu4=<0;6>u234g952b<5:=;68>4=3df>ag<uz9?87>54z?01c<282788i4>7e9>744=lj16?>?5d89~w6312908w0=:f;34`>;4?80><63=fg8gg>{t;=?1<7:t=243>06<5:>n6<9k;<126?bf3498?7j6;|q012<72:q6?;>516f896152<:01?hi:ec8yv53>3:18v3<60864>;4<o0:;i523019`<=:;:n1h45rs27;>5<4s49==7?8d:?036<28278<=4k9:p775=838p1>:i:428965d28==7p}<2383>7}:;=o19=5232`9520<uz99<7>52z?00f<28278?44>779~w67a2909w0=;b;73?85403;<:6s|33394?4|5:>o68>4=21b>4113ty8=h4?:3y>71g==916?>951648yv56l3:1>v3<48864>;4;?0:;;5rs23a>5<5s49?;7;?;<100?70>2wx?<m50;0x962?2<:01>=::055?xu4;;0;6?u232a90<=:;:81=:84}r10`?6=:r78?n4>299>76b=9><0q~=<0;297~;4;k0?563<3387=>;4;90:;;5rs210>5<4s498n7?=8:?077<60:16?>=51648yv55m3:1?v3<3`87=>;4;90?563<2d8233=z{:9:6=4<{<10e?750278?=4>829>767=9><0q~==c;297~;4;00?563<2d87=>;4:j0:;;5rs20e>5<4s49857?=8:?06`<60:16??h51648yv55i3:1?v3<3987=>;4:j0?563<2`8233=z{:8o6=4<{<10<?750278>n4>829>77b=9><0q~==8;297~;4;>0?563<2`87=>;4:10:;;5rs20a>5<4s498;7?=8:?06d<60:16??l51648yv55>3:1?v3<3787=>;4:10?563<278233=z{:826=4<{<102?750278>54>829>77?=9><0q~==4;297~;4;<0?563<2787=>;4:=0:;;5rs204>5<4s49897?=8:?063<60:16??951648yv55=3:1?v3<35826==:;;>1=5=4=206>4113ty8:44?:5y>724=9>n01<7::e;894?32mk01>om:2d8yv5103:18v3<70823a=:90<1h4521879`d=:;hh1?h5rs244>5<3s49<<7?8d:?2=2<c127:5;4ka:?0eg<4l2wx?;850;6x960a28=o70?68;f:?87>?3nj70=nb;1`?xu4><0;69u237g952b<58326i74=0;;>ag<5:ki6>l4}r150?6=<r78:i4>7e9>5<g=l016=475d`9>7dd=;h1v>8<:187851k3;<h63>9c8g=>;61h0om63<ac80=>{t;?81<7=t=24a>41c34;2n7jn;<1bf?5?3ty8mh4?:01x96?72==01>6i:55896>b2==01>6k:55896>d2==01>6m:55896>f2==01>66:55896??2==01>78:55896?12==01>7::55896?32==01>7<:55896?52==01>7>:55896>?2==01>68:558970128==7p}<a083>7}:;0:19=523``9g6=z{:k;6=4={<1;b?37349jn77;;|q0=c<72;q6?5k5519>7dd=1;1v>7j:18185?l3?;70=nb;;2?xu41m0;6?u239a915=:;hh15=5rs2;`>5<5s493n7;?;<1bf?>a3ty85o4?:3y>7=g==916?ll58d9~w6?f2909w0=79;73?85fj33o7p}<a`83>7}:;0219=523``9=f=z{:k26=4={<1:3?37349jn7m>;|q0e=<72;q6?485519>7dd=1k1v>o8:18185>=3?;70=nb;;b?xu4i?0;6?u2386915=:;hh1545rs2c6>5<5s492?7;?;<1bf???3ty8m94?:3y>7<4==916?ll5969~w6g42909w0=61;73?85fj33=7p}<a383>7}:;1219=523``9=0=z{:326=4={<1;3?37349jn76k;|q0ef<72;q6?lj5164896ge2j30q~?<7;296~;5::0om63=23826<=z{8?86=4={<3ag?bf34;in7?=9:p672=838p1?<9:e`8974528==7p}>be83>7}:9kl1ho521c`9520<uty?n?4?:3y]0g4<5=>18o<4$2a0>4163ty?n44?:3y]0g?<5=>18o74$2a0>4153ty?m>4?:3y]0d5<5=>18l=4$2a0>4143ty?>54?:3y]052<5=>18=:4$2a0>4503ty?>;4?:3y]055<5=>18==4$2a0>4253ty?>84?:3y]054<5=>18=<4$2a0>42e3ty?>94?:3y]057<5=>18=?4$2a0>42c3ty?>>4?:3y]056<5=>18=>4$2a0>42b3ty?>?4?:3y]7c`<5=>1?kh4$2a0>42a3ty?>=4?:3y]7cb<5=>1?kj4$2a0>4373ty?=k4?:3y]7ce<5=>1?km4$2a0>4363ty?=h4?:3y]7cd<5=>1?kl4$2a0>4353ty?=i4?:3y]7cg<5=>1?ko4$2a0>4333ty?=n4?:3y]7c?<5=>1?k74$2a0>4323ty?=o4?:3y]7c><5=>1?k64$2a0>4313ty?=l4?:3y]7c1<5=>1?k94$2a0>4303ty?=44?:3y]7c0<5=>1?k84$2a0>43?3ty?=54?:3y]7c3<5=>1?k;4$2a0>43>3ty?=:4?:3y]7c2<5=>1?k:4$2a0>43f3ty?=84?:3y]7c4<5=>1?k<4$2a0>43e3ty?=94?:3y]7c7<5=>1?k?4$2a0>43d3ty?=>4?:3y]7c6<5=>1?k>4$2a0>43c3ty?=?4?:3y]7``<5=>1?hh4$2a0>43b3ty?=<4?:3y]7`c<5=>1?hk4$2a0>43a3ty?==4?:3y]7`b<5=>1?hj4$2a0>4073ty?<k4?:3y]7`e<5=>1?hm4$2a0>4063ty?<h4?:3y]7`d<5=>1?hl4$2a0>4053ty?<i4?:3y]7`g<5=>1?ho4$2a0>4043ty?<n4?:3y]7`?<5=>1?h74$2a0>4033ty?>k4?:3y]05g<5=>18=o4$2a0>4023ty?>h4?:3y]05?<5=>18=74$2a0>4013ty?>i4?:3y]05><5=>18=64$2a0>4003ty?>n4?:3y]051<5=>18=94$2a0>40?3ty?>o4?:3y]050<5=>18=84$2a0>40>3ty?>l4?:3y]053<5=>18=;4$2a0>40f3ty?>44?:3y]7cc<5=>1?kk4$2a0>40e3ty?><4?:3y]7c5<5=>1?k=4$2a0>40d3ty?=;4?:3y]7`><5=>1?h64$2a0>40c3ty?<o4?:3y]7`1<5=>1?h94$2a0>40b3ty?o94?:3y]0f2<5=>18n:4$2a0>40a3ty?n=4?:3y]0g6<5=>18o>4$2a0>4173ty?8o4?:3y]06?<5=>18>74$2a0>4513ty?844?:3y]06><5=>18>64$2a0>45?3ty?854?:3y]061<5=>18>94$2a0>45>3ty?8:4?:3y]060<5=>18>84$2a0>45f3ty?8;4?:3y]063<5=>18>;4$2a0>45e3ty?884?:3y]062<5=>18>:4$2a0>45d3ty?894?:3y]065<5=>18>=4$2a0>45c3ty?8>4?:3y]064<5=>18><4$2a0>45b3ty?994?:3y]017<5=>189?4$2a0>45a3ty?9>4?:3y]016<5=>189>4$2a0>4273ty?9?4?:3y]06`<5=>18>h4$2a0>4263ty?9<4?:3y]06c<5=>18>k4$2a0>4243ty?9=4?:3y]06b<5=>18>j4$2a0>4233ty?8k4?:3y]06e<5=>18>m4$2a0>4223ty?8h4?:3y]06d<5=>18>l4$2a0>4213ty?8i4?:3y]06g<5=>18>o4$2a0>4203ty?8n4?:3y]067<5=>18>?4$2a0>42?3ty?8?4?:3y]066<5=>18>>4$2a0>42>3ty?9n4?:3y]00e<5=>188m4$2a0>42f3ty?9;4?:3y]000<5=>18884$2a0>42d3twe4oh50;0xL6e33td3o=4?:3yK7f2<ug2h=7>52zJ0g1=zf1i96=4={I1`0>{i0j91<7<tH2a7?xh?k=0;6?uG3b68yk>d=3:1>vF<c59~j=e12909wE=l4:m<f1=838pD>m;;|l;g=<72;qC?n:4}o:`=?6=:rB8o95rn9ab>5<5sA9h86sa8b`94?4|@:i?7p`7cb83>7}O;j>0qc6ld;296~N4k=1vb5mj:181M5d<2we4nh50;0xL6e33td3h=4?:3yK7f2<ug2o=7>52zJ0g1=zf1n96=4={I1`0>{i0m91<7<tH2a7?xh?l=0;6?uG3b68yk>c=3:1>vF<c59~j=b12909wE=l4:m<a1=838pD>m;;|l;`=<72;qC?n:4}o:g=?6=:rB8o95rn9fb>5<5sA9h86sa8e`94?4|@:i?7p`7db83>7}O;j>0qc6kd;296~N4k=1vb5jj:181M5d<2we4ih50;0xL6e33td3i=4?:3yK7f2<ug2n=7>52zJ0g1=zf1o96=4={I1`0>{i0l91<7<tH2a7?xh?m=0;6?uG3b68yk>b=3:1>vF<c59~j=c12909wE=l4:m<`1=838pD>m;;|l;a=<72;qC?n:4}o:f=?6=:rB8o95rn9gb>5<5sA9h86sa8d`94?4|@:i?7p`7eb83>7}O;j>0qc6jd;296~N4k=1vb5kj:181M5d<2we4hh50;0xL6e33td3j=4?:3yK7f2<ug2m=7>52zJ0g1=zf1l96=4={I1`0>{i0o91<7<tH2a7?xh?n=0;6?uG3b68yk>a=3:1>vF<c59~j=`12909wE=l4:m<c1=838pD>m;;|l;b=<72;qC?n:4}o:e=?6=:rB8o95rn9db>5<5sA9h86sa8g`94?4|@:i?7p`85683>4}O;j>0qc964;295~N4k=1vb:7::182M5d<2we;4850;3xL6e33td<5:4?:0yK7f2<ug=247>51zJ0g1=zf>326=4>{I1`0>{i?0k1<7?tH2a7?xh01k0;6<uG3b68yk1>k3:1=vF<c59~j2?c290:wE=l4:m3<c=83;pD>m;;|l4=c<728qC?n:4}o5b4?6=9rB8o95rn6c2>5<6sA9h86sa7`094?7|@:i?7p`8a283>4}O;j>0qc9n4;295~N4k=1vb:o::182M5d<2we;l850;3xL6e33td<m:4?:0yK7f2<ug=j47>51zJ0g1=zf>k26=4>{I1`0>{i?hk1<7?tH2a7?xh0ik0;6<uG3b68yk1fk3:1=vF<c59~j2gc290:wE=l4:m3dc=83;pD>m;;|l4ec<728qC?n:4}o5a4?6=9rB8o95rn6`2>5<6sA9h86sa7c094?7|@:i?7p`8b283>4}O;j>0qc9m4;295~N4k=1vb:l::182M5d<2we;o850;3xL6e33td<n:4?:0yK7f2<ug=i47>51zJ0g1=zf>h26=4>{I1`0>{i?kk1<7?tH2a7?xh0jk0;6<uG3b68yk1ek3:1=vF<c59~j2dc290:wE=l4:m3gc=83;pD>m;;|l4fc<728qC?n:4}o5`4?6=9rB8o95rn6a2>5<6sA9h86sa7b094?7|@:i?7p`8c283>4}O;j>0qc9l4;295~N4k=1vb:m::182M5d<2we;n850;3xL6e33td<o:4?:0yK7f2<ug=h47>51zJ0g1=zf>i26=4>{I1`0>{i?jk1<7?tH2a7?xh0kk0;6<uG3b68yk1dk3:1=vF<c59~j2ec290:wE=l4:m3fc=83;pD>m;;|l4gc<728qC?n:4}o5g4?6=9rB8o95rn6f2>5<6sA9h86sa7e094?7|@:i?7p`8d283>4}O;j>0qc9k4;295~N4k=1vb:j::182M5d<2we;i850;3xL6e33td<h:4?:0yK7f2<ug=o47>51zJ0g1=zf>n26=4>{I1`0>{i?mk1<7?tH2a7?xh0lk0;6<uG3b68yk1ck3:1=vF<c59~j2bc290:wE=l4:m3ac=83;pD>m;;|l4`c<728qC?n:4}o5f4?6=9rB8o95rn6g2>5<6sA9h86sa7d094?7|@:i?7p`8e283>4}O;j>0qc9j4;295~N4k=1vb:k::182M5d<2we;h850;3xL6e33td<i:4?:0yK7f2<ug=n47>51zJ0g1=zf>o26=4>{I1`0>{i?lk1<7?tH2a7?xh0mk0;6<uG3b68yk1bk3:1=vF<c59~j2cc290:wE=l4:m3`c=83;pD>m;;|l4ac<728qC?n:4}o5e4?6=9rB8o95rn6d2>5<6sA9h86sa7g094?7|@:i?7p`8f283>4}O;j>0qc9i4;295~N4k=1vb:h::182M5d<2we;k850;3xL6e33td<j:4?:0yK7f2<ug=m47>51zJ0g1=zf>l26=4>{I1`0>{i?ok1<7?tH2a7?xh0nk0;6<uG3b68yk1ak3:1=vF<c59~j2`c290:wE=l4:m3cc=83;pD>m;;|l4bc<728qC?n:4}o:34?6=9rB8o95rn922>5<6sA9h86sa81094?7|@:i?7p`70283>4}O;j>0qc6?4;295~N4k=1vb5>::182M5d<2we4=850;3xL6e33td3<:4?:0yK7f2<ug2;47>51zJ0g1=zf1:26=4>{I1`0>{i09k1<7?tH2a7?xh?8k0;6<uG3b68yk>7k3:1=vF<c59~j=6c290:wE=l4:m<5c=83;pD>m;;|l;4c<728qC?n:4}o:24?6=9rB8o95rn932>5<6sA9h86sa80094?7|@:i?7p`71283>4}O;j>0qc6>4;295~N4k=1vb5?::182M5d<2we4<850;3xL6e33td3=:4?:0yK7f2<ug2:47>51zJ0g1=zf1;26=4>{I1`0>{i08k1<7?tH2a7?xh?9k0;6<uG3b68yk>6k3:1=vF<c59~j=7c290:wE=l4:m<4c=83;pD>m;;|l;5c<728qC?n:4}o:14?6=9rB8o95rn902>5<6sA9h86sa83094?7|@:i?7p`72283>4}O;j>0qc6=4;295~N4k=1vb5<::182M5d<2we4?850;3xL6e33td3>:4?:0yK7f2<ug2947>51zJ0g1=zf1826=4>{I1`0>{i0;k1<7?tH2a7?xh?:k0;6<uG3b68yk>5k3:1=vF<c59~j=4c290:wE=l4:m<7c=83;pD>m;;|l;6c<728qC?n:4}o:04?6=9rB8o95rn912>5<6sA9h86sa82094?7|@:i?7p`73283>4}O;j>0qc6<4;295~N4k=1vb5=::182M5d<2we4>850;3xL6e33td3?:4?:0yK7f2<ug2847>51zJ0g1=zf1926=4>{I1`0>{i0:k1<7?tH2a7?xh?;k0;6<uG3b68yk>4k3:1=vF<c59~j=5c290:wE=l4:m<6c=83;pD>m;;|l;7c<728qC?n:4}o:74?6=9rB8o95rn962>5<6sA9h86sa85094?7|@:i?7p`74283>4}O;j>0qc6;4;295~N4k=1vb5:::182M5d<2we49850;3xL6e33td38:4?:0yK7f2<ug2?47>51zJ0g1=zf1>26=4>{I1`0>{i0=k1<7?tH2a7?xh?<k0;6<uG3b68yk>3k3:1=vF<c59~j=2c290:wE=l4:m<1c=83;pD>m;;|l;0c<728qC?n:4}o:64?6=9rB8o95rn972>5<6sA9h86sa84094?7|@:i?7p`75283>4}O;j>0qc6:4;295~N4k=1vb5;::182M5d<2we48850;3xL6e33td39:4?:0yK7f2<ug2>47>51zJ0g1=zf1?26=4>{I1`0>{i0<k1<7?tH2a7?xh?=k0;6<uG3b68yk>2k3:1=vF<c59~j=3c290:wE=l4:m<0c=83;pD>m;;|l;1c<728qC?n:4}o:54?6=9rB8o95rn942>5<6sA9h86sa87094?7|@:i?7p`76283>4}O;j>0qc694;295~N4k=1vb58::182M5d<2we4;850;3xL6e33td3::4?:0yK7f2<ug2=47>51zJ0g1=zf1<26=4>{I1`0>{i0?k1<7?tH2a7?xh?>k0;6<uG3b68yk>1k3:1=vF<c59~j=0c290:wE=l4:m<3c=83;pD>m;;|l;2c<728qC?n:4}o:44?6=9rB8o95rn952>5<6sA9h86sa86094?7|@:i?7p`77283>4}O;j>0qc684;295~N4k=1vb59::182M5d<2we4:850;3xL6e33td3;:4?:0yK7f2<ug2<47>51zJ0g1=zf1=26=4>{I1`0>{i0>k1<7?tH2a7?xh??k0;6<uG3b68yk>0k3:1=vF<c59~j=1c290:wE=l4:m<2c=83;pD>m;;|l;3c<728qC?n:4}o:;4?6=9rB8o95rn9:2>5<6sA9h86sa89094?7|@:i?7p`78283>4}O;j>0qc674;295~N4k=1vb56::182M5d<2we45850;3xL6e33td34:4?:0yK7f2<ug2347>51zJ0g1=zf1226=4>{I1`0>{i01k1<7?tH2a7?xh?0k0;6<uG3b68yk>?k3:1=vF<c59~j=>c290:wE=l4:m<=c=83;pD>m;;|l;<c<728qC?n:4}o::4?6=9rB8o95rn9;2>5<6sA9h86sa88094?7|@:i?7p`79283>4}O;j>0qc664;295~N4k=1vb57::182M5d<2we44850;3xL6e33td35:4?:0yK7f2<ug2247>51zJ0g1=zf1326=4>{I1`0>{i00k1<7?tH2a7?xh?1k0;6<uG3b68yk>>k3:1=vF<c59~j=?c290:wE=l4:m<<c=83;pD>m;;|l;=c<728qC?n:4}o:b4?6=9rB8o95rn9c2>5<6sA9h86sa8`094?7|@:i?7p`7a283>4}O;j>0qc6n4;295~N4k=1vb5o::182M5d<2we4l850;3xL6e33td3m:4?:0yK7f2<ug2j47>51zJ0g1=zf1k26=4>{I1`0>{i0hk1<7?tH2a7?xh?ik0;6<uG3b68yk>fk3:1=vF<c59~j=gc290:wE=l4:m<dc=83;pD>m;;|l;ec<728qC?n:4}o:a4?6=9rB8o95rn9`2>5<6sA9h86sa8c094?7|@:i?7p`7b283>4}O;j>0qc6m4;295~N4k=1vb5l::182M5d<2we4o850;3xL6e33td3n:4?:0yK7f2<ug2i47>51zJ0g1=zf1h26=4>{I1`0>{i0kk1<7?tH2a7?xh?jk0;6<uG3b68yk>ek3:1=vF<c59~j=dc290:wE=l4:m<gc=83;pD>m;;|~yEFDsh<>69>i25f;exFGJr:vLM^t}AB
\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v new file mode 100644 index 000000000..b3d994ae8 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v @@ -0,0 +1,169 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating +// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_36to18( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty); + + +input rst; +input wr_clk; +input rd_clk; +input [35 : 0] din; +input wr_en; +input rd_en; +output [17 : 0] dout; +output full; +output empty; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(18), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(0), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(509), + .C_PROG_FULL_THRESH_NEGATE_VAL(508), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(1024), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(10), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .RD_DATA_COUNT(), + .WR_DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo new file mode 100644 index 000000000..e93be1591 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo @@ -0,0 +1,51 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_36to18 YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [17 : 0] + .full(full), + .empty(empty)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating +// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco new file mode 100644 index 000000000..d3115e7d5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Thu Aug 12 21:06:13 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk_36to18 +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=509 +CSET full_threshold_negate_value=508 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=18 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: a4e70980 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise new file mode 100644 index 000000000..cfe983130 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise @@ -0,0 +1,72 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="fifo_xlnx_512x36_2clk_36to18.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation"/> + <association xil_pn:name="Implementation"/> + </file> + <file xil_pn:name="fifo_xlnx_512x36_2clk_36to18.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation"/> + <association xil_pn:name="Implementation"/> + <association xil_pn:name="PostMapSimulation"/> + <association xil_pn:name="PostRouteSimulation"/> + <association xil_pn:name="PostTranslateSimulation"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_36to18.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-08-12T14:06:16" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3646C65496E43142DA83C69469B5BF88" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt new file mode 100644 index 000000000..54c85b15e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt @@ -0,0 +1,12 @@ +# Output products list for <fifo_xlnx_512x36_2clk_36to18> +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_36to18.gise +fifo_xlnx_512x36_2clk_36to18.ngc +fifo_xlnx_512x36_2clk_36to18.v +fifo_xlnx_512x36_2clk_36to18.veo +fifo_xlnx_512x36_2clk_36to18.xco +fifo_xlnx_512x36_2clk_36to18.xise +fifo_xlnx_512x36_2clk_36to18_flist.txt +fifo_xlnx_512x36_2clk_36to18_readme.txt +fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt new file mode 100644 index 000000000..3efc586bf --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt @@ -0,0 +1,47 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_36to18.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_36to18.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_36to18.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_36to18.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_36to18.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_36to18.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_36to18_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_36to18_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_512x36_2clk_36to18_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl new file mode 100644 index 000000000..5161c1826 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_xlnx_512x36_2clk_36to18_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_xlnx_512x36_2clk_36to18_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_36to18 +} +# ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_36to18 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/extramfifo/.gitignore b/fpga/usrp2/extramfifo/.gitignore new file mode 100644 index 000000000..94bbf6dcc --- /dev/null +++ b/fpga/usrp2/extramfifo/.gitignore @@ -0,0 +1,3 @@ +fifo_extram36_tb +fifo_extram_tb +*.vcd diff --git a/fpga/usrp2/extramfifo/Makefile.srcs b/fpga/usrp2/extramfifo/Makefile.srcs new file mode 100644 index 000000000..7cd49f4f6 --- /dev/null +++ b/fpga/usrp2/extramfifo/Makefile.srcs @@ -0,0 +1,16 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Extram Sources +################################################## +EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extramfifo/, \ +ext_fifo.v \ +nobl_if.v \ +nobl_fifo.v \ +icon.v \ +icon.xco \ +ila.v \ +ila.xco \ +)) diff --git a/fpga/usrp2/extramfifo/ext_fifo.v b/fpga/usrp2/extramfifo/ext_fifo.v new file mode 100644 index 000000000..2af59a75d --- /dev/null +++ b/fpga/usrp2/extramfifo/ext_fifo.v @@ -0,0 +1,123 @@ +// +// FIFO backed by an off chip ZBT/NoBL SRAM. +// +// This module and its sub-hierarchy implment a FIFO capable of sustaining +// a data throughput rate of at least int_clk/2 * 36bits and bursts of int_clk * 36bits. +// +// This has been designed and tested for an int_clk of 100MHz and an ext_clk of 125MHz, +// your milage may vary with other clock ratio's especially those where int_clk < ext_clk. +// Testing has also exclusively used a rst signal synchronized to int_clk. +// +// Interface operation mimics a Xilinx FIFO configured as "First Word Fall Through", +// though signal naming differs. +// +// For FPGA use registers interfacing directly with signals prefixed "RAM_*" should be +// packed into the IO ring. +// + + //`define NO_EXT_FIFO + +module ext_fifo + #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) + ( + input int_clk, + input ext_clk, + input rst, + input [EXT_WIDTH-1:0] RAM_D_pi, + output [EXT_WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [RAM_DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + input [INT_WIDTH-1:0] datain, + input src_rdy_i, // WRITE + output dst_rdy_o, // not FULL + output [INT_WIDTH-1:0] dataout, + output src_rdy_o, // not EMPTY + input dst_rdy_i, // READ + output reg [31:0] debug, + output reg [31:0] debug2 + ); + + wire [EXT_WIDTH-1:0] write_data; + wire [EXT_WIDTH-1:0] read_data; + wire full1, empty1; + wire almost_full2, full2, empty2; + wire [INT_WIDTH-1:0] data_to_fifo; + wire [INT_WIDTH-1:0] data_from_fifo; + wire [FIFO_DEPTH-1:0] capacity; + + + // FIFO buffers data from UDP engine into external FIFO clock domain. + fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( + .rst(rst), + .wr_clk(int_clk), + .rd_clk(ext_clk), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(space_avail&~empty1), + .dout(write_data), // Bus [17 : 0] + .full(full1), + .empty(empty1)); + + assign dst_rdy_o = ~full1; + +`ifdef NO_EXT_FIFO + assign space_avail = ~full2; + assign data_avail = ~empty1; + assign read_data = write_data; +`else + + // External FIFO running at ext clock rate and 18 bit width. + nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH)) + nobl_fifo_i1 + ( + .clk(ext_clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .write_data(write_data), + .write_strobe(~empty1 ), + .space_avail(space_avail), + .read_data(read_data), + .read_strobe(~almost_full2), + .data_avail(data_avail), + .capacity(capacity) + ); +`endif // !`ifdef NO_EXT_FIFO + + + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. + fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [17 : 0] + .wr_en(data_avail), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .prog_full(almost_full2), + .empty(empty2)); + assign src_rdy_o = ~empty2; + + always @ (posedge int_clk) + debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; + + always @ (posedge ext_clk) + debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; + + always@ (posedge ext_clk) +// debug2[31:0] <= {write_data[15:0],read_data[15:0]}; + debug2[31:0] <= 0; +endmodule // ext_fifo diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.cmd b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd new file mode 100644 index 000000000..521f88f21 --- /dev/null +++ b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd @@ -0,0 +1,12 @@ +/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v +-y . +-y ../coregen/ +-y ../fifo +-y ../models +-y /home/ianb/usrp-fpga/usrp2/sdr_lib +-y /home/ianb/usrp-fpga/usrp2/control_lib +-y /home/ianb/usrp-fpga/usrp2/models +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib + diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.prj b/fpga/usrp2/extramfifo/ext_fifo_tb.prj new file mode 100644 index 000000000..a11a15b2f --- /dev/null +++ b/fpga/usrp2/extramfifo/ext_fifo_tb.prj @@ -0,0 +1,9 @@ +verilog work "./ext_fifo_tb.v" +verilog work "./ext_fifo.v" +verilog work "./nobl_fifo.v" +verilog work "./nobl_if.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v" +verilog work "../models/CY7C1356C/cy1356.v" +verilog work "../models/idt71v65603s150.v" +verilog work "$XILINX/verilog/src/glbl.v" diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.sh b/fpga/usrp2/extramfifo/ext_fifo_tb.sh new file mode 100644 index 000000000..dcfede37a --- /dev/null +++ b/fpga/usrp2/extramfifo/ext_fifo_tb.sh @@ -0,0 +1,2 @@ +#fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb +iverilog -c ext_fifo_tb.cmd -o ext_fifo_tb ext_fifo_tb.v diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.v b/fpga/usrp2/extramfifo/ext_fifo_tb.v new file mode 100644 index 000000000..0eda89769 --- /dev/null +++ b/fpga/usrp2/extramfifo/ext_fifo_tb.v @@ -0,0 +1,378 @@ +`timescale 1ns / 1ps +`define INT_WIDTH 36 +`define EXT_WIDTH 18 +`define RAM_DEPTH 19 +`define FIFO_DEPTH 8 +`define DUMP_VCD_FULL + +module ext_fifo_tb(); + + + reg int_clk; + reg ext_clk; + reg rst; + + + + wire [`EXT_WIDTH-1:0] RAM_D_pi; + wire [`EXT_WIDTH-1:0] RAM_D_po; + wire [`EXT_WIDTH-1:0] RAM_D; + wire RAM_D_poe; + wire [`RAM_DEPTH-1:0] RAM_A; + wire RAM_WEn; + wire RAM_CENn; + wire RAM_LDn; + wire RAM_OEn; + wire RAM_CE1n; + reg [`INT_WIDTH-1:0] datain; + reg src_rdy_i; // WRITE + wire dst_rdy_o; // not FULL + wire [`INT_WIDTH-1:0] dataout; + reg [`INT_WIDTH-1:0] ref_dataout; + wire src_rdy_o; // not EMPTY + reg dst_rdy_i; + integer ether_frame; + + + // Clocks + // Int clock is 100MHz + // Ext clock is 125MHz + initial + begin + int_clk <= 0; + ext_clk <= 0; + ref_dataout <= 1; + src_rdy_i <= 0; + dst_rdy_i <= 0; + end + + always + #5 int_clk <= ~int_clk; + + always + #4 ext_clk <= ~ext_clk; + + initial + begin + datain <= 0; + ether_frame <= 0; + + rst <= 1; + repeat (5) @(negedge int_clk); + rst <= 0; + @(negedge int_clk); + while (datain < 10000) + begin + @(negedge int_clk); + datain <= datain + dst_rdy_o; + src_rdy_i <= dst_rdy_o; + // Simulate inter-frame time + if (ether_frame == 1500) + begin + ether_frame <= 0; + repeat(1600) + begin + @(negedge int_clk); + src_rdy_i <= 0; + end + end + else + ether_frame <= ether_frame + dst_rdy_o; + end + end // initial begin + + + initial + begin + repeat (5) @(negedge int_clk); + dst_rdy_i <= 1; + + while (src_rdy_o !== 1) + @(negedge int_clk); + + // Fall through fifo, first output already valid + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); + ref_dataout <= ref_dataout + src_rdy_o ; + + // Decimate by 16 rate + while (ref_dataout < 2000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(14) @(negedge int_clk); + end // while (ref_dataout < 10000) + // Decimate by 8 rate + while (ref_dataout < 4000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(6) @(negedge int_clk); + end // while (ref_dataout < 10000) + // Decimate by 4 rate + while (ref_dataout < 6000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(2) @(negedge int_clk); + end // while (ref_dataout < 10000) + // Max rate + while (ref_dataout < 10000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); + + end // while (ref_dataout < 10000) + + @(negedge int_clk); + $finish; + + end + + +/* -----\/----- EXCLUDED -----\/----- + + initial + begin + rst <= 1; + repeat (5) @(negedge int_clk); + rst <= 0; + @(negedge int_clk); + repeat (4000) + begin + @(negedge int_clk); + datain <= datain + dst_rdy_o; + src_rdy_i <= dst_rdy_o; +// @(negedge int_clk); +// src_rdy_i <= 0; +// @(negedge int_clk); +// dst_rdy_i <= src_rdy_o; +// @(negedge int_clk); +// dst_rdy_i <= 0; +// repeat (2) @(negedge int_clk); + end // repeat (1000) + // Fall through fifo, first output already valid + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + repeat (1000) + begin + @(negedge int_clk); + datain <= datain + dst_rdy_o ; + src_rdy_i <= dst_rdy_o; + @(negedge int_clk); + src_rdy_i <= 0; + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); + dst_rdy_i <= 0; +// repeat (2) @(negedge int_clk); + end // repeat (1000) + repeat (1000) + begin +// @(negedge int_clk); +// datain <= datain + 1; +// src_rdy_i <= 1; +// @(negedge int_clk); +// src_rdy_i <= 0; + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); + dst_rdy_i <= 0; +// repeat (2) @(negedge int_clk); + end // repeat (1000) + + $finish; + + end // initial begin + + + -----/\----- EXCLUDED -----/\----- */ + /////////////////////////////////////////////////////////////////////////////////// + // Simulation control // + /////////////////////////////////////////////////////////////////////////////////// + `ifdef DUMP_LX2_TOP + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.lx2"); + $dumpvars(1,ext_fifo_tb); + end + `endif + + `ifdef DUMP_LX2_FULL + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.lx2"); + $dumpvars(0,ext_fifo_tb); + end + `endif + + `ifdef DUMP_VCD_TOP + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(1,ext_fifo_tb); + end + `endif + + `ifdef DUMP_VCD_TOP_PLUS_NEXT + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(2,ext_fifo_tb); + end + `endif + + + `ifdef DUMP_VCD_FULL + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(0,ext_fifo_tb); + end + `endif + + // Update display every 10 us + always #10000 $monitor("Time in uS ",$time/1000); + + wire [`EXT_WIDTH-1:0] RAM_D_pi_ext; + wire [`EXT_WIDTH-1:0] RAM_D_po_ext; + wire [`EXT_WIDTH-1:0] RAM_D_ext; + wire RAM_D_poe_ext; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi_ext[i]), + .I(RAM_D_po_ext[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe_ext) + ); + end // block: gen_RAM_D_IO + + endgenerate + + wire [`RAM_DEPTH-1:0] RAM_A_ext; + wire RAM_WEn_ext,RAM_LDn_ext,RAM_CE1n_ext,RAM_OEn_ext,RAM_CENn_ext; + + assign #1 RAM_D_pi = RAM_D_pi_ext; + + assign #1 RAM_D_po_ext = RAM_D_po; + + assign #1 RAM_D_poe_ext = RAM_D_poe; + + assign #2 RAM_WEn_ext = RAM_WEn; + + assign #2 RAM_LDn_ext = RAM_LDn; + + assign #2 RAM_CE1n_ext = RAM_CE1n; + + assign #2 RAM_OEn_ext = RAM_OEn; + + assign #2 RAM_CENn_ext = RAM_CENn; + + assign #2 RAM_A_ext = RAM_A; + + + + idt71v65603s150 idt71v65603s150_i1 + ( + .A(RAM_A_ext[17:0]), + .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) + .bw1_(1'b0), + .bw2_(1'b0), + .bw3_(1'b1), + .bw4_(1'b1), // byte write enables (low) + .ce1_(RAM_CE1n_ext), + .ce2(1'b1), + .ce2_(1'b0), // chip enables + .cen_(RAM_CENn_ext), // clock enable (low) + .clk(ext_clk), // clock + .IO({RAM_D[16:9],RAM_D[7:0]}), + .IOP({RAM_D[17],RAM_D[8]}), // data bus + .lbo_(1'b0), // linear burst order (low) + .oe_(RAM_OEn_ext), // output enable (low) + .r_w_(RAM_WEn_ext) + ); // read (high) / write (low) + +/* -----\/----- EXCLUDED -----\/----- + + + cy1356 cy1356_i1 + ( .d(RAM_D), + .clk(ext_clk), + .a(RAM_A_ext), + .bws(2'b00), + .we_b(RAM_WEn_ext), + .adv_lb(RAM_LDn_ext), + .ce1b(RAM_CE1n_ext), + .ce2(1'b1), + .ce3b(1'b0), + .oeb(RAM_OEn_ext), + .cenb(RAM_CENn_ext), + .mode(1'b0) + ); + -----/\----- EXCLUDED -----/\----- */ + + + ext_fifo + #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.RAM_DEPTH(`RAM_DEPTH),.FIFO_DEPTH(`FIFO_DEPTH)) + ext_fifo_i1 + ( + .int_clk(int_clk), + .ext_clk(ext_clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain(datain), + .src_rdy_i(src_rdy_i), // WRITE + .dst_rdy_o(dst_rdy_o), // not FULL + .dataout(dataout), + .src_rdy_o(src_rdy_o), // not EMPTY + .dst_rdy_i(dst_rdy_i) + ); + +endmodule // ext_fifo_tb diff --git a/fpga/usrp2/extramfifo/fifo_extram.v b/fpga/usrp2/extramfifo/fifo_extram.v new file mode 100644 index 000000000..4e1f40371 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram.v @@ -0,0 +1,188 @@ + +// Everything on sram_clk + +module fifo_extram + (input reset, input clear, + input [17:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input [15:0] occ_in, + output [17:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input [15:0] space_in, + input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we, + output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, + output sram_mode, output sram_zz); + + localparam AWIDTH = 19; // 1 MB in x18 + localparam RAMSIZE = ((1<<AWIDTH) - 1); + + wire do_store, do_retrieve; + reg [1:0] do_store_del, do_retr_del; + + reg [AWIDTH-1:0] addr_retrieve, addr_store; + always @(posedge sram_clk) + if(reset | clear) + addr_retrieve <= 0; + else if (do_retrieve) + addr_retrieve <= addr_retrieve + 1; + + always @(posedge sram_clk) + if(reset | clear) + addr_store <= 0; + else if(do_store) + addr_store <= addr_store + 1; + + //wire [AWIDTH-1:0] fullness = (addr_store - addr_retrieve); + reg [AWIDTH-1:0] fullness; + always @(posedge sram_clk) + if(reset | clear) + fullness <= 0; + else if(do_store) + fullness <= fullness + 1; + else if(do_retrieve) + fullness <= fullness - 1; + + // wire empty = (fullness == 0); + //wire full = (fullness == RAMSIZE); // 19'h7FF); + reg empty, full; + + // The math in the following functions is 'AWIDTH wide. Use + // continuous assignments to prevent the numbers from being + // promoted to 32-bit (which would make it wrap wrong). + // + wire [AWIDTH-1:0] addr_retrieve_p1, addr_store_p2; + assign addr_retrieve_p1 = addr_retrieve + 1; + assign addr_store_p2 = addr_store + 2; + + always @(posedge sram_clk) + if(reset | clear) + empty <= 1; + else if(do_store) + empty <= 0; + else if(do_retrieve & (/*(addr_retrieve + 1)*/ addr_retrieve_p1 == addr_store)) + empty <= 1; + + always @(posedge sram_clk) + if(reset | clear) + full <= 0; + else if(do_retrieve) + full <= 0; + else if(do_store & (/*(addr_store+2)*/ addr_store_p2 == addr_retrieve)) + full <= 1; + + reg can_store; + always @* + if(full | ~src_rdy_i) + can_store <= 0; + else if(do_store_del == 0) + can_store <= 1; + else if((do_store_del == 1) || (do_store_del == 2)) + can_store <= (occ_in > 1); + else + can_store <= (occ_in > 2); + + reg can_retrieve; + always @* + if(empty | ~dst_rdy_i) + can_retrieve <= 0; + else if(do_retr_del == 0) + can_retrieve <= 1; + else if((do_retr_del == 1) || (do_retr_del == 2)) + can_retrieve <= (space_in > 1); + else + can_retrieve <= (space_in > 2); + + reg [1:0] state; + localparam IDLE_STORE_NEXT = 0; + localparam STORE = 1; + localparam IDLE_RETR_NEXT = 2; + localparam RETRIEVE = 3; + + reg [7:0] countdown; + wire countdown_done = (countdown == 0); + + localparam CYCLE_SIZE = 6; + + assign do_store = can_store & (state == STORE); + assign do_retrieve = can_retrieve & (state == RETRIEVE); + always @(posedge sram_clk) + if(reset) + do_store_del <= 0; + else + do_store_del <= {do_store_del[0],do_store}; + + always @(posedge sram_clk) + if(reset) + do_retr_del <= 0; + else + do_retr_del <= {do_retr_del[0],do_retrieve}; + + always @(posedge sram_clk) + if(reset | clear) + begin + state <= IDLE_STORE_NEXT; + countdown <= 0; + end + else + case(state) + IDLE_STORE_NEXT : + if(can_store) + begin + state <= STORE; + countdown <= CYCLE_SIZE; + end + else if(can_retrieve) + begin + state <= RETRIEVE; + countdown <= CYCLE_SIZE; + end + STORE : + if(~can_store | (can_retrieve & countdown_done)) + state <= IDLE_RETR_NEXT; + else if(~countdown_done) + countdown <= countdown - 1; + IDLE_RETR_NEXT : + if(can_retrieve) + begin + state <= RETRIEVE; + countdown <= CYCLE_SIZE; + end + else if(can_store) + begin + state <= STORE; + countdown <= CYCLE_SIZE; + end + RETRIEVE : + if(~can_retrieve | (can_store & countdown_done)) + state <= IDLE_STORE_NEXT; + else if(~countdown_done) + countdown <= countdown - 1; + endcase // case (state) + + // RAM wires + assign sram_bw = 0; + assign sram_adv = 0; + assign sram_mode = 0; + assign sram_zz = 0; + assign sram_ce = 0; + + assign sram_a = (state==STORE) ? addr_store : addr_retrieve; + assign sram_we = ~do_store; + assign sram_oe = ~do_retr_del[1]; + assign my_oe = do_store_del[1] & sram_oe; + assign sram_d = my_oe ? datain : 18'bz; + + // FIFO wires + assign dataout = sram_d; + assign src_rdy_o = do_retr_del[1]; + assign dst_rdy_o = do_store_del[1]; + +endmodule // fifo_extram + + + //wire have_1 = (fullness == 1); + //wire have_2 = (fullness == 2); + //wire have_atleast_1 = ~empty; + //wire have_atleast_2 = ~(empty | have_1); + //wire have_atleast_3 = ~(empty | have_1 | have_2); + //wire full_minus_1 = (fullness == (RAMSIZE-1)); // 19'h7FE); + //wire full_minus_2 = (fullness == (RAMSIZE-2)); // 19'h7FD); + //wire spacefor_atleast_1 = ~full; + //wire spacefor_atleast_2 = ~(full | full_minus_1); + //wire spacefor_atleast_3 = ~(full | full_minus_1 | full_minus_2); diff --git a/fpga/usrp2/extramfifo/fifo_extram36.v b/fpga/usrp2/extramfifo/fifo_extram36.v new file mode 100644 index 000000000..29342fdc4 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram36.v @@ -0,0 +1,47 @@ + +// 18 bit interface means we either can't handle errors or can't handle odd lengths +// unless we go to heroic measures + +module fifo_extram36 + (input clk, input reset, input clear, + input [35:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we, + output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, output sram_mode, + output sram_zz); + + wire [17:0] f18_data_1, f18_data_2, f18_data_3, f18_data_4; + wire f18_src_rdy_1, f18_dst_rdy_1, f18_src_rdy_2, f18_dst_rdy_2; + wire f18_src_rdy_3, f18_dst_rdy_3, f18_src_rdy_4, f18_dst_rdy_4; + + fifo36_to_fifo18 f36_to_f18 + (.clk(clk), .reset(reset), .clear(clear), + .f36_datain(datain), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .f18_dataout(f18_data_1), .f18_src_rdy_o(f18_src_rdy_1), .f18_dst_rdy_i(f18_dst_rdy_1) ); + + wire [15:0] f1_occ, f2_space; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_in + (.wclk(clk), .datain(f18_data_1), .src_rdy_i(f18_src_rdy_1), .dst_rdy_o(f18_dst_rdy_1), .space(), + .rclk(sram_clk), .dataout(f18_data_2), .src_rdy_o(f18_src_rdy_2), .dst_rdy_i(f18_dst_rdy_2), .short_occupied(f1_occ), + .arst(reset) ); + + fifo_extram fifo_extram + (.reset(reset), .clear(clear), + .datain(f18_data_2), .src_rdy_i(f18_src_rdy_2), .dst_rdy_o(f18_dst_rdy_2), .space(), .occ_in(f1_occ), + .dataout(f18_data_3), .src_rdy_o(f18_src_rdy_3), .dst_rdy_i(f18_dst_rdy_3), .occupied(), .space_in(f2_space), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_out + (.wclk(sram_clk), .datain(f18_data_3), .src_rdy_i(f18_src_rdy_3), .dst_rdy_o(f18_dst_rdy_3), .short_space(f2_space), + .rclk(clk), .dataout(f18_data_4), .src_rdy_o(f18_src_rdy_4), .dst_rdy_i(f18_dst_rdy_4), .occupied(), + .arst(reset) ); + + fifo18_to_fifo36 f18_to_f36 + (.clk(clk), .reset(reset), .clear(clear), + .f18_datain(f18_data_4), .f18_src_rdy_i(f18_src_rdy_4), .f18_dst_rdy_o(f18_dst_rdy_4), + .f36_dataout(dataout), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i) ); + +endmodule // fifo_extram36 diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.build b/fpga/usrp2/extramfifo/fifo_extram36_tb.build new file mode 100755 index 000000000..ac9369758 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram36_tb.build @@ -0,0 +1 @@ +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.v b/fpga/usrp2/extramfifo/fifo_extram36_tb.v new file mode 100644 index 000000000..e5f8cef4c --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram36_tb.v @@ -0,0 +1,475 @@ +`timescale 1ns/1ns + +module fifo_extram36_tb(); + + reg clk = 0; + reg sram_clk = 0; + reg rst = 1; + reg clear = 0; + + reg Verbose = 0; // + integer ErrorCount = 0; + + initial #1000 rst = 0; +// always #125 clk = ~clk; + task task_CLK; + reg [7:0] ran; + begin + while (1) begin + ran = $random; + if (ran[1]) + #62 clk = ~clk; + else + #63 clk = !clk; + end + end + endtask // task_CLK + initial task_CLK; + +// always #100 sram_clk = ~sram_clk; + task task_SSRAM_clk; + reg [7:0] ran; + begin + while (1) begin + ran = $random; + if (ran[0]) + #49 sram_clk = ~sram_clk; + else + #51 sram_clk = ~sram_clk; + end + end + endtask // task_SSRAM_clk + initial task_SSRAM_clk; + + reg [31:0] f36_data = 32'hX; + reg [1:0] f36_occ = 0; + reg f36_sof = 0, f36_eof = 0; + + wire [35:0] f36_in = {1'b0,f36_occ,f36_eof,f36_sof,f36_data}; + reg src_rdy_f36i = 0; + wire dst_rdy_f36i; + + wire [35:0] f36_out; + wire src_rdy_f36o; + reg dst_rdy_f36o = 0; + + wire [17:0] sram_d; + wire [18:0] sram_a; + wire [1:0] sram_bw; + wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz; + + reg [31:0] ScoreBoard [524288:0]; + reg [18:0] put_index = 0; + reg [18:0] get_index = 0; + +// integer put_index = 0; +// integer get_index = 0; + + wire [15:0] DUT_space, DUT_occupied; + + fifo_extram36 fifo_extram36 + (.clk(clk), .reset(rst), .clear(clear), + .datain(f36_in), .src_rdy_i(src_rdy_f36i), .dst_rdy_o(dst_rdy_f36i), .space(DUT_space), + .dataout(f36_out), .src_rdy_o(src_rdy_f36o), .dst_rdy_i(dst_rdy_f36o), .occupied(DUT_occupied), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + +`define idt 1 +`ifdef idt + wire [15:0] dummy16; + wire [1:0] dummy2; + + idt71v65603s150 + ram_model(.A(sram_a[17:0]), + .adv_ld_(sram_adv), // advance (high) / load (low) + .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low) + .ce1_(0), .ce2(1), .ce2_(0), // chip enables + .cen_(sram_ce), // clock enable (low) + .clk(sram_clk), // clock + .IO({dummy16,sram_d[15:0]}), + .IOP({dummy2,sram_d[17:16]}), // data bus + .lbo_(sram_mode), // linear burst order (low) + .oe_(sram_oe), // output enable (low) + .r_w_(sram_we)); // read (high) / write (low) +`else + cy1356 ram_model(.d(sram_d),.clk(~sram_clk),.a(sram_a), + .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv), + .ce1b(0),.ce2(1),.ce3b(0), + .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) ); +`endif + + task task_SSRAMMonitor; + reg last_mode; + reg last_clock; + reg last_load; + reg [18:0] sram_addr; + + begin + last_mode = 1'bX; + last_clock = 1'bX; + last_load = 1'bX; + + @ (posedge Verbose); + $dumpvars(0,fifo_extram36_tb); + + $display("%t:%m\t*** Task Started",$time); + while (1) @ (posedge sram_clk) begin + if (sram_mode !== last_mode) begin + $display("%t:%m\tSSRAM mode: %b",$time,sram_mode); + last_mode = sram_mode; + end + if (sram_adv !== last_load) begin + $display("%t:%m\tSSRAM adv/load: %b",$time,sram_adv); + last_load = sram_adv; + end + if (sram_ce !== last_clock) begin + $display("%t:%m\tSSRAM clock enable: %b",$time,sram_ce); + last_clock = sram_ce; + end + if (sram_ce == 1'b0) begin + if (sram_adv == 1'b0) begin +// $display("%t:%m\tSSRAM Address Load A=%h",$time,sram_a); + sram_addr = sram_a; + end else begin + sram_addr = sram_addr + 1; + end + if (sram_oe == 1'b0) begin + $display("%t:%m\tSSRAM Read Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d); + end + if (sram_we == 1'b0) begin + $display("%t:%m\tSSRAM Write Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d); + end + if ((sram_we == 1'b0) && (sram_oe == 1'b0)) begin + $display("%t:%m\t*** ERROR: _oe and _we both active",$time); + end + + end // if (sram_ce == 1'b0) + + end // always @ (posedge sram_clk) + end + endtask // task_SSRAMMonitor + + task ReadFromFIFO36; + begin + $display("%t: Read from FIFO36",$time); + #1 dst_rdy_f36o <= 1; + while(1) + begin + while(~src_rdy_f36o) + @(posedge clk); + $display("%t: Read: %h>",$time,f36_out); + @(posedge clk); + end + end + endtask // ReadFromFIFO36 + + initial dst_rdy_f36o = 0; + + task task_ReadFIFO36; + reg [7:0] ran; + begin + $display("%t:%m\t*** Task Started",$time); + while (1) begin + // Read on one of four clocks + #5 dst_rdy_f36o <= 1; + @(posedge clk); + if (src_rdy_f36o) begin + if (f36_out[31:0] != ScoreBoard[get_index]) begin + $display("%t:%m\tFIFO Get Error: R:%h, E:%h (%h)",$time,f36_out[31:0],ScoreBoard[get_index],get_index); + ErrorCount = ErrorCount + 1; + end else begin + if (Verbose) + $display("%t:%m\t(%5h) %o>",$time,get_index,f36_out); + end + get_index = get_index+1; + end else begin + if (ErrorCount >= 192) + $finish; + end // else: !if(src_rdy_f36o) + + #10; + ran = $random; + if (ran[2:0] != 3'b000) begin + dst_rdy_f36o <= 0; + if (ran[2] != 1'b0) begin + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + if (ran[1] != 1'b0) begin + @(posedge clk); + @(posedge clk); + end + if (ran[0] != 1'b0) begin + @(posedge clk); + end + end + end // while (1) + end + + endtask // task_ReadFIFO36 + + + reg [15:0] count; + + task PutPacketInFIFO36; + input [31:0] data_start; + input [31:0] data_len; + + begin + count = 4; + src_rdy_f36i = 1; + f36_data = data_start; + f36_sof = 1; + f36_eof = 0; + f36_occ = 0; + + $display("%t: Put Packet in FIFO36",$time); + while(~dst_rdy_f36i) + #1; //@(posedge clk); + @(posedge clk); + + $display("%t: <%h PPI_FIFO36: Entered First Line",$time,f36_data); + f36_sof <= 0; + while(count+4 < data_len) + begin + f36_data = f36_data + 32'h01010101; + count = count + 4; + while(~dst_rdy_f36i) + #1; //@(posedge clk); + @(posedge clk); + $display("%t: <%h PPI_FIFO36: Entered New Line",$time,f36_data); + end + f36_data <= f36_data + 32'h01010101; + f36_eof <= 1; + if(count + 4 == data_len) + f36_occ <= 0; + else if(count + 3 == data_len) + f36_occ <= 3; + else if(count + 2 == data_len) + f36_occ <= 2; + else + f36_occ <= 1; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + f36_occ <= 0; + f36_eof <= 0; + f36_data <= 0; + src_rdy_f36i <= 0; + $display("%t: <%h PPI_FIFO36: Entered Last Line",$time,f36_data); + end + endtask // PutPacketInFIFO36 + + task task_WriteFIFO36; + integer i; + reg [7:0] ran; + + begin + f36_data = 32'bX; + if (rst != 1'b0) + @ (negedge rst); + $display("%t:%m\t*** Task Started",$time); + #10; + src_rdy_f36i = 1; + f36_data = $random; + for (i=0; i<64; i=i+0 ) begin + @ (posedge clk) ; + if (dst_rdy_f36i) begin + if (Verbose) + $display("%t:%m\t(%5h) %o<",$time,put_index,f36_in); + ScoreBoard[put_index] = f36_in[31:0]; + put_index = put_index + 1; + #5; + f36_data = $random; + i = i + 1; + end + ran = $random; + if (ran[1:0] != 2'b00) begin + @ (negedge clk); + src_rdy_f36i = 0; + #5; + @ (negedge clk) ; + src_rdy_f36i = 1; + end + end + src_rdy_f36i = 0; + f36_data = 32'bX; +// if (put_index > 19'h3ff00) +// Verbose = 1'b1; + + end + endtask // task_WriteFIFO36 + + initial $dumpfile("fifo_extram36_tb.vcd"); +// initial $dumpvars(0,fifo_extram36_tb); + initial $timeformat(-9, 0, " ns", 10); + initial task_SSRAMMonitor; + + initial + begin + @(negedge rst); + #40000; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); +// ReadFromFIFO36; + task_ReadFIFO36; + + end + + integer i; + + initial + begin + @(negedge rst); + @(posedge clk); + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + @(posedge clk); + @(posedge clk); +// PutPacketInFIFO36(32'hA0B0C0D0,12); + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); +// PutPacketInFIFO36(32'hE0F0A0B0,36); + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + for (i=0; i<8192; i = i+1) begin + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + end + +// $dumpvars(0,fifo_extram36_tb); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + + #100000000; + $finish; + + end + + + initial + begin + @(negedge rst); + f36_occ <= 0; + repeat (100) + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= 32'h10203040; + f36_sof <= 1; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= 32'h1F2F3F4F; + f36_sof <= 0; + f36_eof <= 1; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 0; + + + + end + +// initial #500000 $finish; +endmodule // fifo_extram_tb diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.build b/fpga/usrp2/extramfifo/fifo_extram_tb.build new file mode 100755 index 000000000..5607c8691 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram_tb.build @@ -0,0 +1 @@ +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.v b/fpga/usrp2/extramfifo/fifo_extram_tb.v new file mode 100644 index 000000000..73550d9ca --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram_tb.v @@ -0,0 +1,134 @@ +module fifo_extram_tb(); + + reg clk = 0; + reg sram_clk = 0; + reg reset = 1; + reg clear = 0; + + initial #1000 reset = 0; + always #125 clk = ~clk; + always #100 sram_clk = ~sram_clk; + + reg [15:0] f18_data = 0; + reg f18_sof = 0, f18_eof = 0; + + wire [17:0] f18_in = {f18_eof,f18_sof,f18_data}; + reg src_rdy_f18i = 0; + wire dst_rdy_f18i; + + wire [17:0] f18_out; + wire src_rdy_f18o; + reg dst_rdy_f18o = 0; + + wire [17:0] f18_int; + wire src_rdy_f18int, dst_rdy_f18int; + + wire [17:0] sram_d; + wire [18:0] sram_a; + wire [1:0] sram_bw; + wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz; + wire [15:0] f1_occ; + + fifo_short #(.WIDTH(18)) fifo_short + (.clk(sram_clk), .reset(reset), .clear(clear), + .datain(f18_in), .src_rdy_i(src_rdy_f18i), .dst_rdy_o(dst_rdy_f18i), .space(), + .dataout(f18_int), .src_rdy_o(src_rdy_f18int), .dst_rdy_i(dst_rdy_f18int), .occupied(f1_occ[4:0]) ); + + assign f1_occ[15:5] = 0; + + fifo_extram fifo_extram + (.reset(reset), .clear(clear), + .datain(f18_int), .src_rdy_i(src_rdy_f18int), .dst_rdy_o(dst_rdy_f18int), .space(), .occ_in(f1_occ), + .dataout(f18_out), .src_rdy_o(src_rdy_f18o), .dst_rdy_i(dst_rdy_f18o), .occupied(), .space_in(7), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + +`define idt 1 +`ifdef idt + wire [15:0] dummy16; + wire [1:0] dummy2; + + idt71v65603s150 + ram_model(.A(sram_a[17:0]), + .adv_ld_(sram_adv), // advance (high) / load (low) + .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low) + .ce1_(0), .ce2(1), .ce2_(0), // chip enables + .cen_(sram_ce), // clock enable (low) + .clk(sram_clk), // clock + .IO({dummy16,sram_d[15:0]}), + .IOP({dummy2,sram_d[17:16]}), // data bus + .lbo_(sram_mode), // linear burst order (low) + .oe_(sram_oe), // output enable (low) + .r_w_(sram_we)); // read (high) / write (low) +`else + cy1356 ram_model(.d(sram_d),.clk(sram_clk),.a(sram_a), + .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv), + .ce1b(0),.ce2(1),.ce3b(0), + .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) ); +`endif // !`ifdef idt + + always @(posedge sram_clk) + if(dst_rdy_f18o & src_rdy_f18o) + $display("Read: %h",f18_out); + + always @(posedge sram_clk) + if(dst_rdy_f18int & src_rdy_f18int) + $display("Write: %h",f18_int); + + initial $dumpfile("fifo_extram_tb.vcd"); + initial $dumpvars(0,fifo_extram_tb); + + task SendPkt; + input [15:0] data_start; + input [31:0] data_len; + begin + @(posedge sram_clk); + f18_data = data_start; + f18_sof = 1; + f18_eof = 0; + src_rdy_f18i = 1; + while(~dst_rdy_f18i) + #1; + @(posedge sram_clk); + repeat(data_len - 2) + begin + f18_data = f18_data + 16'h0101; + f18_sof = 0; + while(~dst_rdy_f18i) + @(posedge sram_clk); + + @(posedge sram_clk); + end + f18_data = f18_data + 16'h0101; + f18_eof = 1; + while(~dst_rdy_f18i) + #1; + @(posedge sram_clk); + src_rdy_f18i = 0; + f18_data = 0; + f18_eof = 0; + end + endtask // SendPkt + + initial + begin + @(negedge reset); + @(posedge sram_clk); + @(posedge sram_clk); + #10000; + @(posedge sram_clk); + SendPkt(16'hA0B0, 100); + #10000; + //SendPkt(16'hC0D0, 220); + end + + initial + begin + #20000; + dst_rdy_f18o = 1; + end + + initial #200000 $finish; +endmodule // fifo_extram_tb + diff --git a/fpga/usrp2/extramfifo/icon.v b/fpga/usrp2/extramfifo/icon.v new file mode 100644 index 000000000..6537e9340 --- /dev/null +++ b/fpga/usrp2/extramfifo/icon.v @@ -0,0 +1,1286 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.53d +// \ \ Application: netgen +// / / Filename: icon.v +// /___/ /\ Timestamp: Tue Jul 20 20:31:15 2010 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v +// Device : xc3s2000-fg456-5 +// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc +// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v +// # of Modules : 1 +// Design Name : icon +// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module icon ( +CONTROL0 +)/* synthesis syn_black_box syn_noprune=1 */; + inout [35 : 0] CONTROL0; + + // synthesis translate_off + + wire N1; + wire \U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ; + wire \U0/U_ICON/U_CMD/iSEL_n ; + wire \U0/U_ICON/U_CMD/iTARGET_CE ; + wire \U0/U_ICON/U_CTRL_OUT/iDATA_VALID ; + wire \U0/U_ICON/U_STAT/iCMD_GRP0_SEL ; + wire \U0/U_ICON/U_STAT/iDATA_VALID ; + wire \U0/U_ICON/U_STAT/iSTATCMD_CE ; + wire \U0/U_ICON/U_STAT/iSTATCMD_CE_n ; + wire \U0/U_ICON/U_STAT/iSTAT_HIGH ; + wire \U0/U_ICON/U_STAT/iSTAT_LOW ; + wire \U0/U_ICON/U_STAT/iTDO_next ; + wire \U0/U_ICON/U_SYNC/iDATA_CMD_n ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ; + wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ; + wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ; + wire \U0/U_ICON/iCORE_ID_SEL[0] ; + wire \U0/U_ICON/iCORE_ID_SEL[15] ; + wire \U0/U_ICON/iDATA_CMD ; + wire \U0/U_ICON/iDATA_CMD_n ; + wire \U0/U_ICON/iSEL ; + wire \U0/U_ICON/iSEL_n ; + wire \U0/U_ICON/iSYNC ; + wire \U0/U_ICON/iTDI ; + wire \U0/U_ICON/iTDO ; + wire \U0/U_ICON/iTDO_next ; + wire \U0/iSHIFT_OUT ; + wire \U0/iUPDATE_OUT ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ; + wire [11 : 8] \U0/U_ICON/U_CMD/iTARGET ; + wire [1 : 0] \U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL ; + wire [5 : 1] \U0/U_ICON/U_STAT/U_STAT_CNT/CI ; + wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/D ; + wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/S ; + wire [3 : 0] \U0/U_ICON/U_STAT/iSTAT ; + wire [5 : 0] \U0/U_ICON/U_STAT/iSTAT_CNT ; + wire [6 : 0] \U0/U_ICON/U_SYNC/iSYNC_WORD ; + wire [1 : 0] \U0/U_ICON/iCOMMAND_GRP ; + wire [15 : 0] \U0/U_ICON/iCOMMAND_SEL ; + wire [3 : 0] \U0/U_ICON/iCORE_ID ; + wire [15 : 15] \U0/U_ICON/iTDO_VEC ; + GND XST_GND ( + .G(CONTROL0[2]) + ); + VCC XST_VCC ( + .P(N1) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_TDI_reg ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/iTDI ), + .Q(CONTROL0[1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_TDO_reg ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/iTDO_next ), + .Q(\U0/U_ICON/iTDO ) + ); + FDC #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_iDATA_CMD ( + .C(\U0/iUPDATE_OUT ), + .CLR(\U0/U_ICON/iSEL_n ), + .D(\U0/U_ICON/iDATA_CMD_n ), + .Q(\U0/U_ICON/iDATA_CMD ) + ); + MUXF5 \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5 ( + .I0(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ), + .I1(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ), + .S(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iTDO_next ) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4 ( + .I0(CONTROL0[3]), + .I1(\U0/U_ICON/iCORE_ID [0]), + .I2(\U0/U_ICON/iCORE_ID [1]), + .I3(\U0/U_ICON/iCORE_ID [2]), + .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3 ( + .I0(\U0/U_ICON/iTDO_VEC [15]), + .I1(\U0/U_ICON/iCORE_ID [0]), + .I2(\U0/U_ICON/iCORE_ID [1]), + .I3(\U0/U_ICON/iCORE_ID [2]), + .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ) + ); + INV \U0/U_ICON/U_iSEL_n ( + .I(\U0/U_ICON/iSEL ), + .O(\U0/U_ICON/iSEL_n ) + ); + INV \U0/U_ICON/U_iDATA_CMD_n ( + .I(\U0/U_ICON/iDATA_CMD ), + .O(\U0/U_ICON/iDATA_CMD_n ) + ); + BSCAN_SPARTAN3 \U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS ( + .TDI(\U0/U_ICON/iTDI ), + .SHIFT(\U0/iSHIFT_OUT ), + .DRCK1(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ), + .DRCK2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ), + .RESET(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ), + .UPDATE(\U0/iUPDATE_OUT ), + .TDO1(\U0/U_ICON/iTDO ), + .TDO2(CONTROL0[2]), + .CAPTURE(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ), + .SEL1(\U0/U_ICON/iSEL ), + .SEL2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ) + ); + icon_bscan_bufg \U0/U_ICON/I_YES_BSCAN.U_BS/I_USE_SOFTBSCAN_EQ0.I_USE_XST_TCK_WORKAROUND_EQ1.U_ICON_BSCAN_BUFG ( + .DRCK_LOCAL_I(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ), + .DRCK_LOCAL_O(CONTROL0[0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC ( + .I0(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ), + .I1(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC ) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC_L ( + .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]), + .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]), + .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]), + .I3(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC_H ( + .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]), + .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]), + .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]), + .I3(CONTROL0[1]), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ) + ); + INV \U0/U_ICON/U_SYNC/U_iDATA_CMD_n ( + .I(\U0/U_ICON/iDATA_CMD ), + .O(\U0/U_ICON/U_SYNC/iDATA_CMD_n ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/U_SYNC ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_SYNC/iGOT_SYNC ), + .D(N1), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/iSYNC ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[2].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR ( + .C(CONTROL0[0]), + .D(CONTROL0[1]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[20]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[4]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [1]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[21]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [1]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[5]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [2]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[22]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [2]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [3]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[23]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [3]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[7]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [4]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[24]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [4]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[8]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [5]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[25]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [5]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[9]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [6]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[26]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [6]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[10]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [7]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[27]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [7]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[11]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [8]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[28]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [8]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[12]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [9]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[29]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [9]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[13]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [10]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[30]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [10]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[14]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [11]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[31]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [11]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[15]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [12]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[32]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [12]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[16]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [13]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[33]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [13]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[17]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [14]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[34]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [14]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[18]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [15]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[35]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [15]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[19]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/U_ICON/U_CTRL_OUT/U_CMDGRP1 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]) + ); + LUT2 #( + .INIT ( 4'h1 )) + \U0/U_ICON/U_CTRL_OUT/U_CMDGRP0 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_CTRL_OUT/U_DATA_VALID ( + .I0(\U0/U_ICON/iSYNC ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iCORE_ID_SEL[0] ) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0008 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0010 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0020 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0040 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0080 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0100 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h2000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h4000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[15].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iCORE_ID_SEL[15] ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[0].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [0]) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[1].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [1]) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[2].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [2]) + ); + LUT4 #( + .INIT ( 16'h0008 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[3].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [3]) + ); + LUT4 #( + .INIT ( 16'h0010 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[4].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [4]) + ); + LUT4 #( + .INIT ( 16'h0020 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[5].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [5]) + ); + LUT4 #( + .INIT ( 16'h0040 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[6].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [6]) + ); + LUT4 #( + .INIT ( 16'h0080 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[7].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [7]) + ); + LUT4 #( + .INIT ( 16'h0100 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[8].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [8]) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [9]) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[10].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [10]) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[11].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [11]) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[12].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [12]) + ); + LUT4 #( + .INIT ( 16'h2000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[13].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [13]) + ); + LUT4 #( + .INIT ( 16'h4000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[14].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [14]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[15].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [15]) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/U_ICON/U_CMD/U_TARGET_CE ( + .I0(\U0/U_ICON/iDATA_CMD ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_CMD/iTARGET_CE ) + ); + INV \U0/U_ICON/U_CMD/U_SEL_n ( + .I(\U0/U_ICON/iSEL ), + .O(\U0/U_ICON/U_CMD/iSEL_n ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCOMMAND_GRP [1]), + .Q(\U0/U_ICON/iCOMMAND_GRP [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [8]), + .Q(\U0/U_ICON/iCOMMAND_GRP [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [9]), + .Q(\U0/U_ICON/U_CMD/iTARGET [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [10]), + .Q(\U0/U_ICON/U_CMD/iTARGET [9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [11]), + .Q(\U0/U_ICON/U_CMD/iTARGET [10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [0]), + .Q(\U0/U_ICON/U_CMD/iTARGET [11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [1]), + .Q(\U0/U_ICON/iCORE_ID [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [2]), + .Q(\U0/U_ICON/iCORE_ID [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [3]), + .Q(\U0/U_ICON/iCORE_ID [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(CONTROL0[1]), + .Q(\U0/U_ICON/iCORE_ID [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [5]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]) + ); + MUXF6 \U0/U_ICON/U_STAT/U_TDO_next ( + .I0(\U0/U_ICON/U_STAT/iSTAT_LOW ), + .I1(\U0/U_ICON/U_STAT/iSTAT_HIGH ), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [5]), + .O(\U0/U_ICON/U_STAT/iTDO_next ) + ); + MUXF5 \U0/U_ICON/U_STAT/U_STAT_LOW ( + .I0(\U0/U_ICON/U_STAT/iSTAT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT [1]), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/iSTAT_LOW ) + ); + MUXF5 \U0/U_ICON/U_STAT/U_STAT_HIGH ( + .I0(\U0/U_ICON/U_STAT/iSTAT [2]), + .I1(\U0/U_ICON/U_STAT/iSTAT [3]), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/iSTAT_HIGH ) + ); + LUT4 #( + .INIT ( 16'h0101 )) + \U0/U_ICON/U_STAT/F_STAT[0].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [0]) + ); + LUT4 #( + .INIT ( 16'hC101 )) + \U0/U_ICON/U_STAT/F_STAT[1].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [1]) + ); + LUT4 #( + .INIT ( 16'h2100 )) + \U0/U_ICON/U_STAT/F_STAT[2].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [2]) + ); + LUT4 #( + .INIT ( 16'h1610 )) + \U0/U_ICON/U_STAT/F_STAT[3].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [3]) + ); + INV \U0/U_ICON/U_STAT/U_STATCMD_n ( + .I(\U0/U_ICON/U_STAT/iSTATCMD_CE ), + .O(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_STAT/U_STATCMD ( + .I0(\U0/U_ICON/U_STAT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[15] ), + .I3(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ), + .O(\U0/U_ICON/U_STAT/iSTATCMD_CE ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \U0/U_ICON/U_STAT/U_CMDGRP0 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_STAT/U_DATA_VALID ( + .I0(\U0/U_ICON/iSYNC ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_STAT/iDATA_VALID ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_TDO ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/iTDO_next ), + .Q(\U0/U_ICON/iTDO_VEC [15]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp2/extramfifo/icon.xco b/fpga/usrp2/extramfifo/icon.xco new file mode 100644 index 000000000..fda273149 --- /dev/null +++ b/fpga/usrp2/extramfifo/icon.xco @@ -0,0 +1,47 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Wed Jul 21 03:31:19 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a +# END Select +# BEGIN Parameters +CSET component_name=icon +CSET enable_jtag_bufg=true +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +GENERATE +# CRC: 799ba5a1 diff --git a/fpga/usrp2/extramfifo/ila.v b/fpga/usrp2/extramfifo/ila.v new file mode 100644 index 000000000..b0d8f8d0c --- /dev/null +++ b/fpga/usrp2/extramfifo/ila.v @@ -0,0 +1,5544 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.53d +// \ \ Application: netgen +// / / Filename: ila.v +// /___/ /\ Timestamp: Wed Jul 21 11:51:09 2010 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v +// Device : xc3s2000-fg456-5 +// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc +// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v +// # of Modules : 1 +// Design Name : ila +// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module ila ( + CLK, CONTROL, TRIG0, TRIG1, TRIG2, TRIG3 +)/* synthesis syn_black_box syn_noprune=1 */; + input CLK; + inout [35 : 0] CONTROL; + input [7 : 0] TRIG0; + input [7 : 0] TRIG1; + input [7 : 0] TRIG2; + input [3 : 0] TRIG3; + + // synthesis translate_off + + wire N0; + wire N1; + wire N38; + wire N39; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ; + wire \U0/I_NO_D.U_ILA/U_RST/HALT_pulse ; + wire \U0/I_NO_D.U_ILA/U_RST/POR ; + wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ; + wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ; + wire \U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ; + wire \U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ; + wire \U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/NS_load ; + wire \U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/TDO_next ; + wire \U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ; + wire \U0/I_NO_D.U_ILA/iARM ; + wire \U0/I_NO_D.U_ILA/iCAPTURE ; + wire \U0/I_NO_D.U_ILA/iCAP_DONE ; + wire \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ; + wire \U0/I_NO_D.U_ILA/iCAP_WR_EN ; + wire \U0/I_NO_D.U_ILA/iDATA_DOUT ; + wire \U0/I_NO_D.U_ILA/iSTAT_DOUT ; + wire \U0/I_NO_D.U_ILA/iTRIGGER ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED ; + wire [27 : 0] \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp ; + wire [13 : 1] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO ; + wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO ; + wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next ; + wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S ; + wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [4 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data ; + wire [16 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN ; + wire [0 : 0] \U0/I_NO_D.U_ILA/U_RST/iRESET ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_STAT/NS_dstat ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/STATE_dstat ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT ; + wire [9 : 1] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S ; + wire [16 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_TRIG/trigCondIn ; + wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES ; + wire [1 : 0] \U0/I_NO_D.U_ILA/iCAP_STATE ; + wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_WR_ADDR ; + wire [27 : 0] \U0/I_NO_D.U_ILA/iDATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/iRESET ; + wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy ; + wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut ; + wire [27 : 0] \U0/iTRIG_IN ; + GND XST_GND ( + .G(N0) + ); + VCC XST_VCC ( + .P(N1) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_HCMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_LCMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_SCNT_CMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE0 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ), + .R(\U0/I_NO_D.U_ILA/iRESET [7]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_EN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG0 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG1 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [7]), + .Q(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [1]) + ); + LUT3 #( + .INIT ( 8'h20 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG ( + .I0(\U0/I_NO_D.U_ILA/iTRIGGER ), + .I1(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .I2(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]), + .Q15(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ), + .R(N0), + .Q(\U0/I_NO_D.U_ILA/iCAP_DONE ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ) +, + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ) +, + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK1 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK0 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[14].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[13].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[12].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[10].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[9].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[7].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[4].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[1].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL2 ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL3 ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_CR ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[8].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[6].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[5].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[4].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[3].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[2].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATE1 ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATE0 ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_ARM ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ), + .R(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_TRIGGER ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ), + .R(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_FULL ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ), + .R(\U0/I_NO_D.U_ILA/iARM ), + .S(\U0/I_NO_D.U_ILA/iCAP_DONE ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_ECR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ), + .R(\U0/I_NO_D.U_ILA/iARM ), + .S(N1), + .Q(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE ( + .C(CONTROL[0]), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/iARM ), + .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .PRE(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ) + ); + LDC #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC ( + .CLR(\U0/I_NO_D.U_ILA/iARM ), + .D(N1), + .G(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RISING ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ), + .D(N1), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_TDO ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ), + .Q(\U0/I_NO_D.U_ILA/iSTAT_DOUT ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[5]), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(CONTROL[5]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/I_H2L.U_DOUT ( + .C(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]), + .R(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT1 ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT0 ( + .C(CONTROL[0]), + .CE(N1), + .D(CONTROL[5]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ) + ); + LUT4 #( + .INIT ( 16'hFBEA )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ) + ); + MUXF7 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_0 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD ( + .I0(CONTROL[4]), + .I1(CONTROL[5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ) + ); + INV \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD_n ( + .I(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSR ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .O(\NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0F22 )) + \U0/I_NO_D.U_ILA/U_STAT/U_NSL ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ), + .I3(\U0/I_NO_D.U_ILA/iRESET [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/NS_load ) + ); + LUT4 #( + .INIT ( 16'h0030 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[16].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]) + ); + LUT4 #( + .INIT ( 16'h1030 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[15].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[14].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]) + ); + LUT4 #( + .INIT ( 16'h1020 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[13].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[12].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]) + ); + LUT4 #( + .INIT ( 16'h1010 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[11].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[10].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]) + ); + LUT4 #( + .INIT ( 16'h100F )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[9].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]) + ); + LUT4 #( + .INIT ( 16'hFFF0 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[8].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[7].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]) + ); + LUT4 #( + .INIT ( 16'h3000 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[6].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]) + ); + LUT4 #( + .INIT ( 16'h001F )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[5].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]) + ); + LUT4 #( + .INIT ( 16'hF001 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[4].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]) + ); + LUT4 #( + .INIT ( 16'hB610 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[3].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]) + ); + LUT4 #( + .INIT ( 16'h2100 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[2].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]) + ); + LUT4 #( + .INIT ( 16'hC102 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[1].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]) + ); + LUT4 #( + .INIT ( 16'h0101 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[0].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]), + .I1(CONTROL[5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/U_POR ( + .C(CLK), + .D(N0), + .PRE(N0), + .Q(\U0/I_NO_D.U_ILA/U_RST/POR ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [0]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[1].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [1]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[2].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [1]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [2]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[3].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [2]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [3]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[4].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [3]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [4]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[5].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [4]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [5]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[6].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [5]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [6]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[7].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [6]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [7]) + ); + LUT3 #( + .INIT ( 8'hEF )) + \U0/I_NO_D.U_ILA/U_RST/U_PRST1 ( + .I0(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ), + .I1(\U0/I_NO_D.U_ILA/U_RST/POR ), + .I2(N1), + .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ) + ); + LUT4 #( + .INIT ( 16'hFFFE )) + \U0/I_NO_D.U_ILA/U_RST/U_PRST0 ( + .I0(N0), + .I1(\U0/I_NO_D.U_ILA/iCAP_DONE ), + .I2(N0), + .I3(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ), + .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/I_NO_D.U_ILA/U_RST/U_RST0 ( + .I0(\U0/I_NO_D.U_ILA/iARM ), + .I1(\U0/I_NO_D.U_ILA/iRESET [0]), + .O(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ), + .I1(CONTROL[13]), + .O(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[2].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[13]), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ), + .I1(CONTROL[12]), + .O(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[4].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ), + .Q(\U0/I_NO_D.U_ILA/iARM ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[2].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[12]), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(CONTROL[12]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [24]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [25]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [26]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [27]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[23]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[23]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_YES_MUXH.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [0]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [1]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [2]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [3]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [4]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [5]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [6]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [7]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[20]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[20]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [8]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [9]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [10]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [11]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [12]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [13]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [14]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [15]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[21]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[21]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [16]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [17]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [18]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [19]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [20]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [21]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [22]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [23]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[22]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[22]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]), + .Q(\U0/I_NO_D.U_ILA/iDATA [0]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]), + .Q(\U0/I_NO_D.U_ILA/iDATA [1]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]), + .Q(\U0/I_NO_D.U_ILA/iDATA [2]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]), + .Q(\U0/I_NO_D.U_ILA/iDATA [3]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]), + .Q(\U0/I_NO_D.U_ILA/iDATA [4]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]), + .Q(\U0/I_NO_D.U_ILA/iDATA [5]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]), + .Q(\U0/I_NO_D.U_ILA/iDATA [6]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]), + .Q(\U0/I_NO_D.U_ILA/iDATA [7]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]), + .Q(\U0/I_NO_D.U_ILA/iDATA [8]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]), + .Q(\U0/I_NO_D.U_ILA/iDATA [9]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]), + .Q(\U0/I_NO_D.U_ILA/iDATA [10]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]), + .Q(\U0/I_NO_D.U_ILA/iDATA [11]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]), + .Q(\U0/I_NO_D.U_ILA/iDATA [12]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]), + .Q(\U0/I_NO_D.U_ILA/iDATA [13]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]), + .Q(\U0/I_NO_D.U_ILA/iDATA [14]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]), + .Q(\U0/I_NO_D.U_ILA/iDATA [15]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]), + .Q(\U0/I_NO_D.U_ILA/iDATA [16]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]), + .Q(\U0/I_NO_D.U_ILA/iDATA [17]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]), + .Q(\U0/I_NO_D.U_ILA/iDATA [18]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]), + .Q(\U0/I_NO_D.U_ILA/iDATA [19]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]), + .Q(\U0/I_NO_D.U_ILA/iDATA [20]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]), + .Q(\U0/I_NO_D.U_ILA/iDATA [21]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]), + .Q(\U0/I_NO_D.U_ILA/iDATA [22]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]), + .Q(\U0/I_NO_D.U_ILA/iDATA [23]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]), + .Q(\U0/I_NO_D.U_ILA/iDATA [24]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]), + .Q(\U0/I_NO_D.U_ILA/iDATA [25]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]), + .Q(\U0/I_NO_D.U_ILA/iDATA [26]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]), + .Q(\U0/I_NO_D.U_ILA/iDATA [27]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [0]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [1]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [2]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [3]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [4]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [5]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [6]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [7]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [8]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [9]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [10]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [11]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [12]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [13]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [14]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [15]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [16]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [17]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [18]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [19]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [20]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [21]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [22]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [23]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [24]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [25]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [26]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [27]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_DOUT ( + .I0(\U0/I_NO_D.U_ILA/iSTAT_DOUT ), + .I1(\U0/I_NO_D.U_ILA/iDATA_DOUT ), + .I2(CONTROL[6]), + .O(CONTROL[3]) + ); + LUT1 #( + .INIT ( 2'h1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B ( + .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ), + .O(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]), + .CE(CONTROL[8]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ) + + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]), + .I1(CONTROL[8]), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]), + .CE(CONTROL[8]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(CONTROL[1]), + .I1(CONTROL[8]), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_DLY ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/iCAPTURE ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ), + .R(\U0/I_NO_D.U_ILA/iRESET [4]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ), + .R(\U0/I_NO_D.U_ILA/iRESET [4]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/F_NO_TCMC.U_FDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ), + .R(\U0/I_NO_D.U_ILA/iRESET [5]), + .Q(\U0/I_NO_D.U_ILA/iTRIGGER ) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG3[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [27]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG3[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [26]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG3[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [25]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG3[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [24]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG2[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [23]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG2[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [22]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG2[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [21]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG2[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [20]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG2[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [19]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG2[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [18]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG2[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [17]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG2[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [16]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG1[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [15]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG1[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [14]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG1[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [13]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG1[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [12]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG1[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [11]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG1[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [10]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG1[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [9]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG1[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [8]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG0[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [7]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG0[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [6]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG0[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [5]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG0[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [4]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG0[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [3]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG0[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [2]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG0[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG0[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<0> ( + .I0(CONTROL[10]), + .I1(CONTROL[11]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<0> ( + .CI(N1), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1> ( + .I0(CONTROL[12]), + .I1(CONTROL[13]), + .I2(CONTROL[9]), + .I3(CONTROL[14]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<2> ( + .I0(CONTROL[15]), + .I1(CONTROL[16]), + .I2(CONTROL[8]), + .I3(CONTROL[17]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3> ( + .I0(CONTROL[18]), + .I1(CONTROL[21]), + .I2(CONTROL[7]), + .I3(CONTROL[19]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<4> ( + .I0(CONTROL[20]), + .I1(CONTROL[22]), + .I2(CONTROL[6]), + .I3(CONTROL[23]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<5> ( + .I0(CONTROL[24]), + .I1(CONTROL[25]), + .I2(CONTROL[5]), + .I3(CONTROL[26]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<6> ( + .I0(CONTROL[27]), + .I1(CONTROL[28]), + .I2(CONTROL[2]), + .I3(CONTROL[29]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<7> ( + .I0(CONTROL[30]), + .I1(CONTROL[31]), + .I2(CONTROL[1]), + .I3(CONTROL[32]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<8> ( + .I0(CONTROL[33]), + .I1(CONTROL[34]), + .I2(CONTROL[4]), + .I3(CONTROL[35]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]) + ); + LUT4 #( + .INIT ( 16'hFEFF )) + \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ) + ); + LUT4 #( + .INIT ( 16'hFFFE )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ) + ); + LUT4 #( + .INIT ( 16'hF222 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ), + .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ) + ); + LUT4 #( + .INIT ( 16'hAF8D )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O129 ( + .I0(CONTROL[4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91 ( + .I0(N38), + .I1(N39), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ) + ); + LUT3 #( + .INIT ( 8'h15 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .O(N38) + ); + LUT4 #( + .INIT ( 16'h0145 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_G ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ), + .O(N39) + ); + LUT4_L #( + .INIT ( 16'h3F50 )) + \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ) + ); + LUT4_L #( + .INIT ( 16'h3120 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ) + ); + RAMB16_S1_S36 #( + .INIT_B ( 36'h000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_A ( 1'h0 ), + .SIM_COLLISION_CHECK ( "ALL" ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .SRVAL_A ( 1'h0 ), + .WRITE_MODE_A ( "WRITE_FIRST" ), + .WRITE_MODE_B ( "WRITE_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i ( + .CLKA(CONTROL[0]), + .CLKB(CLK), + .ENA(CONTROL[6]), + .ENB(N1), + .WEB(\U0/I_NO_D.U_ILA/iCAP_WR_EN ), + .SSRA(N0), + .SSRB(N0), + .WEA(N0), + .DIPB({N0, N0, N0, N0}), + .ADDRA({\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]}), + .ADDRB({\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5] +, \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1], +\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]}), + .DIB({N0, N0, N0, \U0/I_NO_D.U_ILA/iDATA [27], \U0/I_NO_D.U_ILA/iDATA [26], \U0/I_NO_D.U_ILA/iDATA [25], \U0/I_NO_D.U_ILA/iDATA [24], +\U0/I_NO_D.U_ILA/iDATA [23], \U0/I_NO_D.U_ILA/iDATA [22], \U0/I_NO_D.U_ILA/iDATA [21], \U0/I_NO_D.U_ILA/iDATA [20], \U0/I_NO_D.U_ILA/iDATA [19], +\U0/I_NO_D.U_ILA/iDATA [18], \U0/I_NO_D.U_ILA/iDATA [17], \U0/I_NO_D.U_ILA/iDATA [16], \U0/I_NO_D.U_ILA/iDATA [15], \U0/I_NO_D.U_ILA/iDATA [14], +\U0/I_NO_D.U_ILA/iDATA [13], \U0/I_NO_D.U_ILA/iDATA [12], \U0/I_NO_D.U_ILA/iDATA [11], \U0/I_NO_D.U_ILA/iDATA [10], \U0/I_NO_D.U_ILA/iDATA [9], +\U0/I_NO_D.U_ILA/iDATA [8], \U0/I_NO_D.U_ILA/iDATA [7], \U0/I_NO_D.U_ILA/iDATA [6], \U0/I_NO_D.U_ILA/iDATA [5], \U0/I_NO_D.U_ILA/iDATA [4], +\U0/I_NO_D.U_ILA/iDATA [3], \U0/I_NO_D.U_ILA/iDATA [2], \U0/I_NO_D.U_ILA/iDATA [1], \U0/I_NO_D.U_ILA/iDATA [0], \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT }), + .DOA({\U0/I_NO_D.U_ILA/iDATA_DOUT }), + .DIA({N0}), + .DOB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED }), + .DOPB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED }) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp2/extramfifo/ila.xco b/fpga/usrp2/extramfifo/ila.xco new file mode 100644 index 000000000..c8d4d2f75 --- /dev/null +++ b/fpga/usrp2/extramfifo/ila.xco @@ -0,0 +1,130 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Wed Jul 21 18:51:14 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a +# END Select +# BEGIN Parameters +CSET component_name=ila +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic +CSET match_type_10=basic +CSET match_type_11=basic +CSET match_type_12=basic +CSET match_type_13=basic +CSET match_type_14=basic +CSET match_type_15=basic +CSET match_type_16=basic +CSET match_type_2=basic +CSET match_type_3=basic +CSET match_type_4=basic +CSET match_type_5=basic +CSET match_type_6=basic +CSET match_type_7=basic +CSET match_type_8=basic +CSET match_type_9=basic +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=4 +CSET sample_data_depth=512 +CSET sample_on=Rising +CSET trigger_port_width_1=8 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=4 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=true +# END Parameters +GENERATE +# CRC: 66151c7c diff --git a/fpga/usrp2/extramfifo/nobl_fifo.v b/fpga/usrp2/extramfifo/nobl_fifo.v new file mode 100644 index 000000000..4c009d980 --- /dev/null +++ b/fpga/usrp2/extramfifo/nobl_fifo.v @@ -0,0 +1,96 @@ +// Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port +// device it can only sustain data throughput at half the RAM clock rate. +// Fair arbitration to ensure this occurs is included in this logic and +// requests for transactions that can not be completed are held off. +// This FIFO requires a an external signal driving read_strobe that assures space for at least 6 +// reads since this the theopretical maximum number in flight due to pipeling. + +module nobl_fifo + #(parameter WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) + ( + input clk, + input rst, + input [WIDTH-1:0] RAM_D_pi, + output [WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [RAM_DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + input [WIDTH-1:0] write_data, + input write_strobe, + output reg space_avail, + output [WIDTH-1:0] read_data, + input read_strobe, // Triggers a read, result in approximately 6 cycles. + output data_avail, // Qulaifys read data available this cycle on read_data. + output reg [FIFO_DEPTH-1:0] capacity + ); + + //reg [FIFO_DEPTH-1:0] capacity; + reg [FIFO_DEPTH-1:0] wr_pointer; + reg [FIFO_DEPTH-1:0] rd_pointer; + wire [RAM_DEPTH-1:0] address; + reg data_avail_int; // Internal not empty flag. + + assign read = read_strobe && data_avail_int; + assign write = write_strobe && space_avail; + + // When a read and write collision occur, supress the space_avail flag next cycle + // and complete write followed by read over 2 cycles. This forces balanced arbitration + // and makes for a simple logic design. + + always @(posedge clk) + if (rst) + begin + capacity <= (1 << FIFO_DEPTH) - 1; + wr_pointer <= 0; + rd_pointer <= 0; + space_avail <= 1; + data_avail_int <= 0; + end + else + begin + // No space available if: + // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) + space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); + // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. + data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read)) ); + wr_pointer <= wr_pointer + write; + rd_pointer <= rd_pointer + (~write && read); + capacity <= capacity - write + (~write && read) ; + end // else: !if(rst) + + assign address = write ? wr_pointer : rd_pointer; + assign enable = write || read; + + + // + // Simple NoBL SRAM interface, 4 cycle read latency. + // Read/Write arbitration via temprary application of empty/full flags. + // + nobl_if nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(write_data), + .data_in(read_data), + .data_in_valid(data_avail), + .write(write), + .enable(enable) + ); + + + +endmodule // nobl_fifo diff --git a/fpga/usrp2/extramfifo/nobl_if.v b/fpga/usrp2/extramfifo/nobl_if.v new file mode 100644 index 000000000..391a841e8 --- /dev/null +++ b/fpga/usrp2/extramfifo/nobl_if.v @@ -0,0 +1,139 @@ +// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world. + +module nobl_if + #(parameter WIDTH=18,DEPTH=19) + ( + input clk, + input rst, + input [WIDTH-1:0] RAM_D_pi, + output [WIDTH-1:0] RAM_D_po, + output reg RAM_D_poe, + output [DEPTH-1:0] RAM_A, + output reg RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output reg RAM_CE1n, + input [DEPTH-1:0] address, + input [WIDTH-1:0] data_out, + output reg [WIDTH-1:0] data_in, + output reg data_in_valid, + input write, + input enable + ); + + + reg enable_pipe1; + reg [DEPTH-1:0] address_pipe1; + reg write_pipe1; + reg [WIDTH-1:0] data_out_pipe1; + + reg enable_pipe2; + reg write_pipe2; + reg [WIDTH-1:0] data_out_pipe2; + + reg enable_pipe3; + reg write_pipe3; + reg [WIDTH-1:0] data_out_pipe3; + + assign RAM_LDn = 0; + // ZBT/NoBL RAM actually manages its own output enables very well. + assign RAM_OEn = 0; + + // + // Pipeline stage 1 + // + always @(posedge clk) + if (rst) + begin + enable_pipe1 <= 0; + address_pipe1 <= 0; + write_pipe1 <= 0; + data_out_pipe1 <= 0; + end + else + begin + enable_pipe1 <= enable; + RAM_CE1n <= ~enable; // Creates IOB flob + + + if (enable) + begin + address_pipe1 <= address; + write_pipe1 <= write; + RAM_WEn <= ~write; // Creates IOB flob + + + if (write) + data_out_pipe1 <= data_out; + end + end // always @ (posedge clk) + + // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM + assign RAM_A = address_pipe1; + assign RAM_CENn = 1'b0; + // assign RAM_WEn = ~write_pipe1; +// assign RAM_CE1n = ~enable_pipe1; + + // + // Pipeline stage2 + // + always @(posedge clk) + if (rst) + begin + enable_pipe2 <= 0; + data_out_pipe2 <= 0; + write_pipe2 <= 0; + end + else + begin + data_out_pipe2 <= data_out_pipe1; + write_pipe2 <= write_pipe1; + enable_pipe2 <= enable_pipe1; + end + + // + // Pipeline stage3 + // + always @(posedge clk) + if (rst) + begin + enable_pipe3 <= 0; + data_out_pipe3 <= 0; + write_pipe3 <= 0; + RAM_D_poe <= 0; + end + else + begin + data_out_pipe3 <= data_out_pipe2; + write_pipe3 <= write_pipe2; + enable_pipe3 <= enable_pipe2; + RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx. + end + + // Pipeline 3 drives write data on NoBL SRAM + assign RAM_D_po = data_out_pipe3; + + + // + // Pipeline stage4 + // + always @(posedge clk) + if (rst) + begin + data_in_valid <= 0; + data_in <= 0; + end + else + begin + data_in <= RAM_D_pi; + if (enable_pipe3 & ~write_pipe3) + begin + // Read data now available to be registered. + data_in_valid <= 1'b1; + end + else + data_in_valid <= 1'b0; + end // always @ (posedge clk) + +endmodule // nobl_if diff --git a/fpga/usrp2/extramfifo/test_sram_if.v b/fpga/usrp2/extramfifo/test_sram_if.v new file mode 100644 index 000000000..0e74b49eb --- /dev/null +++ b/fpga/usrp2/extramfifo/test_sram_if.v @@ -0,0 +1,175 @@ +// Instantiate this block at the core level to conduct closed +// loop testing of the AC performance of the USRP2 SRAM interface + + +`define WIDTH 18 +`define DEPTH 19 + +module test_sram_if + ( + input clk, + input rst, + input [`WIDTH-1:0] RAM_D_pi, + output [`WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [`DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + output reg correct + ); + + reg [`DEPTH-1:0] write_count; + reg [`DEPTH-1:0] read_count; + reg enable; + reg write; + reg write_cycle; + reg read_cycle; + reg enable_reads; + reg [18:0] address; + reg [17:0] data_out; + wire [17:0] data_in; + wire data_in_valid; + + reg [17:0] check_data; + reg [17:0] check_data_old; + reg [17:0] check_data_old2; + + // + // Create counter that generates both external modulo 2^19 address and modulo 2^18 data to test RAM. + // + + always @(posedge clk) + if (rst) + begin + write_count <= 19'h0; + read_count <= 19'h0; + end + else if (write_cycle) // Write cycle + if (write_count == 19'h7FFFF) + begin + write_count <= 19'h0; + end + else + begin + write_count <= write_count + 1'b1; + end + else if (read_cycle) // Read cycle + if (read_count == 19'h7FFFF) + begin + read_count <= 19'h0; + end + else + begin + read_count <= read_count + 1'b1; + end + + always @(posedge clk) + if (rst) + begin + enable_reads <= 0; + read_cycle <= 0; + write_cycle <= 0; + end + else + begin + write_cycle <= ~write_cycle; + if (enable_reads) + read_cycle <= write_cycle; + if (write_count == 15) // Enable reads 15 writes after reset terminates. + enable_reads <= 1; + end // else: !if(rst) + + always @(posedge clk) + if (rst) + begin + enable <= 0; + end + else if (write_cycle) + begin + address <= write_count; + data_out <= write_count[17:0]; + enable <= 1; + write <= 1; + end + else if (read_cycle) + begin + address <= read_count; + check_data <= read_count[17:0]; + check_data_old <= check_data; + check_data_old2 <= check_data_old; + enable <= 1; + write <= 0; + end + else + enable <= 0; + + always @(posedge clk) + if (data_in_valid) + begin + correct <= (data_in == check_data_old2); + end + + + nobl_if nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(data_out), + .data_in(data_in), + .data_in_valid(data_in_valid), + .write(write), + .enable(enable) + ); + + + wire [35:0] CONTROL0; + reg [7:0] data_in_reg, data_out_reg, address_reg; + reg data_in_valid_reg,write_reg,enable_reg,correct_reg; + + always @(posedge clk) + begin + data_in_reg <= data_in[7:0]; + data_out_reg <= data_out[7:0]; + data_in_valid_reg <= data_in_valid; + write_reg <= write; + enable_reg <= enable; + correct_reg <= correct; + address_reg <= address; + + end + + + icon icon_i1 + ( + .CONTROL0(CONTROL0) + ); + + ila ila_i1 + ( + .CLK(clk), + .CONTROL(CONTROL0), + // .TRIG0(address_reg), + .TRIG0(data_in_reg[7:0]), + .TRIG1(data_out_reg[7:0]), + .TRIG2(address_reg[7:0]), + .TRIG3({data_in_valid_reg,write_reg,enable_reg,correct_reg}) + ); + + + +endmodule // test_sram_if + +
\ No newline at end of file diff --git a/fpga/usrp2/fifo/fifo18_to_fifo36.v b/fpga/usrp2/fifo/fifo18_to_fifo36.v new file mode 100644 index 000000000..25bb215a1 --- /dev/null +++ b/fpga/usrp2/fifo/fifo18_to_fifo36.v @@ -0,0 +1,20 @@ + +// For now just assume FIFO18 is same as FIFO19 without occupancy bit + +module fifo18_to_fifo36 + (input clk, input reset, input clear, + input [17:0] f18_datain, + input f18_src_rdy_i, + output f18_dst_rdy_o, + + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i + ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk), .reset(reset), .clear(clear), + .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o), + .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) ); + +endmodule // fifo18_to_fifo36 diff --git a/fpga/usrp2/fifo/fifo36_mux.v b/fpga/usrp2/fifo/fifo36_mux.v index 92bf13ff9..c6fd40f27 100644 --- a/fpga/usrp2/fifo/fifo36_mux.v +++ b/fpga/usrp2/fifo/fifo36_mux.v @@ -20,6 +20,9 @@ module fifo36_mux wire eof0 = data0_i[33]; wire eof1 = data1_i[33]; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + always @(posedge clk) if(reset | clear) state <= MUX_IDLE0; @@ -32,7 +35,7 @@ module fifo36_mux state <= MUX_DATA1; MUX_DATA0 : - if(src0_rdy_i & dst_rdy_i & eof0) + if(src0_rdy_i & dst_rdy_int & eof0) state <= prio ? MUX_IDLE0 : MUX_IDLE1; MUX_IDLE1 : @@ -42,16 +45,20 @@ module fifo36_mux state <= MUX_DATA0; MUX_DATA1 : - if(src1_rdy_i & dst_rdy_i & eof1) + if(src1_rdy_i & dst_rdy_int & eof1) state <= MUX_IDLE0; default : state <= MUX_IDLE0; endcase // case (state) - assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; - assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; - assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; + assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; + assign data_int = (state==MUX_DATA0) ? data0_i : data1_i; + fifo_short #(.WIDTH(36)) mux_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); endmodule // fifo36_demux diff --git a/fpga/usrp2/fifo/fifo_2clock_cascade.v b/fpga/usrp2/fifo/fifo_2clock_cascade.v index 5ce726977..4e8c244c2 100644 --- a/fpga/usrp2/fifo/fifo_2clock_cascade.v +++ b/fpga/usrp2/fifo/fifo_2clock_cascade.v @@ -1,8 +1,10 @@ module fifo_2clock_cascade #(parameter WIDTH=32, SIZE=9) - (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, - input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, + output [15:0] space, output [15:0] short_space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, + output [15:0] occupied, output [15:0] short_occupied, input arst); wire [WIDTH-1:0] data_int1, data_int2; @@ -29,7 +31,11 @@ module fifo_2clock_cascade .space(s2_space), .occupied(s2_occupied)); // Be conservative -- Only advertise space from input side of fifo, occupied from output side - assign space = {11'b0,s1_space} + l_space; - assign occupied = {11'b0,s2_occupied} + l_occupied; + assign space = {11'b0,s1_space} + l_space; + assign occupied = {11'b0,s2_occupied} + l_occupied; + + // For the fifo_extram, we only want to know the immediately adjacent space + assign short_space = {11'b0,s1_space}; + assign short_occupied = {11'b0,s2_occupied}; endmodule // fifo_2clock_cascade diff --git a/fpga/usrp2/models/idt71v65603s150.v b/fpga/usrp2/models/idt71v65603s150.v new file mode 100755 index 000000000..457dfa6dd --- /dev/null +++ b/fpga/usrp2/models/idt71v65603s150.v @@ -0,0 +1,301 @@ +/******************************************************************************* + * + * File Name : idt71v65603s150.v + * Product : IDT71V65603 + * Function : 256K x 36 pipeline ZBT Static RAM + * Simulation Tool/Version : Verilog-XL 2.5 + * Date : 07/19/00 + * + * Copyright 1999 Integrated Device Technology, Inc. + * + * Revision Notes: 07/19/00 Rev00 + * + ******************************************************************************/ +/******************************************************************************* + * Module Name: idt71v65603s150 + * + * Notes : This model is believed to be functionally + * accurate. Please direct any inquiries to + * IDT SRAM Applications at: sramhelp@idt.com + * + *******************************************************************************/ + + /*************************************************************** + * + * Integrated Device Technology, Inc. ("IDT") hereby grants the + * user of this Verilog/VCS model a non-exclusive, nontransferable + * license to use this Verilog/VCS model under the following terms. + * The user is granted this license only to use the Verilog/VCS + * model and is not granted rights to sell, copy (except as needed + * to run the IBIS model), rent, lease or sub-license the Verilog/VCS + * model in whole or in part, or in modified form to anyone. The User + * may modify the Verilog/VCS model to suit its specific applications, + * but rights to derivative works and such modifications shall belong + * to IDT. + * + * This Verilog/VCS model is provided on an "AS IS" basis and + * IDT makes absolutely no warranty with respect to the information + * contained herein. IDT DISCLAIMS AND CUSTOMER WAIVES ALL + * WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE + * ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE + * USER ACCORDINGLY, IN NO EVENT SHALL IDT BE LIABLE + * FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN CONTRACT OR + * TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, + * CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF + * THE USE OR APPLICATION OF THE VERILOG/VCS model. Further, + * IDT reserves the right to make changes without notice to any + * product herein to improve reliability, function, or design. + * IDT does not convey any license under patent rights or + * any other intellectual property rights, including those of + * third parties. IDT is not obligated to provide maintenance + * or support for the licensed Verilog/VCS model. + * + ***************************************************************/ + + `timescale 1ns/100ps + +module idt71v65603s150 (A, + adv_ld_, // advance (high) / load (low) + bw1_, bw2_, bw3_, bw4_, // byte write enables (low) + ce1_, ce2, ce2_, // chip enables + cen_, // clock enable (low) + clk, // clock + IO, IOP, // data bus + lbo_, // linear burst order (low) + oe_, // output enable (low) + r_w_); // read (high) / write (low) + +initial +begin + $write("\n********************************************************\n"); + $write(" idt71v65603s150, 256K x 36 Pipelined burst ZBT SRAM \n"); + $write(" Rev: 00 July 2000 \n"); + $write(" copyright 1997,1998,1999,2000 by IDT, Inc. \n"); + $write("********************************************************\n\n"); +end + +input [17:0] A; +inout [31:0] IO; +inout [4:1] IOP; +input adv_ld_, bw1_, bw2_, bw3_, bw4_, ce1_, ce2, ce2_, + cen_, clk, lbo_, oe_, r_w_; + + +//internal registers for data, address, etc +reg [8:0] mem1[0:262143]; //memory array +reg [8:0] mem2[0:262143]; //memory array +reg [8:0] mem3[0:262143]; //memory array +reg [8:0] mem4[0:262143]; //memory array + +reg [35:0] dout; +reg [17:0] addr_a, + addr_b; +reg wren_a, wren_b; +reg cs_a, cs_b; +reg bw_a1, bw_b1; +reg bw_a2, bw_b2; +reg bw_a3, bw_b3; +reg bw_a4, bw_b4; +reg [1:0] brst_cnt; + +wire[35:0] data_out; +wire doe; +wire cs = (~ce1_ & ce2 & ~ce2_); +wire baddr0, baddr1; + + +parameter regdelay = 0.2; +parameter outdly = 0.2; + +specify +specparam +//Clock Parameters + tCYC = 6.7, //clock cycle time + tCH = 2.0, //clock high time + tCL = 2.0, //clock low time + +//Output Parameters + tCD = 3.8, //clk to data valid + tCLZ = 1.5, //clk to output Low-Z + tCHZ = 3.0, //clk to data Hi-Z + tOE = 3.8, //OE to output valid + tOLZ = 0.0, //OE to output Hi-Z + tOHZ = 3.8, //OE to output Hi-Z + +//Set up times + tSE = 1.5, //clock enable set-up + tSA = 1.5, //address set-up + tSD = 1.5, //data set-up + tSW = 1.5, //Read/Write set-up + tSADV = 1.5, //Advance/Load set-up + tSC = 1.5, //Chip enable set-up + tSB = 1.5, //Byte write enable set-up + +//Hold times + tHE = 0.5, //clock enable hold + tHA = 0.5, //address hold + tHD = 0.5, //data hold + tHW = 0.5, //Read/Write hold + tHADV = 0.5, //Advance/Load hold + tHC = 0.5, //Chip enable hold + tHB = 0.5; //Byte write enable hold + + + (oe_ *> IO) = (tOE,tOE,tOHZ,tOLZ,tOHZ,tOLZ); //(01,10,0z,z1,1z,z0) + (clk *> IO) = (tCD,tCD,tCHZ,tCLZ,tCHZ,tCLZ); //(01,10,0z,z1,1z,z0) + + (oe_ *> IOP) = (tOE,tOE,tOHZ,tOLZ,tOHZ,tOLZ); //(01,10,0z,z1,1z,z0) + (clk *> IOP) = (tCD,tCD,tCHZ,tCLZ,tCHZ,tCLZ); //(01,10,0z,z1,1z,z0) + +//timing checks + + $period(posedge clk, tCYC ); + $width (posedge clk, tCH ); + $width (negedge clk, tCL ); + + + $setuphold(posedge clk, A, tSA, tHA); + $setuphold(posedge clk, IO, tSD, tHD); + $setuphold(posedge clk, IOP, tSD, tHD); + $setuphold(posedge clk, adv_ld_, tSADV, tHADV); + $setuphold(posedge clk, bw1_, tSB, tHB); + $setuphold(posedge clk, bw2_, tSB, tHB); + $setuphold(posedge clk, bw3_, tSB, tHB); + $setuphold(posedge clk, bw4_, tSB, tHB); + $setuphold(posedge clk, ce1_, tSC, tHC); + $setuphold(posedge clk, ce2, tSC, tHC); + $setuphold(posedge clk, ce2_, tSC, tHC); + $setuphold(posedge clk, cen_, tSE, tHE); + $setuphold(posedge clk, r_w_, tSW, tHW); + +endspecify + +initial begin + cs_a = 0; + cs_b = 0; +end + + +///////////////////////////////////////////////////////////////////////// +//input registers +//-------------------- +always @(posedge clk) +begin + if ( ~cen_ & ~adv_ld_ ) cs_a <= #regdelay cs; + if ( ~cen_ ) cs_b <= #regdelay cs_a; + + if ( ~cen_ & ~adv_ld_ ) wren_a <= #regdelay (cs & ~r_w_); + if ( ~cen_ ) wren_b <= #regdelay wren_a; + + if ( ~cen_ ) bw_a1 <= #regdelay ~bw1_; + if ( ~cen_ ) bw_a2 <= #regdelay ~bw2_; + if ( ~cen_ ) bw_a3 <= #regdelay ~bw3_; + if ( ~cen_ ) bw_a4 <= #regdelay ~bw4_; + + if ( ~cen_ ) bw_b1 <= #regdelay bw_a1; + if ( ~cen_ ) bw_b2 <= #regdelay bw_a2; + if ( ~cen_ ) bw_b3 <= #regdelay bw_a3; + if ( ~cen_ ) bw_b4 <= #regdelay bw_a4; + + if ( ~cen_ & ~adv_ld_ ) addr_a[17:0] <= #regdelay A[17:0]; + if ( ~cen_ ) addr_b[17:0] <= #regdelay {addr_a[17:2], baddr1, baddr0}; +end + + +///////////////////////////////////////////////////////////////////////// +//burst counter +//-------------------- +always @(posedge clk) +begin + if ( lbo_ & ~cen_ & ~adv_ld_) brst_cnt <= #regdelay 0; + else if (~lbo_ & ~cen_ & ~adv_ld_) brst_cnt <= #regdelay A[1:0]; + else if ( ~cen_ & adv_ld_) brst_cnt <= #regdelay brst_cnt + 1; +end + + +///////////////////////////////////////////////////////////////////////// +//address logic +//-------------------- +assign baddr1 = lbo_ ? (brst_cnt[1] ^ addr_a[1]) : brst_cnt[1]; +assign baddr0 = lbo_ ? (brst_cnt[0] ^ addr_a[0]) : brst_cnt[0]; + + +///////////////////////////////////////////////////////////////////////// +//data output register +//-------------------- +always @(posedge clk) +begin + #regdelay; + #regdelay; + dout[8:0] = mem1[addr_b]; + dout[17:9] = mem2[addr_b]; + dout[26:18] = mem3[addr_b]; + dout[35:27] = mem4[addr_b]; +end + +assign data_out = dout; + + +///////////////////////////////////////////////////////////////////////// +//Output buffers: using a bufif1 has the same effect as... +// +// assign D = doe ? data_out : 36'hz; +// +//It was coded this way to support SPECIFY delays in the specparam section. +//-------------------- +bufif1 #outdly (IO[0],data_out[0],doe); +bufif1 #outdly (IO[1],data_out[1],doe); +bufif1 #outdly (IO[2],data_out[2],doe); +bufif1 #outdly (IO[3],data_out[3],doe); +bufif1 #outdly (IO[4],data_out[4],doe); +bufif1 #outdly (IO[5],data_out[5],doe); +bufif1 #outdly (IO[6],data_out[6],doe); +bufif1 #outdly (IO[7],data_out[7],doe); +bufif1 #outdly (IOP[1],data_out[8],doe); + +bufif1 #outdly (IO[8],data_out[9],doe); +bufif1 #outdly (IO[9],data_out[10],doe); +bufif1 #outdly (IO[10],data_out[11],doe); +bufif1 #outdly (IO[11],data_out[12],doe); +bufif1 #outdly (IO[12],data_out[13],doe); +bufif1 #outdly (IO[13],data_out[14],doe); +bufif1 #outdly (IO[14],data_out[15],doe); +bufif1 #outdly (IO[15],data_out[16],doe); +bufif1 #outdly (IOP[2],data_out[17],doe); + +bufif1 #outdly (IO[16],data_out[18],doe); +bufif1 #outdly (IO[17],data_out[19],doe); +bufif1 #outdly (IO[18],data_out[20],doe); +bufif1 #outdly (IO[19],data_out[21],doe); +bufif1 #outdly (IO[20],data_out[22],doe); +bufif1 #outdly (IO[21],data_out[23],doe); +bufif1 #outdly (IO[22],data_out[24],doe); +bufif1 #outdly (IO[23],data_out[25],doe); +bufif1 #outdly (IOP[3],data_out[26],doe); + +bufif1 #outdly (IO[24],data_out[27],doe); +bufif1 #outdly (IO[25],data_out[28],doe); +bufif1 #outdly (IO[26],data_out[29],doe); +bufif1 #outdly (IO[27],data_out[30],doe); +bufif1 #outdly (IO[28],data_out[31],doe); +bufif1 #outdly (IO[29],data_out[32],doe); +bufif1 #outdly (IO[30],data_out[33],doe); +bufif1 #outdly (IO[31],data_out[34],doe); +bufif1 #outdly (IOP[4],data_out[35],doe); + +assign doe = cs_b & ~wren_b & ~oe_ ; + + +///////////////////////////////////////////////////////////////////////// +// write to ram +//------------- +always @(posedge clk) +begin + if (wren_b & bw_b1 & ~cen_) mem1[addr_b] = {IOP[1], IO[7:0]}; + if (wren_b & bw_b2 & ~cen_) mem2[addr_b] = {IOP[2], IO[15:8]}; + if (wren_b & bw_b3 & ~cen_) mem3[addr_b] = {IOP[3], IO[23:16]}; + if (wren_b & bw_b4 & ~cen_) mem4[addr_b] = {IOP[4], IO[31:24]}; +end + +endmodule diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common index 4da64ac28..9a180d10e 100644 --- a/fpga/usrp2/top/Makefile.common +++ b/fpga/usrp2/top/Makefile.common @@ -31,6 +31,7 @@ synth: $(ISE_FILE) $(ISE_HELPER) "Synthesize - XST" bin: $(BIN_FILE) + $(ISE_HELPER) "Generate Programming File" mcs: $(MCS_FILE) diff --git a/fpga/usrp2/top/u2_rev3/Makefile.udp b/fpga/usrp2/top/u2_rev3/Makefile.udp index 9962887d4..99effb038 100644 --- a/fpga/usrp2/top/u2_rev3/Makefile.udp +++ b/fpga/usrp2/top/u2_rev3/Makefile.udp @@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + ################################################## # Project Properties diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v index 9ba3cc136..a5963f6b1 100755 --- a/fpga/usrp2/top/u2_rev3/u2_core.v +++ b/fpga/usrp2/top/u2_rev3/u2_core.v @@ -123,7 +123,7 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - output RAM_CLK, + // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, diff --git a/fpga/usrp2/top/u2_rev3/u2_core_udp.v b/fpga/usrp2/top/u2_rev3/u2_core_udp.v index c9502898b..b47e7e311 100644 --- a/fpga/usrp2/top/u2_rev3/u2_core_udp.v +++ b/fpga/usrp2/top/u2_rev3/u2_core_udp.v @@ -119,11 +119,13 @@ module u2_core inout [15:0] io_rx, // External RAM - inout [17:0] RAM_D, + input [17:0] RAM_D_pi, + output [17:0] RAM_D_po, + output RAM_D_poe, output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - output RAM_CLK, + // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -169,7 +171,7 @@ module u2_core wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -412,7 +414,7 @@ module u2_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .gpio({io_tx,io_rx}) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -425,7 +427,7 @@ module u2_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd2; + localparam compat_num = 32'd3; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -539,10 +541,17 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Interrupt Controller, Slave #8 + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + assign irq= {{8'b0}, {8'b0}, {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), @@ -653,14 +662,47 @@ module u2_core wire [35:0] tx_data; wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; + + // FIFO cascade draws from buffer pool, feeds vita tx deframer +/* -----\/----- EXCLUDED -----\/----- fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); + -----/\----- EXCLUDED -----/\----- */ + + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) + ext_fifo_i1 + ( + .int_clk(dsp_clk), + .ext_clk(clk_to_mac), +// .ext_clk(wb_clk), + .rst(dsp_rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), +// .datain({rd1_flags,rd1_dat}), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .src_rdy_i(rd1_ready_o), // WRITE + .dst_rdy_o(rd1_ready_i), // not FULL +// .dataout(tx_data), + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .src_rdy_o(tx_src_rdy), // not EMPTY + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) + ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), @@ -719,7 +761,30 @@ module u2_core assign RAM_CE1n = 0; assign RAM_D[17:16] = 2'bzz; - */ +/* -----\/----- EXCLUDED -----\/----- + *-/ + + test_sram_if test_sram_if_i1 + ( + // .clk(wb_clk), + .clk(clk_to_mac), + .rst(wb_rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .correct() + ); + -----/\----- EXCLUDED -----/\----- */ + + //assign RAM_CLK = wb_clk; + //assign RAM_CLK = clk_to_mac; + // ///////////////////////////////////////////////////////////////////////// // VITA Timing @@ -731,8 +796,8 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = 2'b00; - assign debug = 32'd0; + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf index 6aa699d2a..6e0caedd5 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf @@ -74,49 +74,49 @@ NET "MDC" LOC = "V18" ; NET "PHY_INTn" LOC = "AB13" ; NET "PHY_RESETn" LOC = "AA19" ; NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" ; -NET "RAM_D[1]" LOC = "N21" ; -NET "RAM_D[2]" LOC = "N22" ; -NET "RAM_D[3]" LOC = "M17" ; -NET "RAM_D[4]" LOC = "M18" ; -NET "RAM_D[5]" LOC = "M19" ; -NET "RAM_D[6]" LOC = "M20" ; -NET "RAM_D[7]" LOC = "M21" ; -NET "RAM_D[8]" LOC = "M22" ; -NET "RAM_D[9]" LOC = "Y22" ; -NET "RAM_D[10]" LOC = "Y21" ; -NET "RAM_D[11]" LOC = "Y20" ; -NET "RAM_D[12]" LOC = "Y19" ; -NET "RAM_D[13]" LOC = "W22" ; -NET "RAM_D[14]" LOC = "W21" ; -NET "RAM_D[15]" LOC = "W20" ; -NET "RAM_D[16]" LOC = "W19" ; -NET "RAM_D[17]" LOC = "V22" ; -NET "RAM_A[0]" LOC = "U21" ; -NET "RAM_A[1]" LOC = "T19" ; -NET "RAM_A[2]" LOC = "V21" ; -NET "RAM_A[3]" LOC = "V20" ; -NET "RAM_A[4]" LOC = "T20" ; -NET "RAM_A[5]" LOC = "T21" ; -NET "RAM_A[6]" LOC = "T22" ; -NET "RAM_A[7]" LOC = "T18" ; -NET "RAM_A[8]" LOC = "R18" ; -NET "RAM_A[9]" LOC = "P19" ; -NET "RAM_A[10]" LOC = "P21" ; -NET "RAM_A[11]" LOC = "P22" ; -NET "RAM_A[12]" LOC = "N19" ; -NET "RAM_A[13]" LOC = "N17" ; -NET "RAM_A[14]" LOC = "N18" ; -NET "RAM_A[15]" LOC = "T17" ; -NET "RAM_A[16]" LOC = "U19" ; -NET "RAM_A[17]" LOC = "U18" ; -NET "RAM_A[18]" LOC = "V19" ; -NET "RAM_CE1n" LOC = "U20" ; -NET "RAM_CENn" LOC = "P18" ; -NET "RAM_CLK" LOC = "P17" ; -NET "RAM_WEn" LOC = "R22" ; -NET "RAM_OEn" LOC = "R21" ; -NET "RAM_LDn" LOC = "R19" ; +NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; NET "ser_enable" LOC = "W11" ; NET "ser_prbsen" LOC = "AA3" ; NET "ser_loopen" LOC = "Y4" ; @@ -264,22 +264,22 @@ NET "sdi_tx_adc" LOC = "J4" ; NET "sen_tx_dac" LOC = "H4" ; NET "sclk_tx_dac" LOC = "J5" ; NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" ; -NET "io_tx[1]" LOC = "K3" ; -NET "io_tx[2]" LOC = "G1" ; -NET "io_tx[3]" LOC = "G5" ; -NET "io_tx[4]" LOC = "H5" ; -NET "io_tx[5]" LOC = "F3" ; -NET "io_tx[6]" LOC = "F2" ; -NET "io_tx[7]" LOC = "F5" ; -NET "io_tx[8]" LOC = "G6" ; -NET "io_tx[9]" LOC = "E2" ; -NET "io_tx[10]" LOC = "E1" ; -NET "io_tx[11]" LOC = "E3" ; -NET "io_tx[12]" LOC = "F4" ; -NET "io_tx[13]" LOC = "D2" ; -NET "io_tx[14]" LOC = "D4" ; -NET "io_tx[15]" LOC = "E4" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; NET "sen_rx_db" LOC = "D22" ; NET "sclk_rx_db" LOC = "F19" ; NET "sdo_rx_db" LOC = "G20" ; @@ -291,22 +291,22 @@ NET "sdi_rx_adc" LOC = "H22" ; NET "sen_rx_dac" LOC = "J18" ; NET "sclk_rx_dac" LOC = "J19" ; NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" ; -NET "io_rx[1]" LOC = "L20" ; -NET "io_rx[2]" LOC = "L19" ; -NET "io_rx[3]" LOC = "L18" ; -NET "io_rx[4]" LOC = "L17" ; -NET "io_rx[5]" LOC = "K22" ; -NET "io_rx[6]" LOC = "K21" ; -NET "io_rx[7]" LOC = "K20" ; -NET "io_rx[8]" LOC = "G22" ; -NET "io_rx[9]" LOC = "G21" ; -NET "io_rx[10]" LOC = "F21" ; -NET "io_rx[11]" LOC = "F20" ; -NET "io_rx[12]" LOC = "G19" ; -NET "io_rx[13]" LOC = "G18" ; -NET "io_rx[14]" LOC = "G17" ; -NET "io_rx[15]" LOC = "E22" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; NET "clk_to_mac" TNM_NET = "clk_to_mac"; TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; @@ -324,6 +324,7 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v index 4daa66212..4f7f9bf1a 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.v +++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v @@ -330,8 +330,8 @@ module u2_rev3 wire [15:0] dac_a_int, dac_b_int; // DAC A and B are swapped in schematic to facilitate clean layout // DAC A is also inverted in schematic to facilitate clean layout - always @(negedge dsp_clk) dac_a <= ~dac_b_int; - always @(negedge dsp_clk) dac_b <= dac_a_int; + always @(posedge dsp_clk) dac_a <= ~dac_b_int; + always @(posedge dsp_clk) dac_b <= dac_a_int; /* OFDDRRSE OFDDRRSE_serdes_inst @@ -345,100 +345,228 @@ module u2_rev3 .S(0) // Synchronous preset input ); */ + + wire [17:0] RAM_D_pi; + wire [17:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + // + // DCM edits start here + // + + + wire RAM_CLK_buf; + wire clk_to_mac_buf; + wire clk125_ext_clk0; + wire clk125_ext_clk180; + wire clk125_ext_clk0_buf; + wire clk125_ext_clk180_buf; + wire clk125_int_buf; + wire clk125_int; + + IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), + .O(clk_to_mac_buf)); + + DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk125_ext_clk0), + .CLK180(clk125_ext_clk180) ); + defparam DCM_INST1.CLK_FEEDBACK = "1X"; + defparam DCM_INST1.CLKDV_DIVIDE = 2.0; + defparam DCM_INST1.CLKFX_DIVIDE = 1; + defparam DCM_INST1.CLKFX_MULTIPLY = 4; + defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST1.CLKIN_PERIOD = 8.000; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; + defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST1.FACTORY_JF = 16'h8080; + defparam DCM_INST1.PHASE_SHIFT = -64; + defparam DCM_INST1.STARTUP_WAIT = "FALSE"; + + IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), + .O(RAM_CLK_buf)); + BUFG clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), + .O(clk125_ext_clk0_buf)); + BUFG clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), + .O(clk125_ext_clk180_buf)); + + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk125_ext_clk0_buf), + .C1(clk125_ext_clk180_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + +// SRL16 dcm2_rst_i1 (.D(1'b0), +// .CLK(clk_to_mac_buf), +// .Q(dcm2_rst), +// .A0(1'b1), +// .A1(1'b1), +// .A2(1'b1), +// .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i1 is "000F"; + + DCM DCM_INST2 (.CLKFB(clk125_int_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk125_int)); + defparam DCM_INST2.CLK_FEEDBACK = "1X"; + defparam DCM_INST2.CLKDV_DIVIDE = 2.0; + defparam DCM_INST2.CLKFX_DIVIDE = 1; + defparam DCM_INST2.CLKFX_MULTIPLY = 4; + defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST2.CLKIN_PERIOD = 8.000; + defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST2.FACTORY_JF = 16'h8080; + defparam DCM_INST2.PHASE_SHIFT = 0; + defparam DCM_INST2.STARTUP_WAIT = "FALSE"; + + BUFG clk125_int_buf_i1 (.I(clk125_int), + .O(clk125_int_buf)); + + // + // DCM edits end here + // + + u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk_buf), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_misc (cpld_misc), - .cpld_init_b (cpld_init_b), - .por (~POR), - .config_success (config_success), - .adc_a (adc_a_reg2), - .adc_ovf_a (adc_ovf_a_reg2), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b_reg2), - .adc_ovf_b (adc_ovf_b_reg2), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a_int), - .dac_b (dac_b_int), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk125_int_buf), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk_buf), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_pi (RAM_D_pi), + .RAM_D_po (RAM_D_po), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + // .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); endmodule // u2_rev2 diff --git a/fpga/usrp2/vrt/Makefile.srcs b/fpga/usrp2/vrt/Makefile.srcs index dc4bd8c96..aa1356d82 100644 --- a/fpga/usrp2/vrt/Makefile.srcs +++ b/fpga/usrp2/vrt/Makefile.srcs @@ -12,4 +12,5 @@ vita_tx_control.v \ vita_tx_deframer.v \ vita_tx_chain.v \ gen_context_pkt.v \ +trigger_context_pkt.v \ )) diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v index 780a027ba..0eb035f3e 100644 --- a/fpga/usrp2/vrt/gen_context_pkt.v +++ b/fpga/usrp2/vrt/gen_context_pkt.v @@ -7,6 +7,8 @@ module gen_context_pkt input [31:0] streamid, input [63:0] vita_time, input [31:0] message, + input [31:0] seqnum0, + input [31:0] seqnum1, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); localparam CTXT_IDLE = 0; @@ -17,17 +19,32 @@ module gen_context_pkt localparam CTXT_TICS = 5; localparam CTXT_TICS2 = 6; localparam CTXT_MESSAGE = 7; - localparam CTXT_DONE = 8; + localparam CTXT_FLOWCTRL0 = 8; + localparam CTXT_FLOWCTRL1 = 9; + localparam CTXT_DONE = 10; reg [33:0] data_int; wire src_rdy_int, dst_rdy_int; - wire [3:0] seqno = 0; + reg [3:0] seqno; reg [3:0] ctxt_state; reg [63:0] err_time; + reg [31:0] stored_message; always @(posedge clk) if(reset | clear) - ctxt_state <= CTXT_IDLE; + stored_message <= 0; + else + if(trigger) + stored_message <= message; + else if(ctxt_state == CTXT_FLOWCTRL1) + stored_message <= 0; + + always @(posedge clk) + if(reset | clear) + begin + ctxt_state <= CTXT_IDLE; + seqno <= 0; + end else case(ctxt_state) CTXT_IDLE : @@ -41,9 +58,10 @@ module gen_context_pkt end CTXT_DONE : - if(~trigger) - ctxt_state <= CTXT_IDLE; - + begin + ctxt_state <= CTXT_IDLE; + seqno <= seqno + 4'd1; + end default : if(dst_rdy_int) ctxt_state <= ctxt_state + 1; @@ -53,13 +71,15 @@ module gen_context_pkt always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd24 }; - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd6 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd32 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd8 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; - CTXT_MESSAGE : data_int <= { 2'b10, message }; + CTXT_MESSAGE : data_int <= { 2'b00, message }; + CTXT_FLOWCTRL0 : data_int <= { 2'b00, seqnum0 }; + CTXT_FLOWCTRL1 : data_int <= { 2'b10, seqnum1 }; default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) diff --git a/fpga/usrp2/vrt/trigger_context_pkt.v b/fpga/usrp2/vrt/trigger_context_pkt.v new file mode 100644 index 000000000..226ec45f2 --- /dev/null +++ b/fpga/usrp2/vrt/trigger_context_pkt.v @@ -0,0 +1,52 @@ + + +module trigger_context_pkt + #(parameter BASE=0) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input packet_consumed, output reg trigger); + + wire [23:0] cycles; + wire [15:0] packets; + wire [6:0] dummy1; + wire [14:0] dummy2; + wire enable_timed, enable_consumed; + reg [30:0] cycle_count, packet_count; + + + setting_reg #(.my_addr(BASE+4), .at_reset(0)) sr_cycles + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_cycle,dummy1,cycles}),.changed()); + + setting_reg #(.my_addr(BASE+5), .at_reset(0)) sr_packets + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_consumed,dummy2,packets}),.changed()); + + always @(posedge clk) + if(reset | clear) + cycle_count <= 0; + else + if(trigger) + cycle_count <= 0; + else if(enable_cycle) + cycle_count <= cycle_count + 1; + + always @(posedge clk) + if(reset | clear) + packet_count <= 0; + else + if(trigger) + packet_count <= 0; + else if(packet_consumed & enable_consumed) + packet_count <= packet_count + 1; + + always @(posedge clk) + if(reset | clear) + trigger <= 0; + else + if((cycle_count > cycles)|(packet_count > packets)) + trigger <= 1; + else + trigger <= 0; + +endmodule // trigger_context_pkt diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v index 662cdca62..00da4c6e1 100644 --- a/fpga/usrp2/vrt/vita_tx_chain.v +++ b/fpga/usrp2/vrt/vita_tx_chain.v @@ -3,7 +3,9 @@ module vita_tx_chain #(parameter BASE_CTRL=0, parameter BASE_DSP=0, parameter REPORT_ERROR=0, - parameter PROT_ENG_FLAGS=0) + parameter DO_FLOW_CONTROL=0, + parameter PROT_ENG_FLAGS=0, + parameter USE_TRANS_HEADER=0) (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, @@ -24,22 +26,27 @@ module vita_tx_chain wire trigger, sent; wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire error; + wire error, packet_consumed; wire [31:0] error_code; wire clear_seqnum; + wire [31:0] current_seqnum; - assign underrun = error; + assign underrun = error & ~(error_code == 1); assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed(clear_seqnum)); - vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer + vita_tx_deframer #(.BASE(BASE_CTRL), + .MAXCHAN(MAXCHAN), + .USE_TRANS_HEADER(USE_TRANS_HEADER)) + vita_tx_deframer (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .current_seqnum(current_seqnum), .debug(debug_vtd) ); vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control @@ -47,7 +54,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time),.error(error),.error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run), .strobe(strobe_tx), + .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed), .debug(debug_vtc) ); dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx @@ -57,15 +64,33 @@ module vita_tx_chain .dac_a(dac_a),.dac_b(dac_b), .debug(debug_tx_dsp) ); - generate - if(REPORT_ERROR==1) - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt - (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(error), .sent(), - .streamid(streamid), .vita_time(vita_time), .message(message), - .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); - endgenerate + wire [35:0] flow_data, err_data_int; + wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int; + + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(32'd0), + .seqnum0(current_seqnum), .seqnum1(32'd0), + .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy)); + trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .packet_consumed(packet_consumed), .trigger(trigger)); + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(error & (REPORT_ERROR==1)), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .seqnum0(current_seqnum), .seqnum1(32'd0), + .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); + assign debug = debug_vtc | debug_vtd; + fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages + (.clk(clk), .reset(reset), .clear(clear_vita), + .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int), + .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + endmodule // vita_tx_chain diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v index d0516bec8..936762212 100644 --- a/fpga/usrp2/vrt/vita_tx_control.v +++ b/fpga/usrp2/vrt/vita_tx_control.v @@ -8,7 +8,8 @@ module vita_tx_control input [63:0] vita_time, output error, output reg [31:0] error_code, - + output reg packet_consumed, + // From vita_tx_deframer input [5+64+16+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, @@ -48,6 +49,7 @@ module vita_tx_control localparam IBS_ERROR_DONE = 4; localparam IBS_ERROR_WAIT = 5; + wire [31:0] CODE_EOB_ACK = {seqnum,16'd1}; wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8}; @@ -106,7 +108,11 @@ module vita_tx_control end else if(eop) if(eob) - ibs_state <= IBS_IDLE; + begin + ibs_state <= IBS_ERROR_DONE; // Not really an error + error_code <= CODE_EOB_ACK; + send_error <= 1; + end else ibs_state <= IBS_CONT_BURST; @@ -154,9 +160,14 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - //assign error = (ibs_state == IBS_ERROR_DONE); assign error = send_error; + always @(posedge clk) + if(reset) + packet_consumed <= 0; + else + packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; + assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v index f9cd7d00d..7fb8e3893 100644 --- a/fpga/usrp2/vrt/vita_tx_deframer.v +++ b/fpga/usrp2/vrt/vita_tx_deframer.v @@ -1,7 +1,8 @@ module vita_tx_deframer #(parameter BASE=0, - parameter MAXCHAN=1) + parameter MAXCHAN=1, + parameter USE_TRANS_HEADER=0) (input clk, input reset, input clear, input clear_seqnum, input set_stb, input [7:0] set_addr, input [31:0] set_data, @@ -13,6 +14,8 @@ module vita_tx_deframer output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, + + output [31:0] current_seqnum, // FIFO Levels output [15:0] fifo_occupied, @@ -45,58 +48,80 @@ module vita_tx_deframer reg [1:0] vector_phase; wire line_done; - reg seqnum_err; - reg [3:0] seqnum_reg; - wire [3:0] seqnum = data_i[19:16]; - wire [3:0] next_seqnum = seqnum_reg + 4'd1; + wire [31:0] seqnum = data_i; + reg [31:0] seqnum_reg; + wire [31:0] next_seqnum = seqnum_reg + 32'd1; + wire [3:0] vita_seqnum = data_i[19:16]; + reg [3:0] vita_seqnum_reg; + wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; + reg seqnum_err; + + assign current_seqnum = seqnum_reg; // Output FIFO for packetized data - localparam VITA_HEADER = 0; - localparam VITA_STREAMID = 1; - localparam VITA_CLASSID = 2; - localparam VITA_CLASSID2 = 3; - localparam VITA_SECS = 4; - localparam VITA_TICS = 5; - localparam VITA_TICS2 = 6; - localparam VITA_PAYLOAD = 7; - localparam VITA_STORE = 8; - localparam VITA_TRAILER = 9; - + localparam VITA_TRANS_HEADER = 0; + localparam VITA_HEADER = 1; + localparam VITA_STREAMID = 2; + localparam VITA_CLASSID = 3; + localparam VITA_CLASSID2 = 4; + localparam VITA_SECS = 5; + localparam VITA_TICS = 6; + localparam VITA_TICS2 = 7; + localparam VITA_PAYLOAD = 8; + localparam VITA_STORE = 9; + localparam VITA_TRAILER = 10; + localparam VITA_DUMP = 11; + wire [15:0] hdr_len = 2 + has_streamid_reg + has_classid_reg + has_classid_reg + has_secs_reg + has_tics_reg + has_tics_reg + has_trailer_reg; - wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets? + wire vita_eof = (pkt_len==hdr_len); + wire eop = eof | vita_eof; // FIXME would ignoring eof allow larger VITA packets? wire fifo_space; always @(posedge clk) if(reset | clear_seqnum) - seqnum_reg <= 4'hF; + begin + seqnum_reg <= 32'hFFFF_FFFF; + vita_seqnum_reg <= 4'hF; + end else - if((vita_state==VITA_HEADER) & src_rdy_i) - seqnum_reg <= seqnum; + begin + if((vita_state==VITA_TRANS_HEADER) & src_rdy_i) + seqnum_reg <= seqnum; + if((vita_state==VITA_HEADER) & src_rdy_i) + vita_seqnum_reg <= vita_seqnum; + end // else: !if(reset | clear_seqnum) always @(posedge clk) if(reset | clear) begin - vita_state <= VITA_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; seqnum_err <= 0; end else if((vita_state == VITA_STORE) & fifo_space) - if(eop) - if(has_trailer_reg) + if(vita_eof) + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; + else if(has_trailer_reg) vita_state <= VITA_TRAILER; else - vita_state <= VITA_HEADER; - else + vita_state <= VITA_DUMP; + else begin vita_state <= VITA_PAYLOAD; pkt_len <= pkt_len - 1; end else if(src_rdy_i) case(vita_state) + VITA_TRANS_HEADER : + begin + seqnum_err <= ~(seqnum == next_seqnum); + vita_state <= VITA_HEADER; + end VITA_HEADER : begin {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} @@ -113,7 +138,7 @@ module vita_tx_deframer vita_state <= VITA_TICS; else vita_state <= VITA_PAYLOAD; - seqnum_err <= ~(seqnum == next_seqnum); + seqnum_err <= seqnum_err | ~(vita_seqnum == next_vita_seqnum); end // case: VITA_HEADER VITA_STREAMID : if(has_classid_reg) @@ -151,11 +176,17 @@ module vita_tx_deframer else vector_phase <= vector_phase + 1; VITA_TRAILER : - vita_state <= VITA_HEADER; + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; + else + vita_state <= VITA_DUMP; + VITA_DUMP : + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; VITA_STORE : ; default : - vita_state <= VITA_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; endcase // case (vita_state) assign line_done = (vector_phase == numchan); @@ -191,7 +222,7 @@ module vita_tx_deframer // sob, eob, has_secs (send_at) ignored on all lines except first assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop, - 12'd0,seqnum_reg,send_time}; + 12'd0,seqnum_reg[3:0],send_time}; assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; |