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authorMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
committerMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
commitfd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch)
tree3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp2/coregen
parent3b66804e41891e358c790b453a7a59ec7462dba4 (diff)
downloaduhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz
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uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp2/coregen')
-rw-r--r--fpga/usrp2/coregen/.gitignore3
-rw-r--r--fpga/usrp2/coregen/Makefile.srcs27
-rw-r--r--fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs18
-rw-r--r--fpga/usrp2/coregen/coregen.cgp22
-rw-r--r--fpga/usrp2/coregen/coregen_s6.cgc2352
-rw-r--r--fpga/usrp2/coregen/coregen_s6.cgp22
-rw-r--r--fpga/usrp2/coregen/fifo_generator_release_notes.txt160
-rw-r--r--fpga/usrp2/coregen/fifo_generator_ug175.pdfbin2895895 -> 0 bytes
-rw-r--r--fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy49
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-rw-r--r--fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl72
-rw-r--r--fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy49
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-rw-r--r--fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl72
-rw-r--r--fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy49
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-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl84
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise30
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf0
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-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise72
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt12
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt46
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl68
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy49
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc3
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym74
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-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco82
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise30
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf0
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-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise72
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-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt47
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl68
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise30
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-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco84
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise72
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt12
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-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl68
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso3
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt109
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt8
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise28
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-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc3
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-rwxr-xr-xfpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf72
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-rwxr-xr-xfpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key5
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183 files changed, 0 insertions, 18480 deletions
diff --git a/fpga/usrp2/coregen/.gitignore b/fpga/usrp2/coregen/.gitignore
deleted file mode 100644
index 956cab52b..000000000
--- a/fpga/usrp2/coregen/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-/xlnx_auto*
-/*log
-/tmp
diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs
deleted file mode 100644
index a3a5d826d..000000000
--- a/fpga/usrp2/coregen/Makefile.srcs
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright 2010 Ettus Research LLC
-#
-
-##################################################
-# Coregen Sources
-##################################################
-COREGEN_SRCS = $(abspath $(addprefix $(BASE_DIR)/../coregen/, \
-fifo_xlnx_2Kx36_2clk.v \
-fifo_xlnx_2Kx36_2clk.xco \
-fifo_xlnx_512x36_2clk.v \
-fifo_xlnx_512x36_2clk.xco \
-fifo_xlnx_64x36_2clk.v \
-fifo_xlnx_64x36_2clk.xco \
-fifo_xlnx_16x19_2clk.v \
-fifo_xlnx_16x19_2clk.xco \
-fifo_xlnx_16x40_2clk.v \
-fifo_xlnx_16x40_2clk.xco \
-fifo_xlnx_32x36_2clk.v \
-fifo_xlnx_32x36_2clk.xco \
-fifo_xlnx_512x36_2clk_36to18.v \
-fifo_xlnx_512x36_2clk_36to18.xco \
-fifo_xlnx_512x36_2clk_18to36.v \
-fifo_xlnx_512x36_2clk_18to36.xco \
-fifo_xlnx_512x36_2clk_prog_full.v \
-fifo_xlnx_512x36_2clk_prog_full.xco \
-))
diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index e7bbdb9d5..000000000
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diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp
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index dd85a7f50..000000000
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index 90b359eab..000000000
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- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">CLKFB_IN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">CLKFB_IN_P</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">CLKFB_IN_N</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">CLKFB_OUT</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">CLKFB_OUT_P</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">CLKFB_OUT_N</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">lin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">DONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">RESET</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">LOCKED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">POWER_DOWN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">CLK_IN_SEL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">INPUT_CLK_STOPPED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">CLKFB_STOPPED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_DCM">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_NOTES">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKDV_DIVIDE">2.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKFX_DIVIDE">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKFX_MULTIPLY">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKIN_DIVIDE_BY_2">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKIN_PERIOD">25.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKOUT_PHASE_SHIFT">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_DESKEW_ADJUST">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_PHASE_SHIFT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_FEEDBACK">1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_STARTUP_WAIT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT1_PORT">CLKFX</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT2_PORT">CLK0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT3_PORT">CLKFX</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT4_PORT">CLKFX</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT5_PORT">CLK0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT6_PORT">CLK0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_DCM_CLKGEN">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_NOTES">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_MULTIPLY">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFXDV_DIVIDE">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_MD_MAX">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_STARTUP_WAIT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_SPREAD_SPECTRUM">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT1_PORT">CLKFX</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT2_PORT">CLKFX</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT3_PORT">CLKFX</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">15</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">25.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">15</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_PLL_CASCADE">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">AUTO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">DCM_SP</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMPONENT_NAME">pll_100_40_75</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">lin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">PLL_BASE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">40.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary__________40.000____________0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______252.791____220.216</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2____40.000______0.000______50.0______309.264____220.216</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3____75.000______0.000______50.0______269.846____220.216</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output </spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">40.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">75.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">75.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">N/A</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">N/A</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">N/A</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">N/A</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">N/A</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">N/A</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">N/A</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">N/A</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKDV_DIVIDE">2.000</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKFX_MULTIPLY">5</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_FEEDBACK">1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_FEEDBACK_PORT">CLKOUT2</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_PHASE_SHIFT">0</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_OUT3_PORT">CLKFX</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_OUT4_PORT">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_OUT5_PORT">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_OUT6_PORT">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_NOTES">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLKFXDV_DIVIDE">2</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLK_OUT2_PORT">CLKFX</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLK_OUT3_PORT">CLKFX</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_PLL_CASCADE">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">CLK_IN1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">CLK_IN2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">CLK_OUT1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">CLK_OUT2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">CLK_OUT3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">CLK_OUT4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">CLK_OUT5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">CLK_OUT6</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">RESET</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">LOCKED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">CLKFB_IN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">CLKFB_IN_P</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">CLKFB_IN_N</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">CLKFB_OUT</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">CLKFB_OUT_P</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">CLKFB_OUT_N</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">POWER_DOWN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">DADDR</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">DCLK</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">DRDY</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">DWE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">DIN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">DOUT</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">DEN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">PSCLK</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">PSINCDEC</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">PSDONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">CLK_IN_SEL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">INPUT_CLK_STOPPED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">CLKFB_STOPPED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">250.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
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- <xilinx:userFileType>txt</xilinx:userFileType>
- <xilinx:timeStamp>Mon Jun 25 01:22:09 GMT 2012</xilinx:timeStamp>
- <xilinx:checkSum>0x1BF90E4F</xilinx:checkSum>
- <xilinx:generationId>generationID_4013899584</xilinx:generationId>
- </xilinx:file>
- </xilinx:fileSet>
- <xilinx:fileSet>
- <xilinx:name>asy_generator</xilinx:name>
- <xilinx:file>
- <xilinx:name>./pll_100_40_75.asy</xilinx:name>
- <xilinx:userFileType>asy</xilinx:userFileType>
- <xilinx:timeStamp>Mon Jun 25 01:22:17 GMT 2012</xilinx:timeStamp>
- <xilinx:checkSum>0x61F47740</xilinx:checkSum>
- <xilinx:generationId>generationID_4013899584</xilinx:generationId>
- </xilinx:file>
- </xilinx:fileSet>
- <xilinx:fileSet>
- <xilinx:name>ise_generator</xilinx:name>
- <xilinx:file>
- <xilinx:name>./_xmsgs/pn_parser.xmsgs</xilinx:name>
- <xilinx:userFileType>ignore</xilinx:userFileType>
- <xilinx:userFileType>unknown</xilinx:userFileType>
- <xilinx:timeStamp>Mon Jun 25 01:22:24 GMT 2012</xilinx:timeStamp>
- <xilinx:checkSum>0xEDD97934</xilinx:checkSum>
- <xilinx:generationId>generationID_4013899584</xilinx:generationId>
- </xilinx:file>
- <xilinx:file>
- <xilinx:name>./pll_100_40_75.gise</xilinx:name>
- <xilinx:userFileType>ignore</xilinx:userFileType>
- <xilinx:userFileType>gise</xilinx:userFileType>
- <xilinx:timeStamp>Mon Jun 25 01:22:25 GMT 2012</xilinx:timeStamp>
- <xilinx:checkSum>0x3AB6E652</xilinx:checkSum>
- <xilinx:generationId>generationID_4013899584</xilinx:generationId>
- </xilinx:file>
- <xilinx:file>
- <xilinx:name>./pll_100_40_75.xise</xilinx:name>
- <xilinx:userFileType>ignore</xilinx:userFileType>
- <xilinx:userFileType>xise</xilinx:userFileType>
- <xilinx:timeStamp>Mon Jun 25 01:22:25 GMT 2012</xilinx:timeStamp>
- <xilinx:checkSum>0xAD3860B6</xilinx:checkSum>
- <xilinx:generationId>generationID_4013899584</xilinx:generationId>
- </xilinx:file>
- </xilinx:fileSet>
- <xilinx:fileSet>
- <xilinx:name>deliver_readme_generator</xilinx:name>
- </xilinx:fileSet>
- <xilinx:fileSet>
- <xilinx:name>flist_generator</xilinx:name>
- <xilinx:file>
- <xilinx:name>./pll_100_40_75_flist.txt</xilinx:name>
- <xilinx:userFileType>ignore</xilinx:userFileType>
- <xilinx:userFileType>txtFlist</xilinx:userFileType>
- <xilinx:userFileType>txt</xilinx:userFileType>
- <xilinx:timeStamp>Mon Jun 25 01:22:25 GMT 2012</xilinx:timeStamp>
- <xilinx:checkSum>0x4D0B8946</xilinx:checkSum>
- <xilinx:generationId>generationID_4013899584</xilinx:generationId>
- </xilinx:file>
- </xilinx:fileSet>
- <xilinx:fileSet>
- <xilinx:name>view_readme_generator</xilinx:name>
- </xilinx:fileSet>
- </xilinx:generationHistory>
- </spirit:vendorExtensions>
- </spirit:componentInstance>
- </spirit:componentInstances>
- <spirit:vendorExtensions>
- <xilinx:instanceProperties>
- <xilinx:projectOptions>
- <xilinx:projectName>coregen_s6</xilinx:projectName>
- <xilinx:outputDirectory>./</xilinx:outputDirectory>
- <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
- <xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
- </xilinx:projectOptions>
- <xilinx:part>
- <xilinx:device>xc6slx75</xilinx:device>
- <xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
- <xilinx:package>csg484</xilinx:package>
- <xilinx:speedGrade>-3</xilinx:speedGrade>
- </xilinx:part>
- <xilinx:flowOptions>
- <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
- <xilinx:designEntry>Verilog</xilinx:designEntry>
- <xilinx:asySymbol>true</xilinx:asySymbol>
- <xilinx:flowVendor>Other</xilinx:flowVendor>
- <xilinx:addPads>false</xilinx:addPads>
- <xilinx:removeRPMs>false</xilinx:removeRPMs>
- <xilinx:createNDF>false</xilinx:createNDF>
- <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
- <xilinx:formalVerification>false</xilinx:formalVerification>
- </xilinx:flowOptions>
- <xilinx:simulationOptions>
- <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
- <xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
- <xilinx:foundationSym>false</xilinx:foundationSym>
- </xilinx:simulationOptions>
- </xilinx:instanceProperties>
- </spirit:vendorExtensions>
-</spirit:design>
-
diff --git a/fpga/usrp2/coregen/coregen_s6.cgp b/fpga/usrp2/coregen/coregen_s6.cgp
deleted file mode 100644
index 1abd1b021..000000000
--- a/fpga/usrp2/coregen/coregen_s6.cgp
+++ /dev/null
@@ -1,22 +0,0 @@
-# Date: Fri May 4 20:42:23 2012
-
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx75
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-SET workingdirectory = ./tmp/
-
-# CRC: f7d4ca66
diff --git a/fpga/usrp2/coregen/fifo_generator_release_notes.txt b/fpga/usrp2/coregen/fifo_generator_release_notes.txt
deleted file mode 100644
index 554ec87f4..000000000
--- a/fpga/usrp2/coregen/fifo_generator_release_notes.txt
+++ /dev/null
@@ -1,160 +0,0 @@
-COPYRIGHT (c) 2006, 2007 XILINX, INC.
-ALL RIGHTS RESERVED
-
-Core name : FIFO Generator
-Version : v4.1
-Release Date : August 8, 2007
-File : fifo_generator_release_notes.txt
-
-Revision History
-Date By Version Change Description
-========================================================================
-09/2006 Xilinx, Inc. 3.2 Initial creation.
-02/2007 Xilinx, Inc. 3.3 Revised for v3.3.
-02/2007 Xilinx, Inc. 3.3 Revised for v3.3 rev 1.
-08/2007 Xilinx, Inc. 3.4 Revised for v4.1.
-========================================================================
-
-INTRODUCTION
-RELEASE NOTES
- 1. General Core Design
- 1.1 Enhancements
- 1.2 Resolved Issues
- 1.3 Outstanding Issues
- 2. General Simulation
- 2.1 Enhancements
- 2.2 Resolved Issues
- 2.3 Outstanding Issues
- 3. Documentation
- 3.1 Enhancements
- 3.2 Resolved Issues
- 3.3 Outstanding Issues
-OTHER GENERAL INFORMATION
-TECHNICAL SUPPORT
-
-========================================================================
-
-INTRODUCTION
-============
-Thank you using the FIFO Generator core from Xilinx!
-In order to obtain the latest core updates and documentation,
-please visit the Intellectual Property page located at:
-http://www.xilinx.com/ipcenter/index.htm
-This document contains the release notes for FIFO Generator v4.1
-which includes enhancements, resolved issues and outstanding known
-issues. For release notes and known issues for CORE Generator 9.2i IP
-Update 1 and FIFO Generator v4.1 please see Answer Record 25222.
-
-RELEASE NOTES
-=============
-This section lists any enhancements, resolved issues and outstanding
-known issues.
-
-
-1. General Core Design
- 1.1 Enhancements
- 1.1.1 Error Correction Checking (ECC) feature support for
- Virtex-5 block RAM FIFO configurations
-
- 1.1.2 Full range data count widths now supported for non-symmetric
- aspect ratio configurations
-
- 1.1.3 Option to define asynchronous reset value for full condition
- flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM,
- distributed RAM and shift RAM-based FIFO configurations only
-
- 1.1.4 Support added for use embedded output registers in block RAM
- FIFO configurations (Virtex-4 and Virtex-5 only)
-
- 1.2 Resolved Issues
- 1.2.1 Coregen GUI - For built-in FIFOs, GUI reports incorrect
- number of built-in FIFO primitives used.
- Change request: 4433738
-
- 1.2.2 Programmable full flag is always asserted even when FIFO is
- empty due to incorrect threshold setting.
- Change request: 435835
-
- 1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol
- .. , these pins should be connected to the same signal" occur
- during MAP when targeting Virtex-4 and Virtex-5.
- Change request: 338260
-
- 1.2.4 Write Data Count and Read Data Count overestimate the number
- of words written or read when core is configured with this
- combination of options: First-Word-Fall-Through(FWFT),
- accurate data count using extra logic, non-symmetric port
- aspect ratio.
- Change request: 436886
-
- 1.2.5 SBITERR and DBITERR outputs are not driven in behavior
- models.
- Change request: 433637
-
- 1.2.6 Maximum programmable empty threshold negate value is
- incorrect.
- Change request: 433921
-
- 1.2.7 Programmable full flag behavior is incorrect when the
- core is configured with this combination of options:
- FWFT, non-symmetric port aspect ratio, single or
- multiple programmable full threshold input port.
- Change request: 435874
-
- 1.2.8 Programmable empty flag stuck high when the core is
- configured with this combination of options: block or
- distributed RAM FIFO, single or multiple programmable
- empty threshold input port.
- Change request: 443569
-
- 1.3 Outstanding Issues
- 1.3.1 "WARNING:Ngdbuild:452 - logical net
- 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during
- NgdBuild although programmable empty or full is not selected.
- Warnings can be safely ignored.
- Change request: 431975
-
-2. General Simulation
- 2.1 Enhancements
- None at this time.
-
- 2.2 Resolved Issues
- None at this time.
-
- 2.3 Outstanding Issues
- 2.3.1 Ncelab warnings during Verilog structural and timing simulations
- in ncsim for Virtex5 Block RAM FIFOs.
- The simulations will be successful, but there will be warnings
- similar to the following in the log file: "memory index out of
- declared bounds" in simprims_ver_virtex5_source.v or
- unisims_ver_virtex5_source.v. Cadence does not want to fix this
- issue. These warning messages can safely be ignored.
- Change request: 423374, 423375
-
-3. Documentation
- 3.1 Enhancements
- 3.1.1 Added clarification on FIFO flag latency.
-
- 3.1.1 Added clarification on actual FIFO depth.
-
- 3.2 Resolved Issues
- None at this time.
-
- 3.3 Outstanding Issues
- None at this time.
-
-
-TECHNICAL SUPPORT
-=================
-The fastest method for obtaining specific technical support for the
-FIFO Generator core is through the http://support.xilinx.com/
-website. Questions are routed to a team of engineers with specific
-expertise in using the FIFO Generator core. Xilinx will provide
-technical support for use of this product as described in the FIFO
-Generator Datasheet. Xilinx cannot guarantee timing, functionality,
-or support of this product for designs that do not follow these
-guidelines.
-
-
-
-
diff --git a/fpga/usrp2/coregen/fifo_generator_ug175.pdf b/fpga/usrp2/coregen/fifo_generator_ug175.pdf
deleted file mode 100644
index 5fba6029c..000000000
--- a/fpga/usrp2/coregen/fifo_generator_ug175.pdf
+++ /dev/null
Binary files differ
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy
deleted file mode 100644
index 9664f3a57..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy
+++ /dev/null
@@ -1,49 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 fifo_s6_1Kx36_2clk
-RECTANGLE Normal 32 32 544 768
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName wr_clk
-PINATTR Polarity IN
-LINE Normal 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName rd_clk
-PINATTR Polarity IN
-LINE Normal 144 800 144 768
-PIN 144 800 BOTTOM 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 576 80 544 80
-PIN 576 80 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 576 208 544 208
-PIN 576 208 RIGHT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Wide 576 368 544 368
-PIN 576 368 RIGHT 36
-PINATTR PinName wr_data_count[10:0]
-PINATTR Polarity OUT
-LINE Normal 576 432 544 432
-PIN 576 432 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-LINE Wide 576 592 544 592
-PIN 576 592 RIGHT 36
-PINATTR PinName rd_data_count[10:0]
-PINATTR Polarity OUT
-
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise
deleted file mode 100644
index 90240bfb2..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise
+++ /dev/null
@@ -1,31 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_s6_1Kx36_2clk.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_s6_1Kx36_2clk.asy" xil_pn:origination="imported"/>
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_s6_1Kx36_2clk.veo" xil_pn:origination="imported"/>
- </files>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc
deleted file mode 100644
index f7e21b27e..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v
deleted file mode 100644
index 593d3f82c..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v
+++ /dev/null
@@ -1,173 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_s6_1Kx36_2clk.v when simulating
-// the core, fifo_s6_1Kx36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_s6_1Kx36_2clk(
- rst,
- wr_clk,
- rd_clk,
- din,
- wr_en,
- rd_en,
- dout,
- full,
- empty,
- rd_data_count,
- wr_data_count);
-
-
-input rst;
-input wr_clk;
-input rd_clk;
-input [35 : 0] din;
-input wr_en;
-input rd_en;
-output [35 : 0] dout;
-output full;
-output empty;
-output [10 : 0] rd_data_count;
-output [10 : 0] wr_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V6_1 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(10),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(36),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(36),
- .C_ENABLE_RLOCS(0),
- .C_ENABLE_RST_SYNC(1),
- .C_ERROR_INJECTION_TYPE(0),
- .C_FAMILY("spartan6"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(1),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("1kx36"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(1023),
- .C_PROG_FULL_THRESH_NEGATE_VAL(1022),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(11),
- .C_RD_DEPTH(1024),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(10),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(1),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(11),
- .C_WR_DEPTH(1024),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(10),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .RST(rst),
- .WR_CLK(wr_clk),
- .RD_CLK(rd_clk),
- .DIN(din),
- .WR_EN(wr_en),
- .RD_EN(rd_en),
- .DOUT(dout),
- .FULL(full),
- .EMPTY(empty),
- .RD_DATA_COUNT(rd_data_count),
- .WR_DATA_COUNT(wr_data_count),
- .BACKUP(),
- .BACKUP_MARKER(),
- .CLK(),
- .SRST(),
- .WR_RST(),
- .RD_RST(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .INT_CLK(),
- .INJECTDBITERR(),
- .INJECTSBITERR(),
- .ALMOST_FULL(),
- .WR_ACK(),
- .OVERFLOW(),
- .ALMOST_EMPTY(),
- .VALID(),
- .UNDERFLOW(),
- .DATA_COUNT(),
- .PROG_FULL(),
- .PROG_EMPTY(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo
deleted file mode 100644
index e348767a3..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_s6_1Kx36_2clk YourInstanceName (
- .rst(rst),
- .wr_clk(wr_clk),
- .rd_clk(rd_clk),
- .din(din), // Bus [35 : 0]
- .wr_en(wr_en),
- .rd_en(rd_en),
- .dout(dout), // Bus [35 : 0]
- .full(full),
- .empty(empty),
- .rd_data_count(rd_data_count), // Bus [10 : 0]
- .wr_data_count(wr_data_count)); // Bus [10 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_s6_1Kx36_2clk.v when simulating
-// the core, fifo_s6_1Kx36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco
deleted file mode 100644
index 14ad27c2a..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.1
-# Date: Fri May 4 20:49:07 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx75
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.1
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_s6_1Kx36_2clk
-CSET data_count=false
-CSET data_count_width=10
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=1023
-CSET full_threshold_negate_value=1022
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=36
-CSET input_depth=1024
-CSET output_data_width=36
-CSET output_depth=1024
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=11
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=true
-CSET write_data_count_width=11
-# END Parameters
-GENERATE
-# CRC: 5f5a2e48
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise
deleted file mode 100644
index b6109869c..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise
+++ /dev/null
@@ -1,392 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="fifo_s6_1Kx36_2clk.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- </file>
- <file xil_pn:name="fifo_s6_1Kx36_2clk.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
- <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
- <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
- <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
- <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
- <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading par" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
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- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_s6_1Kx36_2clk" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-04T13:49:09" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="334FF80B875B41AA9C000F6D67B92F9C" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt
deleted file mode 100644
index 4f5b34b9b..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# Output products list for <fifo_s6_1Kx36_2clk>
-_xmsgs/pn_parser.xmsgs
-fifo_generator_ug175.pdf
-fifo_s6_1Kx36_2clk.asy
-fifo_s6_1Kx36_2clk.gise
-fifo_s6_1Kx36_2clk.ngc
-fifo_s6_1Kx36_2clk.v
-fifo_s6_1Kx36_2clk.veo
-fifo_s6_1Kx36_2clk.xco
-fifo_s6_1Kx36_2clk.xise
-fifo_s6_1Kx36_2clk_flist.txt
-fifo_s6_1Kx36_2clk_readme.txt
-fifo_s6_1Kx36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt
deleted file mode 100644
index b101bd8cf..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-The following files were generated for 'fifo_s6_1Kx36_2clk' in directory
-/home/matt/fpgapriv/usrp2/coregen/
-
-fifo_generator_ug175.pdf:
- Please see the core data sheet.
-
-fifo_s6_1Kx36_2clk.asy:
- Graphical symbol information file. Used by the ISE tools and some
- third party tools to create a symbol representing the core.
-
-fifo_s6_1Kx36_2clk.gise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_s6_1Kx36_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_s6_1Kx36_2clk.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_s6_1Kx36_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_s6_1Kx36_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_s6_1Kx36_2clk.xise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_s6_1Kx36_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_s6_1Kx36_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-fifo_s6_1Kx36_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl
deleted file mode 100644
index f9a9ac233..000000000
--- a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl
+++ /dev/null
@@ -1,72 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_s6_1Kx36_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_s6_1Kx36_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_s6_1Kx36_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_1Kx36_2clk
-}
-# ::fifo_s6_1Kx36_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_s6_1Kx36_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_1Kx36_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy
deleted file mode 100644
index 0b429a886..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy
+++ /dev/null
@@ -1,49 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 fifo_s6_2Kx36_2clk
-RECTANGLE Normal 32 32 544 768
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName wr_clk
-PINATTR Polarity IN
-LINE Normal 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName rd_clk
-PINATTR Polarity IN
-LINE Normal 144 800 144 768
-PIN 144 800 BOTTOM 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 576 80 544 80
-PIN 576 80 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 576 208 544 208
-PIN 576 208 RIGHT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Wide 576 368 544 368
-PIN 576 368 RIGHT 36
-PINATTR PinName wr_data_count[11:0]
-PINATTR Polarity OUT
-LINE Normal 576 432 544 432
-PIN 576 432 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-LINE Wide 576 592 544 592
-PIN 576 592 RIGHT 36
-PINATTR PinName rd_data_count[11:0]
-PINATTR Polarity OUT
-
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise
deleted file mode 100644
index d90a25595..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise
+++ /dev/null
@@ -1,31 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_s6_2Kx36_2clk.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_s6_2Kx36_2clk.asy" xil_pn:origination="imported"/>
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_s6_2Kx36_2clk.veo" xil_pn:origination="imported"/>
- </files>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc
deleted file mode 100644
index 994b767ea..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v
deleted file mode 100644
index 9f2cc7d4e..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v
+++ /dev/null
@@ -1,173 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_s6_2Kx36_2clk.v when simulating
-// the core, fifo_s6_2Kx36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_s6_2Kx36_2clk(
- rst,
- wr_clk,
- rd_clk,
- din,
- wr_en,
- rd_en,
- dout,
- full,
- empty,
- rd_data_count,
- wr_data_count);
-
-
-input rst;
-input wr_clk;
-input rd_clk;
-input [35 : 0] din;
-input wr_en;
-input rd_en;
-output [35 : 0] dout;
-output full;
-output empty;
-output [11 : 0] rd_data_count;
-output [11 : 0] wr_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V6_1 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(11),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(36),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(36),
- .C_ENABLE_RLOCS(0),
- .C_ENABLE_RST_SYNC(1),
- .C_ERROR_INJECTION_TYPE(0),
- .C_FAMILY("spartan6"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(1),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("2kx18"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(2047),
- .C_PROG_FULL_THRESH_NEGATE_VAL(2046),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(12),
- .C_RD_DEPTH(2048),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(11),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(1),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(12),
- .C_WR_DEPTH(2048),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(11),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .RST(rst),
- .WR_CLK(wr_clk),
- .RD_CLK(rd_clk),
- .DIN(din),
- .WR_EN(wr_en),
- .RD_EN(rd_en),
- .DOUT(dout),
- .FULL(full),
- .EMPTY(empty),
- .RD_DATA_COUNT(rd_data_count),
- .WR_DATA_COUNT(wr_data_count),
- .BACKUP(),
- .BACKUP_MARKER(),
- .CLK(),
- .SRST(),
- .WR_RST(),
- .RD_RST(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .INT_CLK(),
- .INJECTDBITERR(),
- .INJECTSBITERR(),
- .ALMOST_FULL(),
- .WR_ACK(),
- .OVERFLOW(),
- .ALMOST_EMPTY(),
- .VALID(),
- .UNDERFLOW(),
- .DATA_COUNT(),
- .PROG_FULL(),
- .PROG_EMPTY(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo
deleted file mode 100644
index 7657f41bc..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_s6_2Kx36_2clk YourInstanceName (
- .rst(rst),
- .wr_clk(wr_clk),
- .rd_clk(rd_clk),
- .din(din), // Bus [35 : 0]
- .wr_en(wr_en),
- .rd_en(rd_en),
- .dout(dout), // Bus [35 : 0]
- .full(full),
- .empty(empty),
- .rd_data_count(rd_data_count), // Bus [11 : 0]
- .wr_data_count(wr_data_count)); // Bus [11 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_s6_2Kx36_2clk.v when simulating
-// the core, fifo_s6_2Kx36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco
deleted file mode 100644
index 659795e5f..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.1
-# Date: Fri May 4 20:55:54 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx75
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.1
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_s6_2Kx36_2clk
-CSET data_count=false
-CSET data_count_width=11
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=2047
-CSET full_threshold_negate_value=2046
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=36
-CSET input_depth=2048
-CSET output_data_width=36
-CSET output_depth=2048
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=12
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=true
-CSET write_data_count_width=12
-# END Parameters
-GENERATE
-# CRC: e7a1c106
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise
deleted file mode 100644
index c09cc4b35..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise
+++ /dev/null
@@ -1,392 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="fifo_s6_2Kx36_2clk.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- </file>
- <file xil_pn:name="fifo_s6_2Kx36_2clk.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
- <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
- <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
- <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
- <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
- <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading par" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_s6_2Kx36_2clk" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-04T13:55:55" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B3454C89F83BDEF9B4A09CDC070DE482" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt
deleted file mode 100644
index 3466e5f91..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# Output products list for <fifo_s6_2Kx36_2clk>
-_xmsgs/pn_parser.xmsgs
-fifo_generator_ug175.pdf
-fifo_s6_2Kx36_2clk.asy
-fifo_s6_2Kx36_2clk.gise
-fifo_s6_2Kx36_2clk.ngc
-fifo_s6_2Kx36_2clk.v
-fifo_s6_2Kx36_2clk.veo
-fifo_s6_2Kx36_2clk.xco
-fifo_s6_2Kx36_2clk.xise
-fifo_s6_2Kx36_2clk_flist.txt
-fifo_s6_2Kx36_2clk_readme.txt
-fifo_s6_2Kx36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt
deleted file mode 100644
index 3a017fbb0..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-The following files were generated for 'fifo_s6_2Kx36_2clk' in directory
-/home/matt/fpgapriv/usrp2/coregen/
-
-fifo_generator_ug175.pdf:
- Please see the core data sheet.
-
-fifo_s6_2Kx36_2clk.asy:
- Graphical symbol information file. Used by the ISE tools and some
- third party tools to create a symbol representing the core.
-
-fifo_s6_2Kx36_2clk.gise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_s6_2Kx36_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_s6_2Kx36_2clk.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_s6_2Kx36_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_s6_2Kx36_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_s6_2Kx36_2clk.xise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_s6_2Kx36_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_s6_2Kx36_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-fifo_s6_2Kx36_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl
deleted file mode 100644
index 63b4f2099..000000000
--- a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl
+++ /dev/null
@@ -1,72 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_s6_2Kx36_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_s6_2Kx36_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_s6_2Kx36_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_2Kx36_2clk
-}
-# ::fifo_s6_2Kx36_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_s6_2Kx36_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_2Kx36_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy
deleted file mode 100644
index 5adf4bfb4..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy
+++ /dev/null
@@ -1,49 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 fifo_s6_512x36_2clk
-RECTANGLE Normal 32 32 544 768
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName wr_clk
-PINATTR Polarity IN
-LINE Normal 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName rd_clk
-PINATTR Polarity IN
-LINE Normal 144 800 144 768
-PIN 144 800 BOTTOM 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 576 80 544 80
-PIN 576 80 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 576 208 544 208
-PIN 576 208 RIGHT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Wide 576 368 544 368
-PIN 576 368 RIGHT 36
-PINATTR PinName wr_data_count[9:0]
-PINATTR Polarity OUT
-LINE Normal 576 432 544 432
-PIN 576 432 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-LINE Wide 576 592 544 592
-PIN 576 592 RIGHT 36
-PINATTR PinName rd_data_count[9:0]
-PINATTR Polarity OUT
-
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise
deleted file mode 100644
index 2edb1c020..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise
+++ /dev/null
@@ -1,31 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_s6_512x36_2clk.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_s6_512x36_2clk.asy" xil_pn:origination="imported"/>
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_s6_512x36_2clk.veo" xil_pn:origination="imported"/>
- </files>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc
deleted file mode 100644
index 523080a69..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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1c4283>7p}:9883>7}Y=><01;=55648 1c4283=7p}:9983>7}Y=>?01;=55678 1c4283<7p}:9683>7}Y=>>01;=55668 1c428327p}:9783>7}Y=>901;=55618 1c4283j7p}:b883>7}Y=0>01;=55868 1c4283i7p}:b983>7}Y=0901;=55818 1c4283h7p}:b683>7}Y=0801;=55808 1c4283o7p}:b783>7}Y=0;01;=55838 1c4283n7p}:b483>7}Y=0:01;=55828 1c4283m7p}:b583>7}Y=1l01;=559d8 1c428k;7p}:b283>7}Y=1201;=559:8 1c428k:7p}:ac83>7}Y=>n01;=556f8 1c428k97p}:a183>7}Y=>801;=55608 1c428k?7p}:9483>7}Y=>;01;=55638 1c428k>7p}:c083>7}Y=j;01;=55b38 1c428k=7p}:bc83>7}Y=kh01;=55c`8 1c428k<7p}91`83>7}Y>9l01;=561d8 1c428k27p}91983>7}Y>9o01;=561g8 1c428ki7p}91683>7}Y>9n01;=561f8 1c428kh7p}91783>7}Y>9i01;=561a8 1c428ko7p}91483>7}Y>9h01;=561`8 1c428kn7p}91583>7}Y>9k01;=561c8 1c428km7p}91283>7}Y>9301;=561;8 1c428h;7p}91383>7}Y>9201;=561:8 1c428h:7p}91083>7}Y>9=01;=56158 1c428h97p}91183>7}Y>9<01;=56148 1c428h87p}93883>7}Y>;o01;=563g8 1c428h?7p}93683>7}Y>;n01;=563f8 1c428h=7p}93783>7}Y>;i01;=563a8 1c428h<7p}93483>7}Y>;h01;=563`8 1c428h37p}93583>7}Y>;k01;=563c8 1c428h27p}93283>7}Y>;301;=563;8 1c428hj7p}93383>7}Y>;201;=563:8 1c428hi7p}93083>7}Y>;=01;=56358 1c428hh7p}93183>7}Y>;<01;=56348 1c428ho7p}92g83>7}Y>;?01;=56378 1c428hn7psab`f94?4|@=o?7p`mad83>7}O<l>0qclnf;296~N3m=1vbol?:181M2b<2weno?50;0xL1c33tdin?4?:3yK0`2<ughi?7>52zJ7a1=zfkh?6=4={I6f0>{ijk?1<7<tH5g7?xhej?0;6?uG4d68ykde?3:1>vF;e59~jgd?2909wE:j4:mfg?=838pD9k;;|lafd<72;qC8h:4}o`af?6=:rB?i95rnc``>5<5sA>n86sabcf94?4|@=o?7p`mbd83>7}O<l>0qclmf;296~N3m=1vbom?:181M2b<2wenn?50;0xL1c33tdio?4?:3yK0`2<ughh?7>52zJ7a1=zfki?6=4={I6f0>{ijj?1<7<tH5g7?xhek?0;6?uG4d68ykdd?3:1>vF;e59~jge?2909wE:j4:mff?=838pD9k;;|lagd<72;qC8h:4}o``f?6=:rB?i95rnca`>5<5sA>n86sabbf94?4|@=o?7p`mcd83>7}O<l>0qcllf;296~N3m=1vboj?:181M2b<2weni?50;0xL1c33tdih?4?:3yK0`2<ugho?7>52zJ7a1=zfkn?6=4={I6f0>{ijm?1<7<tH5g7?xhel?0;6?uG4d68ykdc?3:1>vF;e59~jgb?2909wE:j4:mfa?=838pD9k;;|la`d<72;qC8h:4}o`gf?6=:rB?i95rncf`>5<5sA>n86sabef94?4|@=o?7p`mdd83>7}O<l>0qclkf;296~N3m=1vbok?:181M2b<2wenh?50;0xL1c33tdii?4?:3yK0`2<ughn?7>52zJ7a1=zfko?6=4={I6f0>{ijl?1<7<tH5g7?xhem?0;6?uG4d68ykdb?3:1>vF;e59~jgc?2909wE:j4:mf`?=838pD9k;;|laad<72;qC8h:4}o`ff?6=:rB?i95rncg`>5<5sA>n86sabdf94?4|@=o?7p`med83>7}O<l>0qcljf;296~N3m=1vboh?:181M2b<2wenk?50;0xL1c33tdij?4?:3yK0`2<ughm?7>52zJ7a1=zfkl?6=4={I6f0>{ijo?1<7<tH5g7?xhen?0;6?uG4d68ykda?3:1>vF;e59~jg`?2909wE:j4:mfc?=838pD9k;;|labd<72;qC8h:4}o`ef?6=:rB?i95rncd`>5<5sA>n86sabgf94?4|@=o?7p`mfd83>7}O<l>0qclif;296~N3m=1vbn>?:181M2b<2weo=?50;0xL1c33tdh<?4?:3yK0`2<ugi;?7>52zJ7a1=zfj:?6=4={I6f0>{ik9?1<7<tH5g7?xhd8?0;6?uG4d68yke7?3:1>vF;e59~jf6?2909wE:j4:mg5?=838pD9k;;|l`4d<72;qC8h:4}oa3f?6=:rB?i95rnb2`>5<5sA>n86sac1f94?4|@=o?7p`l0d83>7}O<l>0qcm?f;296~N3m=1vbl>6:182M2b<2wem9:50;3xL1c33tdj884?:0yK0`2<ugk?:7>51zJ7a1=zfh><6=4>{I6f0>{ii=21<7?tH5g7?xhf<00;6<uG4d68ykg3i3:1=vF;e59~jd2e290:wE:j4:me1e=83;pD9k;;|lb0a<728qC8h:4}oc7a?6=9rB?i95rn`6e>5<6sA>n86saa4294?7|@=o?7p`n5083>4}O<l>0qco:2;295~N3m=1vbl;<:182M2b<2wem8:50;3xL1c33tdj984?:0yK0`2<ugk>:7>51zJ7a1=zfh?<6=4>{I6f0>{ii<21<7?tH5g7?xhf=00;6<uG4d68ykg2i3:1=vF;e59~jd3e290:wE:j4:me0e=83;pD9k;;|lb1a<728qC8h:4}oc6a?6=9rB?i95rn`7e>5<6sA>n86saa7294?7|@=o?7p`n6083>4}O<l>0qco92;295~N3m=1vbl8<:182M2b<2wem;:50;3xL1c33tdj:84?:0yK0`2<ugk=:7>51zJ7a1=zfh<<6=4>{I6f0>{ii?21<7?tH5g7?xhf>00;6<uG4d68ykg1i3:1=vF;e59~jd0e290:wE:j4:me3e=83;pD9k;;|lb2a<728qC8h:4}oc5a?6=9rB?i95rn`4e>5<6sA>n86saa6294?7|@=o?7p`n7083>4}O<l>0qco82;295~N3m=1vbl9<:182M2b<2wem::50;3xL1c33tdj;84?:0yK0`2<ugk<:7>51zJ7a1=zfh=<6=4>{I6f0>{ii>21<7?tH5g7?xhf?00;6<uG4d68ykg0i3:1=vF;e59~jd1e290:wE:j4:me2e=83;pD9k;;|lb3a<728qC8h:4}oc4a?6=9rB?i95rn`5e>5<6sA>n86saa9294?7|@=o?7p`n8083>4}O<l>0qco72;295~N3m=1vbl6<:182M2b<2wem5:50;3xL1c33tdj484?:0yK0`2<ugk3:7>51zJ7a1=zfh2<6=4>{I6f0>{ii121<7?tH5g7?xhf000;6<uG4d68ykg?i3:1=vF;e59~jd>e290:wE:j4:me=e=83;pD9k;;|lb<a<728qC8h:4}oc;a?6=9rB?i95rn`:e>5<6sA>n86saa8294?7|@=o?7p`n9083>4}O<l>0qco62;295~N3m=1vbl7<:182M2b<2wem4:50;3xL1c33tdj584?:0yK0`2<ugk2:7>51zJ7a1=zfh3<6=4>{I6f0>{ii021<7?tH5g7?xhf100;6<uG4d68ykg>i3:1=vF;e59~jd?e290:wE:j4:me<e=83;pD9k;;|lb=a<728qC8h:4}oc:a?6=9rB?i95rn`;e>5<6sA>n86saa`294?7|@=o?7p`na083>4}O<l>0qcon2;295~N3m=1vblo<:182M2b<2weml:50;3xL1c33tdjm84?:0yK0`2<ugkj:7>51zJ7a1=zfhk<6=4>{I6f0>{iih21<7?tH5g7?xhfi00;6<uG4d68ykgfi3:1=vF;e59~jdge290:wE:j4:mede=83;pD9k;;|lbea<728qC8h:4}ocba?6=9rB?i95rn`ce>5<6sA>n86saac294?7|@=o?7p`nb083>4}O<l>0qcom2;295~N3m=1vbll<:182M2b<2wemo:50;3xL1c33tdjn84?:0yK0`2<ugki:7>51zJ7a1=zfhh<6=4>{I6f0>{iik21<7?tH5g7?xhfj00;6<uG4d68ykgei3:1=vF;e59~jdde290:wE:j4:mege=83;pD9k;;|lbfa<728qC8h:4}ocaa?6=9rB?i95rn``e>5<6sA>n86saab294?7|@=o?7p`nc083>4}O<l>0qcol2;295~N3m=1vblm<:182M2b<2wemn:50;3xL1c33tdjo84?:0yK0`2<ugkh:7>51zJ7a1=zfhi<6=4>{I6f0>{iij21<7?tH5g7?xhfk00;6<uG4d68ykgdi3:1=vF;e59~jdee290:wE:j4:mefe=83;pD9k;;|lbga<728qC8h:4}oc`a?6=9rB?i95rn`ae>5<6sA>n86saae294?7|@=o?7p`nd083>4}O<l>0qcok2;295~N3m=1vblj<:182M2b<2wemi:50;3xL1c33tdjh84?:0yK0`2<ugko:7>51zJ7a1=zfhn<6=4>{I6f0>{iim21<7?tH5g7?xhfl00;6<uG4d68ykgci3:1=vF;e59~jdbe290:wE:j4:meae=83;pD9k;;|lb`a<728qC8h:4}ocga?6=9rB?i95rn`fe>5<6sA>n86saad294?7|@=o?7p`ne083>4}O<l>0qcoj2;295~N3m=1vblk<:182M2b<2wemh:50;3xL1c33tdji84?:0yK0`2<ugkn:7>51zJ7a1=zfho<6=4>{I6f0>{iil21<7?tH5g7?xhfm00;6<uG4d68ykgbi3:1=vF;e59~jdce290:wE:j4:me`e=83;pD9k;;|lbaa<728qC8h:4}ocfa?6=9rB?i95rn`ge>5<6sA>n86saag294?7|@=o?7p`nf083>4}O<l>0qcoi2;295~N3m=1vblh<:182M2b<2wemk:50;3xL1c33tdjj84?:0yK0`2<ugkm:7>51zJ7a1=zfhl<6=4>{I6f0>{iio21<7?tH5g7?xhfn00;6<uG4d68ykgai3:1=vF;e59~jd`e290:wE:j4:mece=83;pD9k;;|lbba<728qC8h:4}ocea?6=9rB?i95rn`de>5<6sA>n86sab1294?7|@=o?7p`m0083>4}O<l>0qcl?2;295~N3m=1vbo><:182M2b<2wen=:50;3xL1c33tdi<84?:0yK0`2<ugh;:7>51zJ7a1=zfk:<6=4>{I6f0>{ij921<7?tH5g7?xhe800;6<uG4d68ykd7i3:1=vF;e59~jg6e290:wE:j4:mf5e=83;pD9k;;|la4a<728qC8h:4}o`3a?6=9rB?i95rnc2e>5<6sA>n86sab0294?7|@=o?7p`m1083>4}O<l>0qcl>2;295~N3m=1vbo?<:182M2b<2wen<:50;3xL1c33tdi=84?:0yK0`2<ugh::7>51zJ7a1=zfk;<6=4>{I6f0>{ij821<7?tH5g7?xhe900;6<uG4d68ykd6i3:1=vF;e59~jg7e290:wE:j4:mf4e=83;pD9k;;|la5a<728qC8h:4}o`2a?6=9rB?i95rnc3e>5<6sA>n86sab3294?7|@=o?7p`m2083>4}O<l>0qcl=2;295~N3m=1vbo<<:182M2b<2wen?:50;3xL1c33tdi>84?:0yK0`2<ugh9:7>51zJ7a1=zfk8<6=4>{I6f0>{ij;21<7?tH5g7?xhe:00;6<uG4d68ykd5i3:1=vF;e59~jg4e290:wE:j4:mf7e=83;pD9k;;|la6a<728qC8h:4}o`1a?6=9rB?i95rnc0e>5<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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v
deleted file mode 100644
index 4b7a31173..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v
+++ /dev/null
@@ -1,173 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating
-// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_s6_512x36_2clk(
- rst,
- wr_clk,
- rd_clk,
- din,
- wr_en,
- rd_en,
- dout,
- full,
- empty,
- rd_data_count,
- wr_data_count);
-
-
-input rst;
-input wr_clk;
-input rd_clk;
-input [35 : 0] din;
-input wr_en;
-input rd_en;
-output [35 : 0] dout;
-output full;
-output empty;
-output [9 : 0] rd_data_count;
-output [9 : 0] wr_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V6_1 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(9),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(36),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(36),
- .C_ENABLE_RLOCS(0),
- .C_ENABLE_RST_SYNC(1),
- .C_ERROR_INJECTION_TYPE(0),
- .C_FAMILY("spartan6"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(1),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("512x36"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(511),
- .C_PROG_FULL_THRESH_NEGATE_VAL(510),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(10),
- .C_RD_DEPTH(512),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(9),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(1),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(10),
- .C_WR_DEPTH(512),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(9),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .RST(rst),
- .WR_CLK(wr_clk),
- .RD_CLK(rd_clk),
- .DIN(din),
- .WR_EN(wr_en),
- .RD_EN(rd_en),
- .DOUT(dout),
- .FULL(full),
- .EMPTY(empty),
- .RD_DATA_COUNT(rd_data_count),
- .WR_DATA_COUNT(wr_data_count),
- .BACKUP(),
- .BACKUP_MARKER(),
- .CLK(),
- .SRST(),
- .WR_RST(),
- .RD_RST(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .INT_CLK(),
- .INJECTDBITERR(),
- .INJECTSBITERR(),
- .ALMOST_FULL(),
- .WR_ACK(),
- .OVERFLOW(),
- .ALMOST_EMPTY(),
- .VALID(),
- .UNDERFLOW(),
- .DATA_COUNT(),
- .PROG_FULL(),
- .PROG_EMPTY(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo
deleted file mode 100644
index 766965d02..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_s6_512x36_2clk YourInstanceName (
- .rst(rst),
- .wr_clk(wr_clk),
- .rd_clk(rd_clk),
- .din(din), // Bus [35 : 0]
- .wr_en(wr_en),
- .rd_en(rd_en),
- .dout(dout), // Bus [35 : 0]
- .full(full),
- .empty(empty),
- .rd_data_count(rd_data_count), // Bus [9 : 0]
- .wr_data_count(wr_data_count)); // Bus [9 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating
-// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco
deleted file mode 100644
index 4f40b8702..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.1
-# Date: Fri May 4 20:46:48 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx75
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.1
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_s6_512x36_2clk
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=511
-CSET full_threshold_negate_value=510
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=36
-CSET input_depth=512
-CSET output_data_width=36
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=10
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=true
-CSET write_data_count_width=10
-# END Parameters
-GENERATE
-# CRC: a4cd75c3
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise
deleted file mode 100644
index 9f43a161e..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise
+++ /dev/null
@@ -1,392 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="fifo_s6_512x36_2clk.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- </file>
- <file xil_pn:name="fifo_s6_512x36_2clk.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
- <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
- <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
- <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
- <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
- <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading par" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
- <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
- <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
- <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
- <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_s6_512x36_2clk" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_s6_512x36_2clk.ngc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_s6_512x36_2clk" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
- <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
- <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
- <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
- <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
- <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
- <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Output File Name" xil_pn:value="fifo_s6_512x36_2clk" xil_pn:valueState="default"/>
- <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
- <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
- <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="fifo_s6_512x36_2clk_map.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="fifo_s6_512x36_2clk_timesim.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="fifo_s6_512x36_2clk_synthesis.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="fifo_s6_512x36_2clk_translate.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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- <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_s6_512x36_2clk" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-04T13:46:49" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F64CBD650BAE027D4131AE4B4B6DCBBE" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt
deleted file mode 100644
index e72108931..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# Output products list for <fifo_s6_512x36_2clk>
-_xmsgs/pn_parser.xmsgs
-fifo_generator_ug175.pdf
-fifo_s6_512x36_2clk.asy
-fifo_s6_512x36_2clk.gise
-fifo_s6_512x36_2clk.ngc
-fifo_s6_512x36_2clk.v
-fifo_s6_512x36_2clk.veo
-fifo_s6_512x36_2clk.xco
-fifo_s6_512x36_2clk.xise
-fifo_s6_512x36_2clk_flist.txt
-fifo_s6_512x36_2clk_readme.txt
-fifo_s6_512x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt
deleted file mode 100644
index 21f058c0b..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-The following files were generated for 'fifo_s6_512x36_2clk' in directory
-/home/matt/fpgapriv/usrp2/coregen/
-
-fifo_generator_ug175.pdf:
- Please see the core data sheet.
-
-fifo_s6_512x36_2clk.asy:
- Graphical symbol information file. Used by the ISE tools and some
- third party tools to create a symbol representing the core.
-
-fifo_s6_512x36_2clk.gise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_s6_512x36_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_s6_512x36_2clk.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_s6_512x36_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_s6_512x36_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_s6_512x36_2clk.xise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_s6_512x36_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_s6_512x36_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-fifo_s6_512x36_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl
deleted file mode 100644
index 150807984..000000000
--- a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl
+++ /dev/null
@@ -1,72 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_s6_512x36_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_s6_512x36_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_s6_512x36_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_512x36_2clk
-}
-# ::fifo_s6_512x36_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_s6_512x36_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_512x36_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc
deleted file mode 100644
index b12d34d7c..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.4e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v
deleted file mode 100644
index 1d633384b..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v
+++ /dev/null
@@ -1,169 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
-// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_xlnx_16x19_2clk(
- din,
- rd_clk,
- rd_en,
- rst,
- wr_clk,
- wr_en,
- dout,
- empty,
- full,
- rd_data_count,
- wr_data_count);
-
-
-input [18 : 0] din;
-input rd_clk;
-input rd_en;
-input rst;
-input wr_clk;
-input wr_en;
-output [18 : 0] dout;
-output empty;
-output full;
-output [4 : 0] rd_data_count;
-output [4 : 0] wr_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V4_3 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(5),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(19),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(19),
- .C_ENABLE_RLOCS(0),
- .C_FAMILY("spartan3"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(1),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(2),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("512x36"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(15),
- .C_PROG_FULL_THRESH_NEGATE_VAL(14),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(5),
- .C_RD_DEPTH(16),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(4),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(1),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(5),
- .C_WR_DEPTH(16),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(4),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .DIN(din),
- .RD_CLK(rd_clk),
- .RD_EN(rd_en),
- .RST(rst),
- .WR_CLK(wr_clk),
- .WR_EN(wr_en),
- .DOUT(dout),
- .EMPTY(empty),
- .FULL(full),
- .RD_DATA_COUNT(rd_data_count),
- .WR_DATA_COUNT(wr_data_count),
- .CLK(),
- .INT_CLK(),
- .BACKUP(),
- .BACKUP_MARKER(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .RD_RST(),
- .SRST(),
- .WR_RST(),
- .ALMOST_EMPTY(),
- .ALMOST_FULL(),
- .DATA_COUNT(),
- .OVERFLOW(),
- .PROG_EMPTY(),
- .PROG_FULL(),
- .VALID(),
- .UNDERFLOW(),
- .WR_ACK(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo
deleted file mode 100644
index 2e9af1efa..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_16x19_2clk YourInstanceName (
- .din(din), // Bus [18 : 0]
- .rd_clk(rd_clk),
- .rd_en(rd_en),
- .rst(rst),
- .wr_clk(wr_clk),
- .wr_en(wr_en),
- .dout(dout), // Bus [18 : 0]
- .empty(empty),
- .full(full),
- .rd_data_count(rd_data_count), // Bus [4 : 0]
- .wr_data_count(wr_data_count)); // Bus [4 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
-// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
deleted file mode 100644
index d0f638026..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
+++ /dev/null
@@ -1,82 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version K.39
-# Date: Fri Sep 11 04:33:27 2009
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = True
-SET vhdlsim = False
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 4.3
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_xlnx_16x19_2clk
-CSET data_count=false
-CSET data_count_width=5
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET fifo_implementation=Independent_Clocks_Distributed_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=15
-CSET full_threshold_negate_value=14
-CSET input_data_width=19
-CSET input_depth=16
-CSET output_data_width=19
-CSET output_depth=16
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=5
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=true
-CSET write_data_count_width=5
-# END Parameters
-GENERATE
-# CRC: 60b85dda
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
deleted file mode 100644
index f1a6f7899..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
+++ /dev/null
@@ -1,3 +0,0 @@
-blkmemdp_v6_2
-blk_mem_gen_v2_6
-fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
deleted file mode 100644
index ef33fff67..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ /dev/null
@@ -1,103 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
-<document OS="lin64" product="ISE" version="10.1.03">
-
- <!--The data in this file is primarily intended for consumption by Xilinx tools.
- The structure and the elements are likely to change over the next few releases.
- This means code written to parse this file will need to be revisited each subsequent release.-->
-
- <application stringID="Xst" timeStamp="Thu Sep 10 21:33:06 2009">
- <section stringID="XST_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_RAMS" value="1"></item>
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="32">
- <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
- <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_4BIT_REGISTER" value="11"/>
- <item dataType="int" stringID="XST_5BIT_REGISTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="28">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
- </item>
- </section>
- <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_FSMS" value="1"/>
- <item dataType="int" stringID="XST_RAMS" value="1"></item>
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="107">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="107"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="28">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
- </item>
- </section>
- <section stringID="XST_FINAL_REGISTER_REPORT">
- <item dataType="int" stringID="XST_REGISTERS" value="126">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="126"/>
- </item>
- </section>
- <section stringID="XST_PARTITION_REPORT">
- <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- </section>
- <section stringID="XST_FINAL_REPORT">
- <section stringID="XST_FINAL_RESULTS">
- <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc"/>
- <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
- <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
- <item stringID="XST_KEEP_HIERARCHY" value="no"/>
- </section>
- <section stringID="XST_DESIGN_STATISTICS">
- <item stringID="XST_IOS" value="101"/>
- </section>
- <section stringID="XST_CELL_USAGE">
- <item dataType="int" stringID="XST_BELS" value="66">
- <item dataType="int" stringID="XST_GND" value="1"/>
- <item dataType="int" stringID="XST_INV" value="2"/>
- <item dataType="int" stringID="XST_LUT2" value="18"/>
- <item dataType="int" stringID="XST_LUT2L" value="1"/>
- <item dataType="int" stringID="XST_LUT3" value="8"/>
- <item dataType="int" stringID="XST_LUT4" value="30"/>
- <item dataType="int" stringID="XST_LUT4D" value="3"/>
- <item dataType="int" stringID="XST_LUT4L" value="3"/>
- </item>
- <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="126">
- <item dataType="int" stringID="XST_FD" value="4"/>
- <item dataType="int" stringID="XST_FDC" value="40"/>
- <item dataType="int" stringID="XST_FDCE" value="62"/>
- <item dataType="int" stringID="XST_FDP" value="10"/>
- <item dataType="int" stringID="XST_FDPE" value="5"/>
- </item>
- <item dataType="int" stringID="XST_RAMS" value="19">
- <item dataType="int" stringID="XST_RAM16X1D" value="19"/>
- </item>
- </section>
- </section>
- <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
- <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
- <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="96"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="126"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="103"/>
- <item dataType="int" stringID="XST_NUMBER_USED_AS_LOGIC" value="65"/>
- <item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="38"/>
- <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="101"/>
- <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
- </section>
- <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- <section stringID="XST_ERRORS_STATISTICS">
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="73"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
- </section>
- </application>
-
-</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt
deleted file mode 100644
index 5e1a6ed35..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# Output products list for <fifo_xlnx_16x19_2clk>
-fifo_xlnx_16x19_2clk.ngc
-fifo_xlnx_16x19_2clk.v
-fifo_xlnx_16x19_2clk.veo
-fifo_xlnx_16x19_2clk.xco
-fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-fifo_xlnx_16x19_2clk_flist.txt
-fifo_xlnx_16x19_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt
deleted file mode 100644
index 1b5976555..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-The following files were generated for 'fifo_xlnx_16x19_2clk' in directory
-/home/matt/gnuradio.git/usrp2/fpga/coregen/:
-
-fifo_xlnx_16x19_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_16x19_2clk.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_xlnx_16x19_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_16x19_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
- Please see the core data sheet.
-
-fifo_xlnx_16x19_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-fifo_xlnx_16x19_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_16x19_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
deleted file mode 100644
index 8d633e9c2..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_16x19_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_16x19_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x19_2clk
-}
-# ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x19_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc
deleted file mode 100644
index f42663419..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.4e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v
deleted file mode 100644
index 8a08330d5..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v
+++ /dev/null
@@ -1,165 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating
-// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_xlnx_16x40_2clk(
- din,
- rd_clk,
- rd_en,
- rst,
- wr_clk,
- wr_en,
- dout,
- empty,
- full);
-
-
-input [39 : 0] din;
-input rd_clk;
-input rd_en;
-input rst;
-input wr_clk;
-input wr_en;
-output [39 : 0] dout;
-output empty;
-output full;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V4_3 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(4),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(40),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(40),
- .C_ENABLE_RLOCS(0),
- .C_FAMILY("spartan3"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(0),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(0),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(2),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("512x72"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(15),
- .C_PROG_FULL_THRESH_NEGATE_VAL(14),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(4),
- .C_RD_DEPTH(16),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(4),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(0),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(4),
- .C_WR_DEPTH(16),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(4),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .DIN(din),
- .RD_CLK(rd_clk),
- .RD_EN(rd_en),
- .RST(rst),
- .WR_CLK(wr_clk),
- .WR_EN(wr_en),
- .DOUT(dout),
- .EMPTY(empty),
- .FULL(full),
- .CLK(),
- .INT_CLK(),
- .BACKUP(),
- .BACKUP_MARKER(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .RD_RST(),
- .SRST(),
- .WR_RST(),
- .ALMOST_EMPTY(),
- .ALMOST_FULL(),
- .DATA_COUNT(),
- .OVERFLOW(),
- .PROG_EMPTY(),
- .PROG_FULL(),
- .VALID(),
- .RD_DATA_COUNT(),
- .UNDERFLOW(),
- .WR_ACK(),
- .WR_DATA_COUNT(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo
deleted file mode 100644
index 684078e58..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo
+++ /dev/null
@@ -1,51 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_16x40_2clk YourInstanceName (
- .din(din), // Bus [39 : 0]
- .rd_clk(rd_clk),
- .rd_en(rd_en),
- .rst(rst),
- .wr_clk(wr_clk),
- .wr_en(wr_en),
- .dout(dout), // Bus [39 : 0]
- .empty(empty),
- .full(full));
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating
-// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco
deleted file mode 100644
index d0da5a6e8..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco
+++ /dev/null
@@ -1,82 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version K.39
-# Date: Tue May 11 20:27:53 2010
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = True
-SET vhdlsim = False
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 4.3
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_xlnx_16x40_2clk
-CSET data_count=false
-CSET data_count_width=4
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET fifo_implementation=Independent_Clocks_Distributed_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=15
-CSET full_threshold_negate_value=14
-CSET input_data_width=40
-CSET input_depth=16
-CSET output_data_width=40
-CSET output_depth=16
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=4
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=4
-# END Parameters
-GENERATE
-# CRC: 6bcb05e1
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
deleted file mode 100644
index 544bda31d..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ /dev/null
@@ -1,98 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
-<document OS="lin64" product="ISE" version="10.1.03">
-
- <!--The data in this file is primarily intended for consumption by Xilinx tools.
- The structure and the elements are likely to change over the next few releases.
- This means code written to parse this file will need to be revisited each subsequent release.-->
-
- <application stringID="Xst" timeStamp="Tue May 11 13:27:35 2010">
- <section stringID="XST_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_RAMS" value="1"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="30">
- <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
- <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_4BIT_REGISTER" value="11"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="28">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
- </item>
- </section>
- <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_FSMS" value="1"/>
- <item dataType="int" stringID="XST_RAMS" value="1"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="144">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="144"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="28">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
- </item>
- </section>
- <section stringID="XST_FINAL_REGISTER_REPORT">
- <item dataType="int" stringID="XST_REGISTERS" value="150">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="150"/>
- </item>
- </section>
- <section stringID="XST_PARTITION_REPORT">
- <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- </section>
- <section stringID="XST_FINAL_REPORT">
- <section stringID="XST_FINAL_RESULTS">
- <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc"/>
- <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
- <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
- <item stringID="XST_KEEP_HIERARCHY" value="no"/>
- </section>
- <section stringID="XST_DESIGN_STATISTICS">
- <item stringID="XST_IOS" value="140"/>
- </section>
- <section stringID="XST_CELL_USAGE">
- <item dataType="int" stringID="XST_BELS" value="42">
- <item dataType="int" stringID="XST_GND" value="1"/>
- <item dataType="int" stringID="XST_INV" value="2"/>
- <item dataType="int" stringID="XST_LUT2" value="14"/>
- <item dataType="int" stringID="XST_LUT3" value="7"/>
- <item dataType="int" stringID="XST_LUT4" value="16"/>
- <item dataType="int" stringID="XST_LUT4L" value="2"/>
- </item>
- <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="150">
- <item dataType="int" stringID="XST_FD" value="4"/>
- <item dataType="int" stringID="XST_FDC" value="34"/>
- <item dataType="int" stringID="XST_FDCE" value="97"/>
- <item dataType="int" stringID="XST_FDP" value="10"/>
- <item dataType="int" stringID="XST_FDPE" value="5"/>
- </item>
- <item dataType="int" stringID="XST_RAMS" value="40">
- <item dataType="int" stringID="XST_RAM16X1D" value="40"/>
- </item>
- </section>
- </section>
- <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
- <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
- <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="127"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="150"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="121"/>
- <item dataType="int" stringID="XST_NUMBER_USED_AS_LOGIC" value="41"/>
- <item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="80"/>
- <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="140"/>
- <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
- </section>
- <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- <section stringID="XST_ERRORS_STATISTICS">
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="74"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="9"/>
- </section>
- </application>
-
-</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt
deleted file mode 100644
index c38f4e991..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# Output products list for <fifo_xlnx_16x40_2clk>
-fifo_xlnx_16x40_2clk.ngc
-fifo_xlnx_16x40_2clk.v
-fifo_xlnx_16x40_2clk.veo
-fifo_xlnx_16x40_2clk.xco
-fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-fifo_xlnx_16x40_2clk_flist.txt
-fifo_xlnx_16x40_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt
deleted file mode 100644
index bbcd4af79..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-The following files were generated for 'fifo_xlnx_16x40_2clk' in directory
-/home/matt/sourcerepo/fpga/usrp2/coregen/:
-
-fifo_xlnx_16x40_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_16x40_2clk.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_xlnx_16x40_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_16x40_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
- Please see the core data sheet.
-
-fifo_xlnx_16x40_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-fifo_xlnx_16x40_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_16x40_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl
deleted file mode 100644
index 2b4824831..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_16x40_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_16x40_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x40_2clk
-}
-# ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x40_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy
deleted file mode 100644
index a87aa2f84..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy
+++ /dev/null
@@ -1,49 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 fifo_xlnx_2Kx36_2clk
-RECTANGLE Normal 32 32 544 672
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName wr_clk
-PINATTR Polarity IN
-LINE Normal 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName rd_clk
-PINATTR Polarity IN
-LINE Normal 144 704 144 672
-PIN 144 704 BOTTOM 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 576 80 544 80
-PIN 576 80 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 576 208 544 208
-PIN 576 208 RIGHT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Wide 576 368 544 368
-PIN 576 368 RIGHT 36
-PINATTR PinName wr_data_count[11:0]
-PINATTR Polarity OUT
-LINE Normal 576 432 544 432
-PIN 576 432 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-LINE Wide 576 592 544 592
-PIN 576 592 RIGHT 36
-PINATTR PinName rd_data_count[11:0]
-PINATTR Polarity OUT
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc
deleted file mode 100644
index 684eb74f4..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym
deleted file mode 100644
index 5d56b5c98..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym
+++ /dev/null
@@ -1,74 +0,0 @@
-VERSION 5
-BEGIN SYMBOL fifo_xlnx_2Kx36_2clk
-SYMBOLTYPE BLOCK
-TIMESTAMP 2009 9 3 17 25 13
-SYMPIN 0 80 Input din[35:0]
-SYMPIN 0 144 Input wr_en
-SYMPIN 0 176 Input wr_clk
-SYMPIN 0 240 Input rd_en
-SYMPIN 0 272 Input rd_clk
-SYMPIN 144 704 Input rst
-SYMPIN 576 80 Output dout[35:0]
-SYMPIN 576 208 Output full
-SYMPIN 576 368 Output wr_data_count[11:0]
-SYMPIN 576 432 Output empty
-SYMPIN 576 592 Output rd_data_count[11:0]
-BEGIN DISPLAY 32 32 TEXT fifo_xlnx_2Kx36_2clk
- FONT 40 "Arial"
-END DISPLAY
-RECTANGLE N 32 32 544 672
-BEGIN LINE W 0 80 32 80
-END LINE
-BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 0 144 32 144
-BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 0 176 32 176
-BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 0 240 32 240
-BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 0 272 32 272
-BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 144 704 144 672
-BEGIN DISPLAY 144 668 PIN rst ATTR PinName
- ALIGNMENT BCENTER
- FONT 24 "Arial"
-END DISPLAY
-BEGIN LINE W 576 80 544 80
-END LINE
-BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-LINE N 576 208 544 208
-BEGIN DISPLAY 540 208 PIN full ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-BEGIN LINE W 576 368 544 368
-END LINE
-BEGIN DISPLAY 540 368 PIN wr_data_count[11:0] ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-LINE N 576 432 544 432
-BEGIN DISPLAY 540 432 PIN empty ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-BEGIN LINE W 576 592 544 592
-END LINE
-BEGIN DISPLAY 540 592 PIN rd_data_count[11:0] ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-END SYMBOL
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
deleted file mode 100644
index 0762b3ae9..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
+++ /dev/null
@@ -1,173 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating
-// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_xlnx_2Kx36_2clk(
- din,
- rd_clk,
- rd_en,
- rst,
- wr_clk,
- wr_en,
- dout,
- empty,
- full,
- rd_data_count,
- wr_data_count);
-
-
-input [35 : 0] din;
-input rd_clk;
-input rd_en;
-input rst;
-input wr_clk;
-input wr_en;
-output [35 : 0] dout;
-output empty;
-output full;
-output [11 : 0] rd_data_count;
-output [11 : 0] wr_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V4_3 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(12),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(36),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(36),
- .C_ENABLE_RLOCS(0),
- .C_FAMILY("spartan3"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(1),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("2kx18"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(2047),
- .C_PROG_FULL_THRESH_NEGATE_VAL(2046),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(12),
- .C_RD_DEPTH(2048),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(11),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(1),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(12),
- .C_WR_DEPTH(2048),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(11),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .DIN(din),
- .RD_CLK(rd_clk),
- .RD_EN(rd_en),
- .RST(rst),
- .WR_CLK(wr_clk),
- .WR_EN(wr_en),
- .DOUT(dout),
- .EMPTY(empty),
- .FULL(full),
- .RD_DATA_COUNT(rd_data_count),
- .WR_DATA_COUNT(wr_data_count),
- .CLK(),
- .INT_CLK(),
- .BACKUP(),
- .BACKUP_MARKER(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .RD_RST(),
- .SRST(),
- .WR_RST(),
- .ALMOST_EMPTY(),
- .ALMOST_FULL(),
- .DATA_COUNT(),
- .OVERFLOW(),
- .PROG_EMPTY(),
- .PROG_FULL(),
- .VALID(),
- .UNDERFLOW(),
- .WR_ACK(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-// XST black box declaration
-// box_type "black_box"
-// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box"
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo
deleted file mode 100644
index af9191555..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_2Kx36_2clk YourInstanceName (
- .din(din), // Bus [35 : 0]
- .rd_clk(rd_clk),
- .rd_en(rd_en),
- .rst(rst),
- .wr_clk(wr_clk),
- .wr_en(wr_en),
- .dout(dout), // Bus [35 : 0]
- .empty(empty),
- .full(full),
- .rd_data_count(rd_data_count), // Bus [11 : 0]
- .wr_data_count(wr_data_count)); // Bus [11 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating
-// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd
deleted file mode 100644
index 53033dc97..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd
+++ /dev/null
@@ -1,156 +0,0 @@
---------------------------------------------------------------------------------
--- This file is owned and controlled by Xilinx and must be used --
--- solely for design, simulation, implementation and creation of --
--- design files limited to Xilinx devices or technologies. Use --
--- with non-Xilinx devices or technologies is expressly prohibited --
--- and immediately terminates your license. --
--- --
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
--- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
--- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
--- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
--- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
--- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
--- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
--- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
--- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
--- FOR A PARTICULAR PURPOSE. --
--- --
--- Xilinx products are not intended for use in life support --
--- appliances, devices, or systems. Use in such applications are --
--- expressly prohibited. --
--- --
--- (c) Copyright 1995-2007 Xilinx, Inc. --
--- All rights reserved. --
---------------------------------------------------------------------------------
--- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating
--- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY fifo_xlnx_2Kx36_2clk IS
- port (
- din: IN std_logic_VECTOR(35 downto 0);
- rd_clk: IN std_logic;
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_clk: IN std_logic;
- wr_en: IN std_logic;
- dout: OUT std_logic_VECTOR(35 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- rd_data_count: OUT std_logic_VECTOR(11 downto 0);
- wr_data_count: OUT std_logic_VECTOR(11 downto 0));
-END fifo_xlnx_2Kx36_2clk;
-
-ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS
--- synthesis translate_off
-component wrapped_fifo_xlnx_2Kx36_2clk
- port (
- din: IN std_logic_VECTOR(35 downto 0);
- rd_clk: IN std_logic;
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_clk: IN std_logic;
- wr_en: IN std_logic;
- dout: OUT std_logic_VECTOR(35 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- rd_data_count: OUT std_logic_VECTOR(11 downto 0);
- wr_data_count: OUT std_logic_VECTOR(11 downto 0));
-end component;
-
--- Configuration specification
- for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
- generic map(
- c_has_int_clk => 0,
- c_rd_freq => 1,
- c_wr_response_latency => 1,
- c_has_srst => 0,
- c_has_rd_data_count => 1,
- c_din_width => 36,
- c_has_wr_data_count => 1,
- c_full_flags_rst_val => 1,
- c_implementation_type => 2,
- c_family => "spartan3",
- c_use_embedded_reg => 0,
- c_has_wr_rst => 0,
- c_wr_freq => 1,
- c_use_dout_rst => 1,
- c_underflow_low => 0,
- c_has_meminit_file => 0,
- c_has_overflow => 0,
- c_preload_latency => 0,
- c_dout_width => 36,
- c_msgon_val => 1,
- c_rd_depth => 2048,
- c_default_value => "BlankString",
- c_mif_file_name => "BlankString",
- c_has_underflow => 0,
- c_has_rd_rst => 0,
- c_has_almost_full => 0,
- c_has_rst => 1,
- c_data_count_width => 12,
- c_has_wr_ack => 0,
- c_use_ecc => 0,
- c_wr_ack_low => 0,
- c_common_clock => 0,
- c_rd_pntr_width => 11,
- c_use_fwft_data_count => 1,
- c_has_almost_empty => 0,
- c_rd_data_count_width => 12,
- c_enable_rlocs => 0,
- c_wr_pntr_width => 11,
- c_overflow_low => 0,
- c_prog_empty_type => 0,
- c_optimization_mode => 0,
- c_wr_data_count_width => 12,
- c_preload_regs => 1,
- c_dout_rst_val => "0",
- c_has_data_count => 0,
- c_prog_full_thresh_negate_val => 2046,
- c_wr_depth => 2048,
- c_prog_empty_thresh_negate_val => 5,
- c_prog_empty_thresh_assert_val => 4,
- c_has_valid => 0,
- c_init_wr_pntr_val => 0,
- c_prog_full_thresh_assert_val => 2047,
- c_use_fifo16_flags => 0,
- c_has_backup => 0,
- c_valid_low => 0,
- c_prim_fifo_type => "2kx18",
- c_count_type => 0,
- c_prog_full_type => 0,
- c_memory_type => 1);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_fifo_xlnx_2Kx36_2clk
- port map (
- din => din,
- rd_clk => rd_clk,
- rd_en => rd_en,
- rst => rst,
- wr_clk => wr_clk,
- wr_en => wr_en,
- dout => dout,
- empty => empty,
- full => full,
- rd_data_count => rd_data_count,
- wr_data_count => wr_data_count);
--- synthesis translate_on
-
-END fifo_xlnx_2Kx36_2clk_a;
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho
deleted file mode 100644
index 5165b0bc4..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho
+++ /dev/null
@@ -1,76 +0,0 @@
---------------------------------------------------------------------------------
--- This file is owned and controlled by Xilinx and must be used --
--- solely for design, simulation, implementation and creation of --
--- design files limited to Xilinx devices or technologies. Use --
--- with non-Xilinx devices or technologies is expressly prohibited --
--- and immediately terminates your license. --
--- --
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
--- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
--- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
--- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
--- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
--- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
--- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
--- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
--- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
--- FOR A PARTICULAR PURPOSE. --
--- --
--- Xilinx products are not intended for use in life support --
--- appliances, devices, or systems. Use in such applications are --
--- expressly prohibited. --
--- --
--- (c) Copyright 1995-2007 Xilinx, Inc. --
--- All rights reserved. --
---------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component fifo_xlnx_2Kx36_2clk
- port (
- din: IN std_logic_VECTOR(35 downto 0);
- rd_clk: IN std_logic;
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_clk: IN std_logic;
- wr_en: IN std_logic;
- dout: OUT std_logic_VECTOR(35 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- rd_data_count: OUT std_logic_VECTOR(11 downto 0);
- wr_data_count: OUT std_logic_VECTOR(11 downto 0));
-end component;
-
--- Synplicity black box declaration
-attribute syn_black_box : boolean;
-attribute syn_black_box of fifo_xlnx_2Kx36_2clk: component is true;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : fifo_xlnx_2Kx36_2clk
- port map (
- din => din,
- rd_clk => rd_clk,
- rd_en => rd_en,
- rst => rst,
- wr_clk => wr_clk,
- wr_en => wr_en,
- dout => dout,
- empty => empty,
- full => full,
- rd_data_count => rd_data_count,
- wr_data_count => wr_data_count);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating
--- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
deleted file mode 100644
index e25ad38da..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
+++ /dev/null
@@ -1,82 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version K.39
-# Date: Thu Sep 3 17:25:43 2009
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = True
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = VHDL
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Foundation_iSE
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = True
-SET vhdlsim = True
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 4.3
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_xlnx_2Kx36_2clk
-CSET data_count=false
-CSET data_count_width=12
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=2047
-CSET full_threshold_negate_value=2046
-CSET input_data_width=36
-CSET input_depth=2048
-CSET output_data_width=36
-CSET output_depth=2048
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=12
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=true
-CSET write_data_count_width=12
-# END Parameters
-GENERATE
-# CRC: 2ae9f6ef
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
deleted file mode 100644
index f1a6f7899..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
+++ /dev/null
@@ -1,3 +0,0 @@
-blkmemdp_v6_2
-blk_mem_gen_v2_6
-fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
deleted file mode 100644
index 5108be2c5..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ /dev/null
@@ -1,106 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
-<document OS="lin64" product="ISE" version="10.1.03">
-
- <!--The data in this file is primarily intended for consumption by Xilinx tools.
- The structure and the elements are likely to change over the next few releases.
- This means code written to parse this file will need to be revisited each subsequent release.-->
-
- <application stringID="Xst" timeStamp="Thu Sep 3 10:25:17 2009">
- <section stringID="XST_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_11BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="31">
- <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
- <item dataType="int" stringID="XST_11BIT_REGISTER" value="11"/>
- <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_36BIT_REGISTER" value="1"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="91">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="90"/>
- <item dataType="int" stringID="XST_1BIT_XOR6" value="1"/>
- </item>
- </section>
- <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_FSMS" value="1"/>
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_11BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="189">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="189"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="91">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="90"/>
- <item dataType="int" stringID="XST_1BIT_XOR6" value="1"/>
- </item>
- </section>
- <section stringID="XST_FINAL_REGISTER_REPORT">
- <item dataType="int" stringID="XST_REGISTERS" value="222">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="222"/>
- </item>
- </section>
- <section stringID="XST_PARTITION_REPORT">
- <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- </section>
- <section stringID="XST_FINAL_REPORT">
- <section stringID="XST_FINAL_RESULTS">
- <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc"/>
- <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
- <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
- <item stringID="XST_KEEP_HIERARCHY" value="no"/>
- </section>
- <section stringID="XST_DESIGN_STATISTICS">
- <item stringID="XST_IOS" value="198"/>
- </section>
- <section stringID="XST_CELL_USAGE">
- <item dataType="int" stringID="XST_BELS" value="283">
- <item dataType="int" stringID="XST_GND" value="1"/>
- <item dataType="int" stringID="XST_INV" value="1"/>
- <item dataType="int" stringID="XST_LUT1" value="22"/>
- <item dataType="int" stringID="XST_LUT2" value="63"/>
- <item dataType="int" stringID="XST_LUT3" value="19"/>
- <item dataType="int" stringID="XST_LUT3D" value="1"/>
- <item dataType="int" stringID="XST_LUT3L" value="3"/>
- <item dataType="int" stringID="XST_LUT4" value="62"/>
- <item dataType="int" stringID="XST_LUT4D" value="2"/>
- <item dataType="int" stringID="XST_MUXCY" value="64"/>
- <item dataType="int" stringID="XST_VCC" value="1"/>
- <item dataType="int" stringID="XST_XORCY" value="44"/>
- </item>
- <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="222">
- <item dataType="int" stringID="XST_FD" value="4"/>
- <item dataType="int" stringID="XST_FDC" value="103"/>
- <item dataType="int" stringID="XST_FDCE" value="88"/>
- <item dataType="int" stringID="XST_FDP" value="10"/>
- <item dataType="int" stringID="XST_FDPE" value="5"/>
- </item>
- <item dataType="int" stringID="XST_RAMS" value="4">
- <item dataType="int" stringID="XST_RAMB16S9S9" value="4"/>
- </item>
- </section>
- </section>
- <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
- <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
- <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="162"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="222"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="173"/>
- <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="198"/>
- <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
- <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="4"/>
- </section>
- <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- <section stringID="XST_ERRORS_STATISTICS">
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="196"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="29"/>
- </section>
- </application>
-
-</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
deleted file mode 100644
index 670d84713..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-# Output products list for <fifo_xlnx_2Kx36_2clk>
-fifo_xlnx_2Kx36_2clk.asy
-fifo_xlnx_2Kx36_2clk.ngc
-fifo_xlnx_2Kx36_2clk.sym
-fifo_xlnx_2Kx36_2clk.v
-fifo_xlnx_2Kx36_2clk.veo
-fifo_xlnx_2Kx36_2clk.vhd
-fifo_xlnx_2Kx36_2clk.vho
-fifo_xlnx_2Kx36_2clk.xco
-fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-fifo_xlnx_2Kx36_2clk_flist.txt
-fifo_xlnx_2Kx36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
deleted file mode 100644
index 1879503a9..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory
-/home/matt/gnuradio.git/usrp2/fpga/coregen/:
-
-fifo_xlnx_2Kx36_2clk.asy:
- Graphical symbol information file. Used by the ISE tools and some
- third party tools to create a symbol representing the core.
-
-fifo_xlnx_2Kx36_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_2Kx36_2clk.sym:
- Please see the core data sheet.
-
-fifo_xlnx_2Kx36_2clk.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_xlnx_2Kx36_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_2Kx36_2clk.vhd:
- VHDL wrapper file provided to support functional simulation. This
- file contains simulation model customization data that is passed to
- a parameterized simulation model for the core.
-
-fifo_xlnx_2Kx36_2clk.vho:
- VHO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a VHDL design.
-
-fifo_xlnx_2Kx36_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
- Please see the core data sheet.
-
-fifo_xlnx_2Kx36_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-fifo_xlnx_2Kx36_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_2Kx36_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
deleted file mode 100644
index cac25efd2..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
+++ /dev/null
@@ -1,84 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_2Kx36_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_2Kx36_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_2Kx36_2clk
-}
-# ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.sym
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vho
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_2Kx36_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
deleted file mode 100644
index 70ee54054..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
+++ /dev/null
@@ -1,30 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_32x36_2clk.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_32x36_2clk.veo" xil_pn:origination="imported"/>
- </files>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
deleted file mode 100644
index e69de29bb..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
+++ /dev/null
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
deleted file mode 100644
index d1ed419a7..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
deleted file mode 100644
index 68a8caaf6..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
+++ /dev/null
@@ -1,3839 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
-////////////////////////////////////////////////////////////////////////////////
-// ____ ____
-// / /\/ /
-// /___/ \ / Vendor: Xilinx
-// \ \ \/ Version: M.63c
-// \ \ Application: netgen
-// / / Filename: fifo_xlnx_32x36_2clk.v
-// /___/ /\ Timestamp: Fri Oct 15 00:50:08 2010
-// \ \ / \
-// \___\/\___\
-//
-// Command : -intstyle ise -w -sim -ofmt verilog /tmp/_cg/fifo_xlnx_32x36_2clk.ngc /tmp/_cg/fifo_xlnx_32x36_2clk.v
-// Device : 3s2000fg456-5
-// Input file : /tmp/_cg/fifo_xlnx_32x36_2clk.ngc
-// Output file : /tmp/_cg/fifo_xlnx_32x36_2clk.v
-// # of Modules : 1
-// Design Name : fifo_xlnx_32x36_2clk
-// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/
-//
-// Purpose:
-// This verilog netlist is a verification model and uses simulation
-// primitives which may not represent the true implementation of the
-// device, however the netlist is functionally correct and should not
-// be modified. This file cannot be synthesized and should only be used
-// with supported simulation tools.
-//
-// Reference:
-// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
-//
-////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1 ns/1 ps
-
-module fifo_xlnx_32x36_2clk (
- rd_en, almost_full, prog_full, wr_en, full, empty, wr_clk, rst, rd_clk, dout, din
-)/* synthesis syn_black_box syn_noprune=1 */;
- input rd_en;
- output almost_full;
- output prog_full;
- input wr_en;
- output full;
- output empty;
- input wr_clk;
- input rst;
- input rd_clk;
- output [35 : 0] dout;
- input [35 : 0] din;
-
- // synthesis translate_off
-
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/N11 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/N11 ;
- wire \BU2/N16 ;
- wire \BU2/N14 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ;
- wire \BU2/U0/grf.rf/mem/dout_i_not0001 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N147 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N145 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N143 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N141 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N137 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N135 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N139 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N133 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N131 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N129 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N127 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N123 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N121 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N125 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N119 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N117 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N115 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N113 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N109 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N107 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N111 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N103 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N101 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N105 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N97 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N95 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N99 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N93 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N91 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N89 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N87 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N83 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N81 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N85 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N79 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N77 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N75 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N73 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N69 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N67 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N71 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N65 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N63 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N61 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N59 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N55 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N53 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N57 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N51 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N49 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N47 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N45 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N41 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N39 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N43 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N37 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N35 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N33 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N31 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N27 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N25 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N29 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N23 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N21 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N19 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N17 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N13 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N11 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N15 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N9 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N7 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/N5 ;
- wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ;
- wire \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ;
- wire \BU2/U0/grf.rf/rstblk/wr_rst_comb ;
- wire \BU2/U0/grf.rf/rstblk/rd_rst_comb ;
- wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ;
- wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ;
- wire \BU2/U0/grf.rf/rstblk/rst_d1_93 ;
- wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ;
- wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ;
- wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ;
- wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ;
- wire \BU2/U0/grf.rf/rstblk/rst_d2_88 ;
- wire \BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ;
- wire \BU2/U0/grf.rf/rstblk/rst_d3_86 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ;
- wire \BU2/N1 ;
- wire NLW_VCC_P_UNCONNECTED;
- wire NLW_GND_G_UNCONNECTED;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ;
- wire [35 : 0] din_2;
- wire [35 : 0] dout_3;
- wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/dout_i ;
- wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count ;
- wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad ;
- wire [5 : 1] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy ;
- wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 ;
- wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state ;
- wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count ;
- wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc ;
- wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc ;
- wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 ;
- wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg ;
- wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 ;
- wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg ;
- wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin ;
- wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin ;
- wire [1 : 0] \BU2/U0/grf.rf/rstblk/wr_rst_reg ;
- wire [2 : 0] \BU2/U0/grf.rf/rstblk/rd_rst_reg ;
- wire [0 : 0] \BU2/rd_data_count ;
- assign
- dout[35] = dout_3[35],
- dout[34] = dout_3[34],
- dout[33] = dout_3[33],
- dout[32] = dout_3[32],
- dout[31] = dout_3[31],
- dout[30] = dout_3[30],
- dout[29] = dout_3[29],
- dout[28] = dout_3[28],
- dout[27] = dout_3[27],
- dout[26] = dout_3[26],
- dout[25] = dout_3[25],
- dout[24] = dout_3[24],
- dout[23] = dout_3[23],
- dout[22] = dout_3[22],
- dout[21] = dout_3[21],
- dout[20] = dout_3[20],
- dout[19] = dout_3[19],
- dout[18] = dout_3[18],
- dout[17] = dout_3[17],
- dout[16] = dout_3[16],
- dout[15] = dout_3[15],
- dout[14] = dout_3[14],
- dout[13] = dout_3[13],
- dout[12] = dout_3[12],
- dout[11] = dout_3[11],
- dout[10] = dout_3[10],
- dout[9] = dout_3[9],
- dout[8] = dout_3[8],
- dout[7] = dout_3[7],
- dout[6] = dout_3[6],
- dout[5] = dout_3[5],
- dout[4] = dout_3[4],
- dout[3] = dout_3[3],
- dout[2] = dout_3[2],
- dout[1] = dout_3[1],
- dout[0] = dout_3[0],
- din_2[35] = din[35],
- din_2[34] = din[34],
- din_2[33] = din[33],
- din_2[32] = din[32],
- din_2[31] = din[31],
- din_2[30] = din[30],
- din_2[29] = din[29],
- din_2[28] = din[28],
- din_2[27] = din[27],
- din_2[26] = din[26],
- din_2[25] = din[25],
- din_2[24] = din[24],
- din_2[23] = din[23],
- din_2[22] = din[22],
- din_2[21] = din[21],
- din_2[20] = din[20],
- din_2[19] = din[19],
- din_2[18] = din[18],
- din_2[17] = din[17],
- din_2[16] = din[16],
- din_2[15] = din[15],
- din_2[14] = din[14],
- din_2[13] = din[13],
- din_2[12] = din[12],
- din_2[11] = din[11],
- din_2[10] = din[10],
- din_2[9] = din[9],
- din_2[8] = din[8],
- din_2[7] = din[7],
- din_2[6] = din[6],
- din_2[5] = din[5],
- din_2[4] = din[4],
- din_2[3] = din[3],
- din_2[2] = din[2],
- din_2[1] = din[1],
- din_2[0] = din[0];
- VCC VCC_0 (
- .P(NLW_VCC_P_UNCONNECTED)
- );
- GND GND_1 (
- .G(NLW_GND_G_UNCONNECTED)
- );
- LUT3_L #(
- .INIT ( 8'h90 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ),
- .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 )
- );
- LUT4_L #(
- .INIT ( 16'h9000 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ),
- .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ),
- .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 )
- );
- LUT4_L #(
- .INIT ( 16'h9000 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ),
- .I3(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 )
- );
- LUT4_L #(
- .INIT ( 16'h8421 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
- .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 )
- );
- LUT4_L #(
- .INIT ( 16'h8241 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
- .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 )
- );
- LUT3_L #(
- .INIT ( 8'h7F ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>111 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
- .LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 )
- );
- LUT3_L #(
- .INIT ( 8'h7F ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
- .LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 )
- );
- LUT2_L #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
- .LO(\BU2/N16 )
- );
- LUT2_L #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
- .LO(\BU2/N14 )
- );
- INV \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0 (
- .I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count )
- );
- INV \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0 (
- .I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count )
- );
- LUT2 #(
- .INIT ( 4'h2 ))
- \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1 (
- .I0(wr_en),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
- .O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 )
- );
- LUT4 #(
- .INIT ( 16'h2333 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1 (
- .I0(rd_en),
- .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 )
- );
- LUT4 #(
- .INIT ( 16'h6AAA ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 )
- );
- LUT4 #(
- .INIT ( 16'h6AAA ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 )
- );
- LUT3 #(
- .INIT ( 8'h08 ))
- \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1 (
- .I0(wr_en),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 )
- );
- LUT3 #(
- .INIT ( 8'h10 ))
- \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
- .I2(wr_en),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 )
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5])
- );
- LUT4 #(
- .INIT ( 16'h9000 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ),
- .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 )
- );
- LUT4 #(
- .INIT ( 16'h9000 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ),
- .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 )
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1])
- );
- LUT4 #(
- .INIT ( 16'h5450 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105 (
- .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ),
- .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 )
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
- .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 )
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
- .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 )
- );
- LUT4 #(
- .INIT ( 16'h8421 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 )
- );
- LUT4 #(
- .INIT ( 16'h5450 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107 (
- .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
- .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 )
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
- .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 )
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
- .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 )
- );
- LUT2 #(
- .INIT ( 4'h2 ))
- \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 (
- .I0(wr_en),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 )
- );
- LUT4 #(
- .INIT ( 16'hECA0 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ),
- .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 )
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 )
- );
- LUT4 #(
- .INIT ( 16'h8421 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 )
- );
- LUT4 #(
- .INIT ( 16'h8241 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 )
- );
- LUT4 #(
- .INIT ( 16'h2333 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21 (
- .I0(rd_en),
- .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 )
- );
- LUT3 #(
- .INIT ( 8'hA6 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 )
- );
- LUT3 #(
- .INIT ( 8'hA6 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 )
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8])
- );
- LUT3 #(
- .INIT ( 8'hE4 ))
- \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ),
- .I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ),
- .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9])
- );
- LUT4 #(
- .INIT ( 16'h6996 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
- .I3(\BU2/N16 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 )
- );
- LUT4 #(
- .INIT ( 16'h6996 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
- .I3(\BU2/N14 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 )
- );
- LUT3 #(
- .INIT ( 8'hA2 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
- .I2(rd_en),
- .O(\BU2/U0/grf.rf/mem/dout_i_not0001 )
- );
- LUT2 #(
- .INIT ( 4'hD ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
- .I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 )
- );
- LUT4 #(
- .INIT ( 16'h8E8A ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
- .I3(rd_en),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 )
- );
- LUT4 #(
- .INIT ( 16'h6996 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 )
- );
- LUT4 #(
- .INIT ( 16'h6996 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 )
- );
- LUT4 #(
- .INIT ( 16'h40FF ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1 (
- .I0(rd_en),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
- .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0])
- );
- LUT3 #(
- .INIT ( 8'h6A ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 )
- );
- LUT3 #(
- .INIT ( 8'h6A ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 )
- );
- LUT3 #(
- .INIT ( 8'h96 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 )
- );
- LUT3 #(
- .INIT ( 8'h96 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 )
- );
- LUT3 #(
- .INIT ( 8'hF2 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
- .I1(rd_en),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1])
- );
- LUT3 #(
- .INIT ( 8'h08 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]),
- .I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 )
- );
- LUT2 #(
- .INIT ( 4'h4 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_comb1 (
- .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ),
- .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
- .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb )
- );
- LUT2 #(
- .INIT ( 4'h4 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_comb1 (
- .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ),
- .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
- .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb )
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
- .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
- .Q(almost_full)
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
- .Q(full)
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 )
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_0 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]),
- .Q(dout_3[0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_1 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]),
- .Q(dout_3[1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_2 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]),
- .Q(dout_3[2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_3 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]),
- .Q(dout_3[3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_4 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]),
- .Q(dout_3[4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_5 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]),
- .Q(dout_3[5])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_6 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]),
- .Q(dout_3[6])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_7 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]),
- .Q(dout_3[7])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_8 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]),
- .Q(dout_3[8])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_9 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]),
- .Q(dout_3[9])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_10 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]),
- .Q(dout_3[10])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_11 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]),
- .Q(dout_3[11])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_12 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]),
- .Q(dout_3[12])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_13 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]),
- .Q(dout_3[13])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_14 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]),
- .Q(dout_3[14])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_15 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]),
- .Q(dout_3[15])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_16 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]),
- .Q(dout_3[16])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_17 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]),
- .Q(dout_3[17])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_18 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]),
- .Q(dout_3[18])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_19 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]),
- .Q(dout_3[19])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_20 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]),
- .Q(dout_3[20])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_21 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]),
- .Q(dout_3[21])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_22 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]),
- .Q(dout_3[22])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_23 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]),
- .Q(dout_3[23])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_24 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]),
- .Q(dout_3[24])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_25 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]),
- .Q(dout_3[25])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_26 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]),
- .Q(dout_3[26])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_27 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]),
- .Q(dout_3[27])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_28 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]),
- .Q(dout_3[28])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_29 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]),
- .Q(dout_3[29])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_30 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]),
- .Q(dout_3[30])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_31 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]),
- .Q(dout_3[31])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_32 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]),
- .Q(dout_3[32])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_33 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]),
- .Q(dout_3[33])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_34 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]),
- .Q(dout_3[34])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_35 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]),
- .Q(dout_3[35])
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[35]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[35]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[34]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[34]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[33]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[32]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[33]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[32]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[31]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[31]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[30]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[29]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[29]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[30]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[28]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[28]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[27]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[27]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[26]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[25]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[26]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[24]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[24]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[25]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[23]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[22]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[23]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[22]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[21]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[21]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[20]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[19]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[19]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[20]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[18]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[18]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[17]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[17]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[16]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[15]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[16]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[15]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[14]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[14]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[13]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[12]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[12]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[13]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[11]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[11]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[10]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[10]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[9]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[8]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[9]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[8]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[7]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[7]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[6]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[5]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[5]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[6]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[4]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[4]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[3]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[3]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[2]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[1]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[2]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[1]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[0]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 )
- );
- RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1 (
- .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
- .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
- .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
- .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
- .D(din_2[0]),
- .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .WCLK(wr_clk),
- .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
- .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ),
- .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 )
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_35 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_34 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_33 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_32 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_31 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_30 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_29 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_28 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_27 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_26 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_25 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_24 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_22 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_21 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_20 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_19 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_18 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_17 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_16 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_15 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_14 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_12 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_11 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_9 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_8 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_7 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_5 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_4 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_3 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_2 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_1 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/gdm.dm/dout_i_0 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]),
- .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
- .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
- .Q(prog_full)
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]),
- .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]),
- .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0> (
- .CI(\BU2/N1 ),
- .DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
- .S(\BU2/rd_data_count [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]),
- .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]),
- .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .Q(empty)
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 )
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 (
- .C(wr_clk),
- .D(\BU2/rd_data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 (
- .C(wr_clk),
- .D(\BU2/rd_data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 (
- .C(rd_clk),
- .D(\BU2/rd_data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 (
- .C(rd_clk),
- .D(\BU2/rd_data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 (
- .C(rd_clk),
- .D(\BU2/rd_data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/rstblk/rst_d1 (
- .C(wr_clk),
- .D(\BU2/rd_data_count [0]),
- .PRE(rst),
- .Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 )
- );
- FDPE \BU2/U0/grf.rf/rstblk/rd_rst_asreg (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
- .D(\BU2/rd_data_count [0]),
- .PRE(rst),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 )
- );
- FD #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 )
- );
- FDPE \BU2/U0/grf.rf/rstblk/wr_rst_asreg (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
- .D(\BU2/rd_data_count [0]),
- .PRE(rst),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 )
- );
- FD #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 )
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/rstblk/rst_d2 (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ),
- .PRE(rst),
- .Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 )
- );
- FD #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 )
- );
- FD #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 )
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/rstblk/rst_d3 (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
- .PRE(rst),
- .Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 )
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/RST_FULL_GEN (
- .C(wr_clk),
- .CLR(rst),
- .D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ),
- .Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 )
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 )
- );
- VCC \BU2/XST_VCC (
- .P(\BU2/N1 )
- );
- GND \BU2/XST_GND (
- .G(\BU2/rd_data_count [0])
- );
-
-// synthesis translate_on
-
-endmodule
-
-// synthesis translate_off
-
-`ifndef GLBL
-`define GLBL
-
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (weak1, weak0) GSR = GSR_int;
- assign (weak1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-
-`endif
-
-// synthesis translate_on
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
deleted file mode 100644
index eb98a2b70..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
+++ /dev/null
@@ -1,47 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_32x36_2clk YourInstanceName (
- .rst(rst),
- .wr_clk(wr_clk),
- .rd_clk(rd_clk),
- .din(din), // Bus [35 : 0]
- .wr_en(wr_en),
- .rd_en(rd_en),
- .dout(dout), // Bus [35 : 0]
- .full(full),
- .almost_full(almost_full),
- .empty(empty),
- .prog_full(prog_full));
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
deleted file mode 100644
index 1cf4c8ba5..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.2
-# Date: Fri Oct 15 07:50:15 2010
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = false
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = false
-SET simulationfiles = Structural
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.1
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=true
-CSET component_name=fifo_xlnx_32x36_2clk
-CSET data_count=false
-CSET data_count_width=5
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Distributed_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=24
-CSET full_threshold_negate_value=23
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=36
-CSET input_depth=32
-CSET output_data_width=36
-CSET output_depth=32
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=5
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=5
-# END Parameters
-GENERATE
-# CRC: 8e84ee7f
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
deleted file mode 100644
index b9eb7bd1a..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
+++ /dev/null
@@ -1,72 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="fifo_xlnx_32x36_2clk.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- </file>
- <file xil_pn:name="fifo_xlnx_32x36_2clk.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_32x36_2clk.ngc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-10-15T00:50:17" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F8449944117490A53CFE9CD2127BE2AA" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
deleted file mode 100644
index b8c69a9f7..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-# Output products list for <fifo_xlnx_32x36_2clk>
-_xmsgs/pn_parser.xmsgs
-fifo_generator_ug175.pdf
-fifo_xlnx_32x36_2clk.gise
-fifo_xlnx_32x36_2clk.ngc
-fifo_xlnx_32x36_2clk.v
-fifo_xlnx_32x36_2clk.veo
-fifo_xlnx_32x36_2clk.xco
-fifo_xlnx_32x36_2clk.xise
-fifo_xlnx_32x36_2clk_flist.txt
-fifo_xlnx_32x36_2clk_readme.txt
-fifo_xlnx_32x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
deleted file mode 100644
index 8ab5679fd..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-The following files were generated for 'fifo_xlnx_32x36_2clk' in directory
-/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
-
-fifo_generator_ug175.pdf:
- Please see the core data sheet.
-
-fifo_xlnx_32x36_2clk.gise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_xlnx_32x36_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_32x36_2clk.v:
- Unisim Verilog file containing the information required to simulate
- the module.
-
-fifo_xlnx_32x36_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_32x36_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_32x36_2clk.xise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_xlnx_32x36_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_32x36_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-fifo_xlnx_32x36_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
deleted file mode 100644
index ec9426357..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_32x36_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_32x36_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_32x36_2clk
-}
-# ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_32x36_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy
deleted file mode 100644
index ecc80b648..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy
+++ /dev/null
@@ -1,49 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk
-RECTANGLE Normal 32 32 544 672
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName wr_clk
-PINATTR Polarity IN
-LINE Normal 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName rd_clk
-PINATTR Polarity IN
-LINE Normal 144 704 144 672
-PIN 144 704 BOTTOM 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 576 80 544 80
-PIN 576 80 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 576 208 544 208
-PIN 576 208 RIGHT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Wide 576 368 544 368
-PIN 576 368 RIGHT 36
-PINATTR PinName wr_data_count[8:0]
-PINATTR Polarity OUT
-LINE Normal 576 432 544 432
-PIN 576 432 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-LINE Wide 576 592 544 592
-PIN 576 592 RIGHT 36
-PINATTR PinName rd_data_count[8:0]
-PINATTR Polarity OUT
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc
deleted file mode 100644
index 55486485a..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.4e
-$4g64g<,[o}e~g`n;"2*413&;$>"9 > %17?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym
deleted file mode 100644
index 13e8af33d..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym
+++ /dev/null
@@ -1,74 +0,0 @@
-VERSION 5
-BEGIN SYMBOL fifo_xlnx_512x36_2clk
-SYMBOLTYPE BLOCK
-TIMESTAMP 2008 7 28 22 45 53
-SYMPIN 0 80 Input din[35:0]
-SYMPIN 0 144 Input wr_en
-SYMPIN 0 176 Input wr_clk
-SYMPIN 0 240 Input rd_en
-SYMPIN 0 272 Input rd_clk
-SYMPIN 144 704 Input rst
-SYMPIN 576 80 Output dout[35:0]
-SYMPIN 576 208 Output full
-SYMPIN 576 368 Output wr_data_count[8:0]
-SYMPIN 576 432 Output empty
-SYMPIN 576 592 Output rd_data_count[8:0]
-BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk
- FONT 40 "Arial"
-END DISPLAY
-RECTANGLE N 32 32 544 672
-BEGIN LINE W 0 80 32 80
-END LINE
-BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 0 144 32 144
-BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 0 176 32 176
-BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 0 240 32 240
-BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 0 272 32 272
-BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName
- FONT 24 "Arial"
-END DISPLAY
-LINE N 144 704 144 672
-BEGIN DISPLAY 144 668 PIN rst ATTR PinName
- ALIGNMENT BCENTER
- FONT 24 "Arial"
-END DISPLAY
-BEGIN LINE W 576 80 544 80
-END LINE
-BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-LINE N 576 208 544 208
-BEGIN DISPLAY 540 208 PIN full ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-BEGIN LINE W 576 368 544 368
-END LINE
-BEGIN DISPLAY 540 368 PIN wr_data_count[8:0] ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-LINE N 576 432 544 432
-BEGIN DISPLAY 540 432 PIN empty ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-BEGIN LINE W 576 592 544 592
-END LINE
-BEGIN DISPLAY 540 592 PIN rd_data_count[8:0] ATTR PinName
- ALIGNMENT RIGHT
- FONT 24 "Arial"
-END DISPLAY
-END SYMBOL
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v
deleted file mode 100644
index 905069743..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v
+++ /dev/null
@@ -1,169 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating
-// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_xlnx_512x36_2clk(
- din,
- rd_clk,
- rd_en,
- rst,
- wr_clk,
- wr_en,
- dout,
- empty,
- full,
- rd_data_count,
- wr_data_count);
-
-
-input [35 : 0] din;
-input rd_clk;
-input rd_en;
-input rst;
-input wr_clk;
-input wr_en;
-output [35 : 0] dout;
-output empty;
-output full;
-output [9 : 0] rd_data_count;
-output [9 : 0] wr_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V4_3 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(10),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(36),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(36),
- .C_ENABLE_RLOCS(0),
- .C_FAMILY("spartan3"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(1),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("512x36"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(511),
- .C_PROG_FULL_THRESH_NEGATE_VAL(510),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(10),
- .C_RD_DEPTH(512),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(9),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(1),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(10),
- .C_WR_DEPTH(512),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(9),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .DIN(din),
- .RD_CLK(rd_clk),
- .RD_EN(rd_en),
- .RST(rst),
- .WR_CLK(wr_clk),
- .WR_EN(wr_en),
- .DOUT(dout),
- .EMPTY(empty),
- .FULL(full),
- .RD_DATA_COUNT(rd_data_count),
- .WR_DATA_COUNT(wr_data_count),
- .CLK(),
- .INT_CLK(),
- .BACKUP(),
- .BACKUP_MARKER(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .RD_RST(),
- .SRST(),
- .WR_RST(),
- .ALMOST_EMPTY(),
- .ALMOST_FULL(),
- .DATA_COUNT(),
- .OVERFLOW(),
- .PROG_EMPTY(),
- .PROG_FULL(),
- .VALID(),
- .UNDERFLOW(),
- .WR_ACK(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo
deleted file mode 100644
index 6699ee73b..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_512x36_2clk YourInstanceName (
- .din(din), // Bus [35 : 0]
- .rd_clk(rd_clk),
- .rd_en(rd_en),
- .rst(rst),
- .wr_clk(wr_clk),
- .wr_en(wr_en),
- .dout(dout), // Bus [35 : 0]
- .empty(empty),
- .full(full),
- .rd_data_count(rd_data_count), // Bus [9 : 0]
- .wr_data_count(wr_data_count)); // Bus [9 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating
-// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd
deleted file mode 100644
index d9c2dd307..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd
+++ /dev/null
@@ -1,156 +0,0 @@
---------------------------------------------------------------------------------
--- This file is owned and controlled by Xilinx and must be used --
--- solely for design, simulation, implementation and creation of --
--- design files limited to Xilinx devices or technologies. Use --
--- with non-Xilinx devices or technologies is expressly prohibited --
--- and immediately terminates your license. --
--- --
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
--- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
--- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
--- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
--- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
--- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
--- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
--- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
--- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
--- FOR A PARTICULAR PURPOSE. --
--- --
--- Xilinx products are not intended for use in life support --
--- appliances, devices, or systems. Use in such applications are --
--- expressly prohibited. --
--- --
--- (c) Copyright 1995-2007 Xilinx, Inc. --
--- All rights reserved. --
---------------------------------------------------------------------------------
--- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
--- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY fifo_xlnx_512x36_2clk IS
- port (
- din: IN std_logic_VECTOR(35 downto 0);
- rd_clk: IN std_logic;
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_clk: IN std_logic;
- wr_en: IN std_logic;
- dout: OUT std_logic_VECTOR(35 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- rd_data_count: OUT std_logic_VECTOR(8 downto 0);
- wr_data_count: OUT std_logic_VECTOR(8 downto 0));
-END fifo_xlnx_512x36_2clk;
-
-ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS
--- synthesis translate_off
-component wrapped_fifo_xlnx_512x36_2clk
- port (
- din: IN std_logic_VECTOR(35 downto 0);
- rd_clk: IN std_logic;
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_clk: IN std_logic;
- wr_en: IN std_logic;
- dout: OUT std_logic_VECTOR(35 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- rd_data_count: OUT std_logic_VECTOR(8 downto 0);
- wr_data_count: OUT std_logic_VECTOR(8 downto 0));
-end component;
-
--- Configuration specification
- for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
- generic map(
- c_has_int_clk => 0,
- c_rd_freq => 1,
- c_wr_response_latency => 1,
- c_has_srst => 0,
- c_has_rd_data_count => 1,
- c_din_width => 36,
- c_has_wr_data_count => 1,
- c_full_flags_rst_val => 1,
- c_implementation_type => 2,
- c_family => "spartan3",
- c_use_embedded_reg => 0,
- c_has_wr_rst => 0,
- c_wr_freq => 1,
- c_use_dout_rst => 0,
- c_underflow_low => 0,
- c_has_meminit_file => 0,
- c_has_overflow => 0,
- c_preload_latency => 0,
- c_dout_width => 36,
- c_msgon_val => 1,
- c_rd_depth => 512,
- c_default_value => "BlankString",
- c_mif_file_name => "BlankString",
- c_has_underflow => 0,
- c_has_rd_rst => 0,
- c_has_almost_full => 0,
- c_has_rst => 1,
- c_data_count_width => 9,
- c_has_wr_ack => 0,
- c_use_ecc => 0,
- c_wr_ack_low => 0,
- c_common_clock => 0,
- c_rd_pntr_width => 9,
- c_use_fwft_data_count => 0,
- c_has_almost_empty => 0,
- c_rd_data_count_width => 9,
- c_enable_rlocs => 0,
- c_wr_pntr_width => 9,
- c_overflow_low => 0,
- c_prog_empty_type => 0,
- c_optimization_mode => 0,
- c_wr_data_count_width => 9,
- c_preload_regs => 1,
- c_dout_rst_val => "0",
- c_has_data_count => 0,
- c_prog_full_thresh_negate_val => 510,
- c_wr_depth => 512,
- c_prog_empty_thresh_negate_val => 5,
- c_prog_empty_thresh_assert_val => 4,
- c_has_valid => 0,
- c_init_wr_pntr_val => 0,
- c_prog_full_thresh_assert_val => 511,
- c_use_fifo16_flags => 0,
- c_has_backup => 0,
- c_valid_low => 0,
- c_prim_fifo_type => "512x36",
- c_count_type => 0,
- c_prog_full_type => 0,
- c_memory_type => 1);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_fifo_xlnx_512x36_2clk
- port map (
- din => din,
- rd_clk => rd_clk,
- rd_en => rd_en,
- rst => rst,
- wr_clk => wr_clk,
- wr_en => wr_en,
- dout => dout,
- empty => empty,
- full => full,
- rd_data_count => rd_data_count,
- wr_data_count => wr_data_count);
--- synthesis translate_on
-
-END fifo_xlnx_512x36_2clk_a;
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho
deleted file mode 100644
index 70eac27a5..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho
+++ /dev/null
@@ -1,76 +0,0 @@
---------------------------------------------------------------------------------
--- This file is owned and controlled by Xilinx and must be used --
--- solely for design, simulation, implementation and creation of --
--- design files limited to Xilinx devices or technologies. Use --
--- with non-Xilinx devices or technologies is expressly prohibited --
--- and immediately terminates your license. --
--- --
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
--- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
--- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
--- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
--- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
--- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
--- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
--- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
--- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
--- FOR A PARTICULAR PURPOSE. --
--- --
--- Xilinx products are not intended for use in life support --
--- appliances, devices, or systems. Use in such applications are --
--- expressly prohibited. --
--- --
--- (c) Copyright 1995-2007 Xilinx, Inc. --
--- All rights reserved. --
---------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component fifo_xlnx_512x36_2clk
- port (
- din: IN std_logic_VECTOR(35 downto 0);
- rd_clk: IN std_logic;
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_clk: IN std_logic;
- wr_en: IN std_logic;
- dout: OUT std_logic_VECTOR(35 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- rd_data_count: OUT std_logic_VECTOR(8 downto 0);
- wr_data_count: OUT std_logic_VECTOR(8 downto 0));
-end component;
-
--- Synplicity black box declaration
-attribute syn_black_box : boolean;
-attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : fifo_xlnx_512x36_2clk
- port map (
- din => din,
- rd_clk => rd_clk,
- rd_en => rd_en,
- rst => rst,
- wr_clk => wr_clk,
- wr_en => wr_en,
- dout => dout,
- empty => empty,
- full => full,
- rd_data_count => rd_data_count,
- wr_data_count => wr_data_count);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
--- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
deleted file mode 100644
index 5934ef285..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
+++ /dev/null
@@ -1,82 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version K.39
-# Date: Thu Sep 3 17:24:24 2009
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = True
-SET vhdlsim = False
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 4.3
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_xlnx_512x36_2clk
-CSET data_count=false
-CSET data_count_width=10
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=511
-CSET full_threshold_negate_value=510
-CSET input_data_width=36
-CSET input_depth=512
-CSET output_data_width=36
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=10
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=true
-CSET write_data_count_width=10
-# END Parameters
-GENERATE
-# CRC: b7f2a9ba
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise
deleted file mode 100644
index c18cf3bf0..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise
+++ /dev/null
@@ -1,30 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_18to36.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_18to36.veo" xil_pn:origination="imported"/>
- </files>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf
deleted file mode 100644
index e69de29bb..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf
+++ /dev/null
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc
deleted file mode 100644
index d9277b0c3..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
deleted file mode 100644
index 25ac9779e..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
+++ /dev/null
@@ -1,173 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating
-// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_xlnx_512x36_2clk_18to36(
- rst,
- wr_clk,
- rd_clk,
- din,
- wr_en,
- rd_en,
- dout,
- full,
- almost_full,
- empty,
- prog_full);
-
-
-input rst;
-input wr_clk;
-input rd_clk;
-input [17 : 0] din;
-input wr_en;
-input rd_en;
-output [35 : 0] dout;
-output full;
-output almost_full;
-output empty;
-output prog_full;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V6_1 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(10),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(18),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(36),
- .C_ENABLE_RLOCS(0),
- .C_ENABLE_RST_SYNC(1),
- .C_ERROR_INJECTION_TYPE(0),
- .C_FAMILY("spartan3"),
- .C_FULL_FLAGS_RST_VAL(0),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(1),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(0),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(0),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("1kx18"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(1015),
- .C_PROG_FULL_THRESH_NEGATE_VAL(1014),
- .C_PROG_FULL_TYPE(1),
- .C_RD_DATA_COUNT_WIDTH(9),
- .C_RD_DEPTH(512),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(9),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(0),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(10),
- .C_WR_DEPTH(1024),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(10),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .RST(rst),
- .WR_CLK(wr_clk),
- .RD_CLK(rd_clk),
- .DIN(din),
- .WR_EN(wr_en),
- .RD_EN(rd_en),
- .DOUT(dout),
- .FULL(full),
- .ALMOST_FULL(almost_full),
- .EMPTY(empty),
- .PROG_FULL(prog_full),
- .BACKUP(),
- .BACKUP_MARKER(),
- .CLK(),
- .SRST(),
- .WR_RST(),
- .RD_RST(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .INT_CLK(),
- .INJECTDBITERR(),
- .INJECTSBITERR(),
- .WR_ACK(),
- .OVERFLOW(),
- .ALMOST_EMPTY(),
- .VALID(),
- .UNDERFLOW(),
- .DATA_COUNT(),
- .RD_DATA_COUNT(),
- .WR_DATA_COUNT(),
- .PROG_EMPTY(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo
deleted file mode 100644
index db2795098..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_512x36_2clk_18to36 YourInstanceName (
- .rst(rst),
- .wr_clk(wr_clk),
- .rd_clk(rd_clk),
- .din(din), // Bus [17 : 0]
- .wr_en(wr_en),
- .rd_en(rd_en),
- .dout(dout), // Bus [35 : 0]
- .full(full),
- .almost_full(almost_full),
- .empty(empty),
- .prog_full(prog_full));
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating
-// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
deleted file mode 100644
index f888ba5f4..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.1
-# Date: Wed Aug 18 17:27:35 2010
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = false
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.1
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=true
-CSET component_name=fifo_xlnx_512x36_2clk_18to36
-CSET data_count=false
-CSET data_count_width=10
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=1015
-CSET full_threshold_negate_value=1014
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=18
-CSET input_depth=1024
-CSET output_data_width=36
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=10
-# END Parameters
-GENERATE
-# CRC: 77234081
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise
deleted file mode 100644
index 04acaf578..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise
+++ /dev/null
@@ -1,72 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="fifo_xlnx_512x36_2clk_18to36.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- </file>
- <file xil_pn:name="fifo_xlnx_512x36_2clk_18to36.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_18to36.ngc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-08-18T10:27:37" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="224FA43C81F32871F9E1930EA6CDD6AD" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt
deleted file mode 100644
index 2f8d522f6..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-# Output products list for <fifo_xlnx_512x36_2clk_18to36>
-_xmsgs/pn_parser.xmsgs
-fifo_generator_ug175.pdf
-fifo_xlnx_512x36_2clk_18to36.gise
-fifo_xlnx_512x36_2clk_18to36.ngc
-fifo_xlnx_512x36_2clk_18to36.v
-fifo_xlnx_512x36_2clk_18to36.veo
-fifo_xlnx_512x36_2clk_18to36.xco
-fifo_xlnx_512x36_2clk_18to36.xise
-fifo_xlnx_512x36_2clk_18to36_flist.txt
-fifo_xlnx_512x36_2clk_18to36_readme.txt
-fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt
deleted file mode 100644
index 03829e876..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory
-/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
-
-fifo_generator_ug175.pdf:
- Please see the core data sheet.
-
-fifo_xlnx_512x36_2clk_18to36.gise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_xlnx_512x36_2clk_18to36.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_512x36_2clk_18to36.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_xlnx_512x36_2clk_18to36.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_512x36_2clk_18to36.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_512x36_2clk_18to36.xise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_xlnx_512x36_2clk_18to36_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_512x36_2clk_18to36_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-fifo_xlnx_512x36_2clk_18to36_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
deleted file mode 100644
index 9b9b1f37a..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_512x36_2clk_18to36_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_512x36_2clk_18to36_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_18to36
-}
-# ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_18to36
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise
deleted file mode 100644
index d0c862319..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise
+++ /dev/null
@@ -1,30 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_36to18.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_36to18.veo" xil_pn:origination="imported"/>
- </files>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf
deleted file mode 100644
index e69de29bb..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf
+++ /dev/null
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc
deleted file mode 100644
index 00814f02e..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
deleted file mode 100644
index b3d994ae8..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
+++ /dev/null
@@ -1,169 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating
-// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_xlnx_512x36_2clk_36to18(
- rst,
- wr_clk,
- rd_clk,
- din,
- wr_en,
- rd_en,
- dout,
- full,
- empty);
-
-
-input rst;
-input wr_clk;
-input rd_clk;
-input [35 : 0] din;
-input wr_en;
-input rd_en;
-output [17 : 0] dout;
-output full;
-output empty;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V6_1 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(9),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(36),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(18),
- .C_ENABLE_RLOCS(0),
- .C_ENABLE_RST_SYNC(1),
- .C_ERROR_INJECTION_TYPE(0),
- .C_FAMILY("spartan3"),
- .C_FULL_FLAGS_RST_VAL(0),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(0),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(0),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("512x36"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(509),
- .C_PROG_FULL_THRESH_NEGATE_VAL(508),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(10),
- .C_RD_DEPTH(1024),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(10),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(0),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(9),
- .C_WR_DEPTH(512),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(9),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .RST(rst),
- .WR_CLK(wr_clk),
- .RD_CLK(rd_clk),
- .DIN(din),
- .WR_EN(wr_en),
- .RD_EN(rd_en),
- .DOUT(dout),
- .FULL(full),
- .EMPTY(empty),
- .BACKUP(),
- .BACKUP_MARKER(),
- .CLK(),
- .SRST(),
- .WR_RST(),
- .RD_RST(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .INT_CLK(),
- .INJECTDBITERR(),
- .INJECTSBITERR(),
- .ALMOST_FULL(),
- .WR_ACK(),
- .OVERFLOW(),
- .ALMOST_EMPTY(),
- .VALID(),
- .UNDERFLOW(),
- .DATA_COUNT(),
- .RD_DATA_COUNT(),
- .WR_DATA_COUNT(),
- .PROG_FULL(),
- .PROG_EMPTY(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo
deleted file mode 100644
index e93be1591..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo
+++ /dev/null
@@ -1,51 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_512x36_2clk_36to18 YourInstanceName (
- .rst(rst),
- .wr_clk(wr_clk),
- .rd_clk(rd_clk),
- .din(din), // Bus [35 : 0]
- .wr_en(wr_en),
- .rd_en(rd_en),
- .dout(dout), // Bus [17 : 0]
- .full(full),
- .empty(empty));
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating
-// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
deleted file mode 100644
index d3115e7d5..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.1
-# Date: Thu Aug 12 21:06:13 2010
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = false
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.1
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_xlnx_512x36_2clk_36to18
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=509
-CSET full_threshold_negate_value=508
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=36
-CSET input_depth=512
-CSET output_data_width=18
-CSET output_depth=1024
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=10
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-# END Parameters
-GENERATE
-# CRC: a4e70980
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise
deleted file mode 100644
index cfe983130..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise
+++ /dev/null
@@ -1,72 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="fifo_xlnx_512x36_2clk_36to18.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- </file>
- <file xil_pn:name="fifo_xlnx_512x36_2clk_36to18.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_36to18.ngc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-08-12T14:06:16" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3646C65496E43142DA83C69469B5BF88" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt
deleted file mode 100644
index 54c85b15e..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-# Output products list for <fifo_xlnx_512x36_2clk_36to18>
-_xmsgs/pn_parser.xmsgs
-fifo_generator_ug175.pdf
-fifo_xlnx_512x36_2clk_36to18.gise
-fifo_xlnx_512x36_2clk_36to18.ngc
-fifo_xlnx_512x36_2clk_36to18.v
-fifo_xlnx_512x36_2clk_36to18.veo
-fifo_xlnx_512x36_2clk_36to18.xco
-fifo_xlnx_512x36_2clk_36to18.xise
-fifo_xlnx_512x36_2clk_36to18_flist.txt
-fifo_xlnx_512x36_2clk_36to18_readme.txt
-fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt
deleted file mode 100644
index 3efc586bf..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory
-/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
-
-fifo_generator_ug175.pdf:
- Please see the core data sheet.
-
-fifo_xlnx_512x36_2clk_36to18.gise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_xlnx_512x36_2clk_36to18.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_512x36_2clk_36to18.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_xlnx_512x36_2clk_36to18.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_512x36_2clk_36to18.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_512x36_2clk_36to18.xise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_xlnx_512x36_2clk_36to18_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_512x36_2clk_36to18_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-fifo_xlnx_512x36_2clk_36to18_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
deleted file mode 100644
index 5161c1826..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_512x36_2clk_36to18_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_512x36_2clk_36to18_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_36to18
-}
-# ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_36to18
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
deleted file mode 100644
index f1a6f7899..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
+++ /dev/null
@@ -1,3 +0,0 @@
-blkmemdp_v6_2
-blk_mem_gen_v2_6
-fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
deleted file mode 100644
index d110a0158..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ /dev/null
@@ -1,109 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
-<document OS="lin64" product="ISE" version="10.1.03">
-
- <!--The data in this file is primarily intended for consumption by Xilinx tools.
- The structure and the elements are likely to change over the next few releases.
- This means code written to parse this file will need to be revisited each subsequent release.-->
-
- <application stringID="Xst" timeStamp="Thu Sep 3 10:23:58 2009">
- <section stringID="XST_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
- <item dataType="int" stringID="XST_10BIT_ADDER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="31">
- <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
- <item dataType="int" stringID="XST_10BIT_REGISTER" value="2"/>
- <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_36BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_9BIT_REGISTER" value="11"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="68">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="68"/>
- </item>
- </section>
- <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_FSMS" value="1"/>
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
- <item dataType="int" stringID="XST_10BIT_ADDER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="165">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="165"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="68">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="68"/>
- </item>
- </section>
- <section stringID="XST_FINAL_REGISTER_REPORT">
- <item dataType="int" stringID="XST_REGISTERS" value="192">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="192"/>
- </item>
- </section>
- <section stringID="XST_PARTITION_REPORT">
- <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- </section>
- <section stringID="XST_FINAL_REPORT">
- <section stringID="XST_FINAL_RESULTS">
- <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc"/>
- <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
- <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
- <item stringID="XST_KEEP_HIERARCHY" value="no"/>
- </section>
- <section stringID="XST_DESIGN_STATISTICS">
- <item stringID="XST_IOS" value="180"/>
- </section>
- <section stringID="XST_CELL_USAGE">
- <item dataType="int" stringID="XST_BELS" value="223">
- <item dataType="int" stringID="XST_GND" value="1"/>
- <item dataType="int" stringID="XST_INV" value="1"/>
- <item dataType="int" stringID="XST_LUT1" value="18"/>
- <item dataType="int" stringID="XST_LUT2" value="50"/>
- <item dataType="int" stringID="XST_LUT2D" value="1"/>
- <item dataType="int" stringID="XST_LUT3" value="16"/>
- <item dataType="int" stringID="XST_LUT3D" value="1"/>
- <item dataType="int" stringID="XST_LUT3L" value="1"/>
- <item dataType="int" stringID="XST_LUT4" value="45"/>
- <item dataType="int" stringID="XST_MUXCY" value="52"/>
- <item dataType="int" stringID="XST_VCC" value="1"/>
- <item dataType="int" stringID="XST_XORCY" value="36"/>
- </item>
- <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="192">
- <item dataType="int" stringID="XST_FD" value="4"/>
- <item dataType="int" stringID="XST_FDC" value="85"/>
- <item dataType="int" stringID="XST_FDCE" value="78"/>
- <item dataType="int" stringID="XST_FDP" value="10"/>
- <item dataType="int" stringID="XST_FDPE" value="5"/>
- </item>
- <item dataType="int" stringID="XST_RAMS" value="1">
- <item dataType="int" stringID="XST_RAMB16S36S36" value="1"/>
- </item>
- </section>
- </section>
- <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
- <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
- <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="137"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="192"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="133"/>
- <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="180"/>
- <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
- <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="1"/>
- </section>
- <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- <section stringID="XST_ERRORS_STATISTICS">
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="128"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="17"/>
- </section>
- </application>
-
-</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt
deleted file mode 100644
index b0975be2d..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# Output products list for <fifo_xlnx_512x36_2clk>
-fifo_xlnx_512x36_2clk.ngc
-fifo_xlnx_512x36_2clk.v
-fifo_xlnx_512x36_2clk.veo
-fifo_xlnx_512x36_2clk.xco
-fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-fifo_xlnx_512x36_2clk_flist.txt
-fifo_xlnx_512x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
deleted file mode 100644
index 660fb2f65..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
+++ /dev/null
@@ -1,28 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema"/>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf
deleted file mode 100644
index e69de29bb..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf
+++ /dev/null
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc
deleted file mode 100644
index 9cb73d5ce..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
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-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
deleted file mode 100644
index 6ec1e3f88..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
+++ /dev/null
@@ -1,173 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating
-// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_xlnx_512x36_2clk_prog_full(
- rst,
- wr_clk,
- rd_clk,
- din,
- wr_en,
- rd_en,
- dout,
- full,
- almost_full,
- empty,
- prog_full);
-
-
-input rst;
-input wr_clk;
-input rd_clk;
-input [35 : 0] din;
-input wr_en;
-input rd_en;
-output [35 : 0] dout;
-output full;
-output almost_full;
-output empty;
-output prog_full;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V6_1 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(9),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(36),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(36),
- .C_ENABLE_RLOCS(0),
- .C_ENABLE_RST_SYNC(1),
- .C_ERROR_INJECTION_TYPE(0),
- .C_FAMILY("spartan3"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(1),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(0),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(0),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("512x36"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(500),
- .C_PROG_FULL_THRESH_NEGATE_VAL(499),
- .C_PROG_FULL_TYPE(1),
- .C_RD_DATA_COUNT_WIDTH(9),
- .C_RD_DEPTH(512),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(9),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(0),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(9),
- .C_WR_DEPTH(512),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(9),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .RST(rst),
- .WR_CLK(wr_clk),
- .RD_CLK(rd_clk),
- .DIN(din),
- .WR_EN(wr_en),
- .RD_EN(rd_en),
- .DOUT(dout),
- .FULL(full),
- .ALMOST_FULL(almost_full),
- .EMPTY(empty),
- .PROG_FULL(prog_full),
- .BACKUP(),
- .BACKUP_MARKER(),
- .CLK(),
- .SRST(),
- .WR_RST(),
- .RD_RST(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .INT_CLK(),
- .INJECTDBITERR(),
- .INJECTSBITERR(),
- .WR_ACK(),
- .OVERFLOW(),
- .ALMOST_EMPTY(),
- .VALID(),
- .UNDERFLOW(),
- .DATA_COUNT(),
- .RD_DATA_COUNT(),
- .WR_DATA_COUNT(),
- .PROG_EMPTY(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo
deleted file mode 100644
index 64e6769d6..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2009 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_512x36_2clk_prog_full YourInstanceName (
- .rst(rst),
- .wr_clk(wr_clk),
- .rd_clk(rd_clk),
- .din(din), // Bus [35 : 0]
- .wr_en(wr_en),
- .rd_en(rd_en),
- .dout(dout), // Bus [35 : 0]
- .full(full),
- .almost_full(almost_full),
- .empty(empty),
- .prog_full(prog_full));
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating
-// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
deleted file mode 100644
index f99c3c6fb..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.2
-# Date: Thu Nov 11 17:27:10 2010
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = false
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.1
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=true
-CSET component_name=fifo_xlnx_512x36_2clk_prog_full
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=500
-CSET full_threshold_negate_value=499
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=36
-CSET input_depth=512
-CSET output_data_width=36
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-# END Parameters
-GENERATE
-# CRC: 6b9f6232
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise
deleted file mode 100644
index 91dbf5819..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise
+++ /dev/null
@@ -1,72 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- </file>
- <file xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_prog_full.ngc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-11-11T09:27:12" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="96435AE73456681FC0EF5839C85C4C97" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt
deleted file mode 100644
index 2eb837a3f..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-# Output products list for <fifo_xlnx_512x36_2clk_prog_full>
-_xmsgs/pn_parser.xmsgs
-fifo_generator_ug175.pdf
-fifo_xlnx_512x36_2clk_prog_full.gise
-fifo_xlnx_512x36_2clk_prog_full.ngc
-fifo_xlnx_512x36_2clk_prog_full.v
-fifo_xlnx_512x36_2clk_prog_full.veo
-fifo_xlnx_512x36_2clk_prog_full.xco
-fifo_xlnx_512x36_2clk_prog_full.xise
-fifo_xlnx_512x36_2clk_prog_full_flist.txt
-fifo_xlnx_512x36_2clk_prog_full_readme.txt
-fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt
deleted file mode 100644
index 33d50a91d..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-The following files were generated for 'fifo_xlnx_512x36_2clk_prog_full' in directory
-/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
-
-fifo_generator_ug175.pdf:
- Please see the core data sheet.
-
-fifo_xlnx_512x36_2clk_prog_full.gise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_xlnx_512x36_2clk_prog_full.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_512x36_2clk_prog_full.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_xlnx_512x36_2clk_prog_full.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_512x36_2clk_prog_full.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_512x36_2clk_prog_full.xise:
- ISE Project Navigator support file. This is a generated file and should
- not be edited directly.
-
-fifo_xlnx_512x36_2clk_prog_full_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-fifo_xlnx_512x36_2clk_prog_full_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
deleted file mode 100644
index e1aecccff..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_512x36_2clk_prog_full_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_512x36_2clk_prog_full_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_prog_full
-}
-# ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_prog_full
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt
deleted file mode 100644
index a250a74f5..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-The following files were generated for 'fifo_xlnx_512x36_2clk' in directory
-/home/matt/gnuradio.git/usrp2/fpga/coregen/:
-
-fifo_xlnx_512x36_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_512x36_2clk.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_xlnx_512x36_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_512x36_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
- Please see the core data sheet.
-
-fifo_xlnx_512x36_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-fifo_xlnx_512x36_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_512x36_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
deleted file mode 100644
index 8a0c0e3ff..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_512x36_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_512x36_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk
-}
-# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc
deleted file mode 100644
index e8c55a1af..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.4e
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p`>2`c94?7|@=2;7p`>2``94?7|@=2;7p`>2`a94?7|@=2;7p`>2`f94?7|@=2;7p`>2`g94?7|@=2;7p`>2`d94?7|@=2;7p`>2c294?7|@=2;7p`>2c394?7|@=2;7p`>2c094?7|@=2;7p`>2c194?7|@=2;7p`>2c694?7|@=2;7p`>2c794?7|@=2;7p`>2c494?7|@=2;7p`>2c594?7|@=2;7p`>2c:94?7|@=2;7p`>2c;94?7|@=2;7p`>2cc94?7|@=2;7p`>2c`94?7|@=2;7p`>2ca94?7|@=2;7p`>2cf94?7|@=2;7p`>2cg94?7|@=2;7p`>2cd94?7|@=2;7p`>2b294?7|@=2;7p`>2b394?7|@=2;7p`>2b094?7|@=2;7p`>2b194?7|@=2;7p`>2b694?7|@=2;7p`>2b794?7|@=2;7p`>2b494?7|@=2;7p`>2b594?7|@=2;7p`>2b:94?7|@=2;7p`>2b;94?7|@=2;7p`>2bc94?7|@=2;7p`>2b`94?7|@=2;7p`>2ba94?7|@=2;7p`>2bf94?7|@=2;7p`>2bg94?7|@=2;7p`>2bd94?7|@=2;7p`>2e294?7|@=2;7p`>2e394?7|@=2;7p`>2e094?7|@=2;7p`>2e194?7|@=2;7p`>2e694?7|@=2;7p`>2e794?7|@=2;7p`>2e494?7|@=2;7p`>2e594?7|@=2;7p`>2e:94?7|@=2;7p`>2e;94?7|@=2;7p`>2ec94?7|@=2;7p`>2e`94?7|@=2;7p`>2ea94?7|@=2;7p`>2ef94?7|@=2;7p`>2eg94?7|@=2;7p`>2ed94?7|@=2;7p`>2d294?7|@=2;7p`>2d394?7|@=2;7p`>2d094?7|@=2;7p`>2d194?7|@=2;7p`>2d694?7|@=2;7p`>2d794?7|@=2;7p`>2d494?7|@=2;7p`>2d594?7|@=2;7p`>2d:94?7|@=2;7p`>2d;94?7|@=2;7p`>2dc94?7|@=2;7p`>2d`94?7|@=2;7p`>2da94?7|@=2;7p`>2df94?7|@=2;7p`>2dg94?7|@=2;7p`>2dd94?7|@=2;7p`>2g294?7|@=2;7p`>2g394?7|@=2;7p`>2g094?7|@=2;7p`>2g194?7|@=2;7p`>2g694?7|@=2;7p`>2g794?7|@=2;7p`>2g494?7|@=2;7p`>2g594?7|@=2;7p`>2g:94?7|@=2;7p`>2g;94?7|@=2;7p`>2gc94?7|@=2;7p`>2g`94?7|@=2;7p`>2ga94?7|@=2;7p`>2gf94?7|@=2;7p`>2gg94?7|@=2;7p`>2gd94?7|@=2;7p`>31294?7|@=2;7p`>31394?7|@=2;7p`>31094?7|@=2;7p`>31194?7|@=2;7p`>31694?7|@=2;7p`>31794?7|@=2;7p`>31494?7|@=2;7p`>31594?7|@=2;7p`>31:94?7|@=2;7p`>31;94?7|@=2;7p`>31c94?7|@=2;7p`>31`94?7|@=2;7p`>31a94?7|@=2;7p`>31f94?7|@=2;7p`>31g94?7|@=2;7p`>31d94?7|@=2;7p`>30294?7|@=2;7p`>30394?7|@=2;7p`>30094?7|@=2;7p`>30194?7|@=2;7p`>30694?7|@=2;7p`>30794?7|@=2;7p`>30494?7|@=2;7p`>30594?7|@=2;7p`>30:94?7|@=2;7p`>30;94?7|@=2;7p`>30c94?7|@=2;7p`>30`94?7|@=2;7p`>30a94?7|@=2;7p`>30f94?7|@=2;7p`>30g94?7|@=2;7p`>30d94?7|@=2;7p`>33294?7|@=2;7p`>33394?7|@=2;7p`>33094?7|@=2;7p`>33194?7|@=2;7p`>33694?7|@=2;7p`>33794?7|@=2;7p`>33494?7|@=2;7p`>33594?7|@=2;7p`>33:94?7|@=2;7p`>33;94?7|@=2;7p`>33c94?7|@=2;7p`>33`94?7|@=2;7p`>33a94?7|@=2;7p`>33f94?7|@=2;7p`>33g94?7|@=2;7p`>33d94?7|@=2;7p`>32294?7|@=2;7p`>32394?7|@=2;7p`>32094?7|@=2;7p`>32194?7|@=2;7p`>32694?7|@=2;7p`>32794?7|@=2;7p`>32494?7|@=2;7p`>32594?7|@=2;7p`>32:94?7|@=2;7p`>32;94?7|@=2;7p`>32c94?7|@=2;7p`>32`94?7|@=2;7p`>32a94?7|@=2;7p`>32f94?7|@=2;7p`>32g94?7|@=2;7p`>32d94?7|@=2;7p`>35294?7|@=2;7p`>35394?7|@=2;7p`>35094?7|@=2;7p`>35194?7|@=2;7p`>35694?7|@=2;7p`>35794?7|@=2;7p`>35494?7|@=2;7p`>35594?7|@=2;7p`>35:94?7|@=2;7p`>35;94?7|@=2;7p`>35c94?7|@=2;7p`>35`94?7|@=2;7p`>35a94?7|@=2;7p`>35f94?7|@=2;7p`>35g94?7|@=2;7p`>35d94?7|@=2;7p`>34294?7|@=2;7p`>34394?7|@=2;7p`>34094?7|@=2;7p`>34194?7|@=2;7p`>34694?7|@=2;7p`>34794?7|@=2;7p`>34494?7|@=2;7p`>34594?7|@=2;7p`>34:94?7|@=2;7p`>34;94?7|@=2;7p`>34c94?7|@=2;7p`>34`94?7|@=2;7p`>34a94?7|@=2;7p`>34f94?7|@=2;7p`>34g94?7|@=2;7p`>34d94?7|@=2;7p`>37294?7|@=2;7p`>37394?7|@=2;7p`>37094?7|@=2;7p`>37194?7|@=2;7p`>37694?7|@=2;7p`>37794?7|@=2;7p`>37494?7|@=2;7p`>37594?7|@=2;7p`>37:94?7|@=2;7p`>37;94?7|@=2;7p`>37c94?7|@=2;7p`>37`94?7|@=2;7p`>37a94?7|@=2;7p`>37f94?7|@=2;7p`>37g94?7|@=2;7p`>37d94?7|@=2;7p`>36294?7|@=2;7p`>36394?7|@=2;7p`>36094?7|@=2;7p`>36194?7|@=2;7p`>36694?7|@=2;7p`>36794?7|@=2;7p`>36494?7|@=2;7p`>36594?7|@=2;7p`>36:94?7|@=2;7p`>36;94?7|@=2;7p`>36c94?7|@=2;7p`>36`94?7|@=2;7p`>36a94?7|@=2;7p`>36f94?7|@=2;7p`>36g94?7|@=2;7p`>36d94?7|@=2;7p`>39294?7|@=2;7p`>39394?7|@=2;7p`>39094?7|@=2;7p`>39194?7|@=2;7p`>39694?7|@=2;7p`>39794?7|@=2;7p`>39494?7|@=2;7p`>39594?7|@=2;7p`>39:94?7|@=2;7p`>39;94?7|@=2;7p`>39c94?7|@=2;7p`>39`94?7|@=2;7p`>39a94?7|@=2;7p`>39f94?7|@=2;7p`>39g94?7|@=2;7p`>39d94?7|@=2;7p`>38294?7|@=2;7p`>38394?7|@=2;7p`>38094?7|@=2;7p`>38194?7|@=2;7p`>38694?7|@=2;7p`>38794?7|@=2;7p`>38494?7|@=2;7p`>38594?7|@=2;7p`>38:94?7|@=2;7p`>38;94?7|@=2;7p`>38c94?7|@=2;7p`>38`94?7|@=2;7p`>38a94?7|@=2;7p`>38f94?7|@=2;7p`>38g94?7|@=2;7p`>38d94?7|@=2;7p`>3`294?7|@=2;7p`>3`394?7|@=2;7p`>3`094?7|@=2;7p`>3`194?7|@=2;7p`>3`694?7|@=2;7p`>3`794?7|@=2;7p`>3`494?7|@=2;7p`>3`594?7|@=2;7p`>3`:94?7|@=2;7p`>3`;94?7|@=2;7p`>3`c94?7|@=2;7p`>3``94?7|@=2;7p`>3`a94?7|@=2;7p`>3`f94?7|@=2;7p`>3`g94?7|@=2;7p`>3`d94?7|@=2;7p`>3c294?7|@=2;7p`>3c394?7|@=2;7p`>3c094?7|@=2;7p`>3c194?7|@=2;7p`>3c694?7|@=2;7p`>3c794?7|@=2;7p`>3c494?7|@=2;7p`>3c594?7|@=2;7p`>3c:94?7|@=2;7p`>3c;94?7|@=2;7p`>3cc94?7|@=2;7p`>3c`94?7|@=2;7p`>3ca94?7|@=2;7p`>3cf94?7|@=2;7p`>3cg94?7|@=2;7p`>3cd94?7|@=2;7p`>3b294?7|@=2;7p`>3b394?7|@=2;7p`>3b094?7|@=2;7p`>3b194?7|@=2;7p`>3b694?7|@=2;7p`>3b794?7|@=2;7p`>3b494?7|@=2;7p`>3b594?7|@=2;7p`>3b:94?7|@=2;7p`>3b;94?7|@=2;7p`>3bc94?7|@=2;7p`>3b`94?7|@=2;7p`>3ba94?7|@=2;7p`>3bf94?7|@=2;7p`>3bg94?7|@=2;7p`>3bd94?7|@=2;7p`>3e294?7|@=2;7psr}AB@40?l3;?hkh977CDG}7uIJ[wpNO \ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v
deleted file mode 100644
index e84237689..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v
+++ /dev/null
@@ -1,169 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating
-// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module fifo_xlnx_64x36_2clk(
- din,
- rd_clk,
- rd_en,
- rst,
- wr_clk,
- wr_en,
- dout,
- empty,
- full,
- rd_data_count,
- wr_data_count);
-
-
-input [35 : 0] din;
-input rd_clk;
-input rd_en;
-input rst;
-input wr_clk;
-input wr_en;
-output [35 : 0] dout;
-output empty;
-output full;
-output [6 : 0] rd_data_count;
-output [6 : 0] wr_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V4_3 #(
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(7),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(36),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(36),
- .C_ENABLE_RLOCS(0),
- .C_FAMILY("spartan3"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(1),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_INIT_WR_PNTR_VAL(0),
- .C_MEMORY_TYPE(2),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(0),
- .C_PRELOAD_REGS(1),
- .C_PRIM_FIFO_TYPE("512x36"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(63),
- .C_PROG_FULL_THRESH_NEGATE_VAL(62),
- .C_PROG_FULL_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(7),
- .C_RD_DEPTH(64),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(6),
- .C_UNDERFLOW_LOW(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(1),
- .C_VALID_LOW(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(7),
- .C_WR_DEPTH(64),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(6),
- .C_WR_RESPONSE_LATENCY(1))
- inst (
- .DIN(din),
- .RD_CLK(rd_clk),
- .RD_EN(rd_en),
- .RST(rst),
- .WR_CLK(wr_clk),
- .WR_EN(wr_en),
- .DOUT(dout),
- .EMPTY(empty),
- .FULL(full),
- .RD_DATA_COUNT(rd_data_count),
- .WR_DATA_COUNT(wr_data_count),
- .CLK(),
- .INT_CLK(),
- .BACKUP(),
- .BACKUP_MARKER(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .RD_RST(),
- .SRST(),
- .WR_RST(),
- .ALMOST_EMPTY(),
- .ALMOST_FULL(),
- .DATA_COUNT(),
- .OVERFLOW(),
- .PROG_EMPTY(),
- .PROG_FULL(),
- .VALID(),
- .UNDERFLOW(),
- .WR_ACK(),
- .SBITERR(),
- .DBITERR());
-
-
-// synthesis translate_on
-
-endmodule
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo
deleted file mode 100644
index 9c761370c..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_64x36_2clk YourInstanceName (
- .din(din), // Bus [35 : 0]
- .rd_clk(rd_clk),
- .rd_en(rd_en),
- .rst(rst),
- .wr_clk(wr_clk),
- .wr_en(wr_en),
- .dout(dout), // Bus [35 : 0]
- .empty(empty),
- .full(full),
- .rd_data_count(rd_data_count), // Bus [6 : 0]
- .wr_data_count(wr_data_count)); // Bus [6 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating
-// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
deleted file mode 100644
index c6e9aae27..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
+++ /dev/null
@@ -1,82 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version K.39
-# Date: Thu Sep 3 17:22:56 2009
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = True
-SET vhdlsim = False
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 4.3
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_xlnx_64x36_2clk
-CSET data_count=false
-CSET data_count_width=7
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET fifo_implementation=Independent_Clocks_Distributed_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=63
-CSET full_threshold_negate_value=62
-CSET input_data_width=36
-CSET input_depth=64
-CSET output_data_width=36
-CSET output_depth=64
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=7
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=true
-CSET write_data_count_width=7
-# END Parameters
-GENERATE
-# CRC: 2bb925ae
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
deleted file mode 100644
index f1a6f7899..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
+++ /dev/null
@@ -1,3 +0,0 @@
-blkmemdp_v6_2
-blk_mem_gen_v2_6
-fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
deleted file mode 100644
index a23402f56..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ /dev/null
@@ -1,104 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
-<document OS="lin64" product="ISE" version="10.1.03">
-
- <!--The data in this file is primarily intended for consumption by Xilinx tools.
- The structure and the elements are likely to change over the next few releases.
- This means code written to parse this file will need to be revisited each subsequent release.-->
-
- <application stringID="Xst" timeStamp="Thu Sep 3 10:22:37 2009">
- <section stringID="XST_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_RAMS" value="1"></item>
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2"></item>
- <item dataType="int" stringID="XST_REGISTERS" value="32">
- <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
- <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_36BIT_REGISTER" value="2"/>
- <item dataType="int" stringID="XST_6BIT_REGISTER" value="11"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="44">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="44"/>
- </item>
- </section>
- <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_FSMS" value="1"/>
- <item dataType="int" stringID="XST_RAMS" value="1"></item>
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2"></item>
- <item dataType="int" stringID="XST_REGISTERS" value="165">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="165"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="44">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="44"/>
- </item>
- </section>
- <section stringID="XST_FINAL_REGISTER_REPORT">
- <item dataType="int" stringID="XST_REGISTERS" value="192">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="192"/>
- </item>
- </section>
- <section stringID="XST_PARTITION_REPORT">
- <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- </section>
- <section stringID="XST_FINAL_REPORT">
- <section stringID="XST_FINAL_RESULTS">
- <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc"/>
- <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
- <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
- <item stringID="XST_KEEP_HIERARCHY" value="no"/>
- </section>
- <section stringID="XST_DESIGN_STATISTICS">
- <item stringID="XST_IOS" value="153"/>
- </section>
- <section stringID="XST_CELL_USAGE">
- <item dataType="int" stringID="XST_BELS" value="227">
- <item dataType="int" stringID="XST_GND" value="1"/>
- <item dataType="int" stringID="XST_INV" value="3"/>
- <item dataType="int" stringID="XST_LUT2" value="37"/>
- <item dataType="int" stringID="XST_LUT2L" value="1"/>
- <item dataType="int" stringID="XST_LUT3" value="86"/>
- <item dataType="int" stringID="XST_LUT3D" value="1"/>
- <item dataType="int" stringID="XST_LUT3L" value="3"/>
- <item dataType="int" stringID="XST_LUT4" value="34"/>
- <item dataType="int" stringID="XST_LUT4D" value="2"/>
- <item dataType="int" stringID="XST_MUXCY" value="10"/>
- <item dataType="int" stringID="XST_MUXF5" value="36"/>
- <item dataType="int" stringID="XST_VCC" value="1"/>
- <item dataType="int" stringID="XST_XORCY" value="12"/>
- </item>
- <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="192">
- <item dataType="int" stringID="XST_FD" value="4"/>
- <item dataType="int" stringID="XST_FDC" value="58"/>
- <item dataType="int" stringID="XST_FDCE" value="108"/>
- <item dataType="int" stringID="XST_FDP" value="10"/>
- <item dataType="int" stringID="XST_FDPE" value="5"/>
- </item>
- <item dataType="int" stringID="XST_RAMS" value="144">
- <item dataType="int" stringID="XST_RAM16X1D" value="144"/>
- </item>
- </section>
- </section>
- <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
- <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
- <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="188"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="192"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="455"/>
- <item dataType="int" stringID="XST_NUMBER_USED_AS_LOGIC" value="167"/>
- <item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="288"/>
- <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="153"/>
- <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
- </section>
- <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- <section stringID="XST_ERRORS_STATISTICS">
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="73"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
- </section>
- </application>
-
-</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt
deleted file mode 100644
index 44e31eb6c..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# Output products list for <fifo_xlnx_64x36_2clk>
-fifo_xlnx_64x36_2clk.ngc
-fifo_xlnx_64x36_2clk.v
-fifo_xlnx_64x36_2clk.veo
-fifo_xlnx_64x36_2clk.xco
-fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-fifo_xlnx_64x36_2clk_flist.txt
-fifo_xlnx_64x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt
deleted file mode 100644
index 7734c0087..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-The following files were generated for 'fifo_xlnx_64x36_2clk' in directory
-/home/matt/gnuradio.git/usrp2/fpga/coregen/:
-
-fifo_xlnx_64x36_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_64x36_2clk.v:
- Verilog wrapper file provided to support functional simulation.
- This file contains simulation model customization data that is
- passed to a parameterized simulation model for the core.
-
-fifo_xlnx_64x36_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_64x36_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
- Please see the core data sheet.
-
-fifo_xlnx_64x36_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-fifo_xlnx_64x36_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_64x36_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl
deleted file mode 100644
index ff5dfd3c2..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_64x36_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_64x36_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_64x36_2clk
-}
-# ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_64x36_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/pll_100_40_75.asy b/fpga/usrp2/coregen/pll_100_40_75.asy
deleted file mode 100644
index 9cd1ec359..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75.asy
+++ /dev/null
@@ -1,29 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 pll_100_40_75
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 0 432 32 432
-PIN 0 432 LEFT 36
-PINATTR PinName reset
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 176 576 176
-PIN 608 176 RIGHT 36
-PINATTR PinName clk_out2
-PINATTR Polarity OUT
-LINE Normal 608 272 576 272
-PIN 608 272 RIGHT 36
-PINATTR PinName clk_out3
-PINATTR Polarity OUT
-LINE Normal 608 976 576 976
-PIN 608 976 RIGHT 36
-PINATTR PinName locked
-PINATTR Polarity OUT
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75.gise b/fpga/usrp2/coregen/pll_100_40_75.gise
deleted file mode 100644
index c94415619..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75.gise
+++ /dev/null
@@ -1,31 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="pll_100_40_75.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="pll_100_40_75.asy" xil_pn:origination="imported"/>
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="pll_100_40_75.veo" xil_pn:origination="imported"/>
- </files>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/fpga/usrp2/coregen/pll_100_40_75.ucf b/fpga/usrp2/coregen/pll_100_40_75.ucf
deleted file mode 100755
index d8590fabb..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75.ucf
+++ /dev/null
@@ -1,71 +0,0 @@
-# file: pll_100_40_75.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;
-
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
-# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz;
-
-# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
-# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz;
-# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
-# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz;
-
-# FALSE PATH constraints
-PIN "RESET" TIG;
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75.v b/fpga/usrp2/coregen/pll_100_40_75.v
deleted file mode 100755
index b400ece75..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75.v
+++ /dev/null
@@ -1,158 +0,0 @@
-// file: pll_100_40_75.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-//----------------------------------------------------------------------------
-// User entered comments
-//----------------------------------------------------------------------------
-// None
-//
-//----------------------------------------------------------------------------
-// "Output Output Phase Duty Pk-to-Pk Phase"
-// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
-//----------------------------------------------------------------------------
-// CLK_OUT1___100.000______0.000______50.0______252.791____220.216
-// CLK_OUT2____40.000______0.000______50.0______309.264____220.216
-// CLK_OUT3____75.000______0.000______50.0______269.846____220.216
-//
-//----------------------------------------------------------------------------
-// "Input Clock Freq (MHz) Input Jitter (UI)"
-//----------------------------------------------------------------------------
-// __primary__________40.000____________0.010
-
-`timescale 1ps/1ps
-
-(* CORE_GENERATION_INFO = "pll_100_40_75,clk_wiz_v4_1,{component_name=pll_100_40_75,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
-module pll_100_40_75
- (// Clock in ports
- input CLK_IN1,
- // Clock out ports
- output CLK_OUT1,
- output CLK_OUT2,
- output CLK_OUT3,
- // Status and control signals
- input RESET,
- output LOCKED
- );
-
- // Input buffering
- //------------------------------------
- IBUFG clkin1_buf
- (.O (clkin1),
- .I (CLK_IN1));
-
-
- // Clocking primitive
- //------------------------------------
- // Instantiation of the PLL primitive
- // * Unused inputs are tied off
- // * Unused outputs are labeled unused
- wire [15:0] do_unused;
- wire drdy_unused;
- wire clkfbout;
- wire clkfbout_buf;
- wire clkout3_unused;
- wire clkout4_unused;
- wire clkout5_unused;
-
- PLL_BASE
- #(.BANDWIDTH ("OPTIMIZED"),
- .CLK_FEEDBACK ("CLKFBOUT"),
- .COMPENSATION ("SYSTEM_SYNCHRONOUS"),
- .DIVCLK_DIVIDE (1),
- .CLKFBOUT_MULT (15),
- .CLKFBOUT_PHASE (0.000),
- .CLKOUT0_DIVIDE (6),
- .CLKOUT0_PHASE (0.000),
- .CLKOUT0_DUTY_CYCLE (0.500),
- .CLKOUT1_DIVIDE (15),
- .CLKOUT1_PHASE (0.000),
- .CLKOUT1_DUTY_CYCLE (0.500),
- .CLKOUT2_DIVIDE (8),
- .CLKOUT2_PHASE (0.000),
- .CLKOUT2_DUTY_CYCLE (0.500),
- .CLKIN_PERIOD (25.000),
- .REF_JITTER (0.010))
- pll_base_inst
- // Output clocks
- (.CLKFBOUT (clkfbout),
- .CLKOUT0 (clkout0),
- .CLKOUT1 (clkout1),
- .CLKOUT2 (clkout2),
- .CLKOUT3 (clkout3_unused),
- .CLKOUT4 (clkout4_unused),
- .CLKOUT5 (clkout5_unused),
- // Status and control signals
- .LOCKED (LOCKED),
- .RST (RESET),
- // Input clock control
- .CLKFBIN (clkfbout_buf),
- .CLKIN (clkin1));
-
-
- // Output buffering
- //-----------------------------------
- BUFG clkf_buf
- (.O (clkfbout_buf),
- .I (clkfbout));
-
- BUFG clkout1_buf
- (.O (CLK_OUT1),
- .I (clkout0));
-
-
- BUFG clkout2_buf
- (.O (CLK_OUT2),
- .I (clkout1));
-
- BUFG clkout3_buf
- (.O (CLK_OUT3),
- .I (clkout2));
-
-
-
-endmodule
diff --git a/fpga/usrp2/coregen/pll_100_40_75.veo b/fpga/usrp2/coregen/pll_100_40_75.veo
deleted file mode 100755
index c6ebc5f5c..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75.veo
+++ /dev/null
@@ -1,82 +0,0 @@
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-//----------------------------------------------------------------------------
-// User entered comments
-//----------------------------------------------------------------------------
-// None
-//
-//----------------------------------------------------------------------------
-// "Output Output Phase Duty Pk-to-Pk Phase"
-// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
-//----------------------------------------------------------------------------
-// CLK_OUT1___100.000______0.000______50.0______252.791____220.216
-// CLK_OUT2____40.000______0.000______50.0______309.264____220.216
-// CLK_OUT3____75.000______0.000______50.0______269.846____220.216
-//
-//----------------------------------------------------------------------------
-// "Input Clock Freq (MHz) Input Jitter (UI)"
-//----------------------------------------------------------------------------
-// __primary__________40.000____________0.010
-
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-
- pll_100_40_75 instance_name
- (// Clock in ports
- .CLK_IN1(CLK_IN1), // IN
- // Clock out ports
- .CLK_OUT1(CLK_OUT1), // OUT
- .CLK_OUT2(CLK_OUT2), // OUT
- .CLK_OUT3(CLK_OUT3), // OUT
- // Status and control signals
- .RESET(RESET),// IN
- .LOCKED(LOCKED)); // OUT
-// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/fpga/usrp2/coregen/pll_100_40_75.xco b/fpga/usrp2/coregen/pll_100_40_75.xco
deleted file mode 100644
index a3a0eb4fb..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75.xco
+++ /dev/null
@@ -1,266 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.1
-# Date: Mon Jun 25 01:21:52 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# Generated from component: xilinx.com:ip:clk_wiz:3.5
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx75
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.5
-# END Select
-# BEGIN Parameters
-CSET calc_done=DONE
-CSET clk_in_sel_port=CLK_IN_SEL
-CSET clk_out1_port=CLK_OUT1
-CSET clk_out1_use_fine_ps_gui=false
-CSET clk_out2_port=CLK_OUT2
-CSET clk_out2_use_fine_ps_gui=false
-CSET clk_out3_port=CLK_OUT3
-CSET clk_out3_use_fine_ps_gui=false
-CSET clk_out4_port=CLK_OUT4
-CSET clk_out4_use_fine_ps_gui=false
-CSET clk_out5_port=CLK_OUT5
-CSET clk_out5_use_fine_ps_gui=false
-CSET clk_out6_port=CLK_OUT6
-CSET clk_out6_use_fine_ps_gui=false
-CSET clk_out7_port=CLK_OUT7
-CSET clk_out7_use_fine_ps_gui=false
-CSET clk_valid_port=CLK_VALID
-CSET clkfb_in_n_port=CLKFB_IN_N
-CSET clkfb_in_p_port=CLKFB_IN_P
-CSET clkfb_in_port=CLKFB_IN
-CSET clkfb_in_signaling=SINGLE
-CSET clkfb_out_n_port=CLKFB_OUT_N
-CSET clkfb_out_p_port=CLKFB_OUT_P
-CSET clkfb_out_port=CLKFB_OUT
-CSET clkfb_stopped_port=CLKFB_STOPPED
-CSET clkin1_jitter_ps=250.0
-CSET clkin1_ui_jitter=0.010
-CSET clkin2_jitter_ps=100.0
-CSET clkin2_ui_jitter=0.010
-CSET clkout1_drives=BUFG
-CSET clkout1_requested_duty_cycle=50.0
-CSET clkout1_requested_out_freq=100.000
-CSET clkout1_requested_phase=0.000
-CSET clkout2_drives=BUFG
-CSET clkout2_requested_duty_cycle=50.0
-CSET clkout2_requested_out_freq=40.000
-CSET clkout2_requested_phase=0.000
-CSET clkout2_used=true
-CSET clkout3_drives=BUFG
-CSET clkout3_requested_duty_cycle=50.0
-CSET clkout3_requested_out_freq=75.000
-CSET clkout3_requested_phase=0.000
-CSET clkout3_used=true
-CSET clkout4_drives=BUFG
-CSET clkout4_requested_duty_cycle=50.0
-CSET clkout4_requested_out_freq=75.000
-CSET clkout4_requested_phase=0.000
-CSET clkout4_used=false
-CSET clkout5_drives=BUFG
-CSET clkout5_requested_duty_cycle=50.0
-CSET clkout5_requested_out_freq=100.000
-CSET clkout5_requested_phase=0.000
-CSET clkout5_used=false
-CSET clkout6_drives=BUFG
-CSET clkout6_requested_duty_cycle=50.0
-CSET clkout6_requested_out_freq=100.000
-CSET clkout6_requested_phase=0.000
-CSET clkout6_used=false
-CSET clkout7_drives=BUFG
-CSET clkout7_requested_duty_cycle=50.0
-CSET clkout7_requested_out_freq=100.000
-CSET clkout7_requested_phase=0.000
-CSET clkout7_used=false
-CSET clock_mgr_type=AUTO
-CSET component_name=pll_100_40_75
-CSET daddr_port=DADDR
-CSET dclk_port=DCLK
-CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLKFX
-CSET dcm_clk_out2_port=CLK0
-CSET dcm_clk_out3_port=CLKFX
-CSET dcm_clk_out4_port=CLKFX
-CSET dcm_clk_out5_port=CLK0
-CSET dcm_clk_out6_port=CLK0
-CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=2
-CSET dcm_clkfx_multiply=5
-CSET dcm_clkgen_clk_out1_port=CLKFX
-CSET dcm_clkgen_clk_out2_port=CLKFX
-CSET dcm_clkgen_clk_out3_port=CLKFX
-CSET dcm_clkgen_clkfx_divide=1
-CSET dcm_clkgen_clkfx_md_max=0.000
-CSET dcm_clkgen_clkfx_multiply=4
-CSET dcm_clkgen_clkfxdv_divide=2
-CSET dcm_clkgen_clkin_period=10.000
-CSET dcm_clkgen_notes=None
-CSET dcm_clkgen_spread_spectrum=NONE
-CSET dcm_clkgen_startup_wait=false
-CSET dcm_clkin_divide_by_2=false
-CSET dcm_clkin_period=25.000
-CSET dcm_clkout_phase_shift=NONE
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
-CSET dcm_notes=None
-CSET dcm_phase_shift=0
-CSET dcm_pll_cascade=NONE
-CSET dcm_startup_wait=false
-CSET den_port=DEN
-CSET din_port=DIN
-CSET dout_port=DOUT
-CSET drdy_port=DRDY
-CSET dwe_port=DWE
-CSET feedback_source=FDBK_AUTO
-CSET in_freq_units=Units_MHz
-CSET in_jitter_units=Units_UI
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED
-CSET jitter_options=UI
-CSET jitter_sel=No_Jitter
-CSET locked_port=LOCKED
-CSET mmcm_bandwidth=OPTIMIZED
-CSET mmcm_clkfbout_mult_f=4.000
-CSET mmcm_clkfbout_phase=0.000
-CSET mmcm_clkfbout_use_fine_ps=false
-CSET mmcm_clkin1_period=10.000
-CSET mmcm_clkin2_period=10.000
-CSET mmcm_clkout0_divide_f=4.000
-CSET mmcm_clkout0_duty_cycle=0.500
-CSET mmcm_clkout0_phase=0.000
-CSET mmcm_clkout0_use_fine_ps=false
-CSET mmcm_clkout1_divide=1
-CSET mmcm_clkout1_duty_cycle=0.500
-CSET mmcm_clkout1_phase=0.000
-CSET mmcm_clkout1_use_fine_ps=false
-CSET mmcm_clkout2_divide=1
-CSET mmcm_clkout2_duty_cycle=0.500
-CSET mmcm_clkout2_phase=0.000
-CSET mmcm_clkout2_use_fine_ps=false
-CSET mmcm_clkout3_divide=1
-CSET mmcm_clkout3_duty_cycle=0.500
-CSET mmcm_clkout3_phase=0.000
-CSET mmcm_clkout3_use_fine_ps=false
-CSET mmcm_clkout4_cascade=false
-CSET mmcm_clkout4_divide=1
-CSET mmcm_clkout4_duty_cycle=0.500
-CSET mmcm_clkout4_phase=0.000
-CSET mmcm_clkout4_use_fine_ps=false
-CSET mmcm_clkout5_divide=1
-CSET mmcm_clkout5_duty_cycle=0.500
-CSET mmcm_clkout5_phase=0.000
-CSET mmcm_clkout5_use_fine_ps=false
-CSET mmcm_clkout6_divide=1
-CSET mmcm_clkout6_duty_cycle=0.500
-CSET mmcm_clkout6_phase=0.000
-CSET mmcm_clkout6_use_fine_ps=false
-CSET mmcm_clock_hold=false
-CSET mmcm_compensation=ZHOLD
-CSET mmcm_divclk_divide=1
-CSET mmcm_notes=None
-CSET mmcm_ref_jitter1=0.010
-CSET mmcm_ref_jitter2=0.010
-CSET mmcm_startup_wait=false
-CSET num_out_clks=3
-CSET override_dcm=false
-CSET override_dcm_clkgen=false
-CSET override_mmcm=false
-CSET override_pll=false
-CSET platform=lin
-CSET pll_bandwidth=OPTIMIZED
-CSET pll_clk_feedback=CLKFBOUT
-CSET pll_clkfbout_mult=15
-CSET pll_clkfbout_phase=0.000
-CSET pll_clkin_period=25.000
-CSET pll_clkout0_divide=6
-CSET pll_clkout0_duty_cycle=0.500
-CSET pll_clkout0_phase=0.000
-CSET pll_clkout1_divide=15
-CSET pll_clkout1_duty_cycle=0.500
-CSET pll_clkout1_phase=0.000
-CSET pll_clkout2_divide=8
-CSET pll_clkout2_duty_cycle=0.500
-CSET pll_clkout2_phase=0.000
-CSET pll_clkout3_divide=8
-CSET pll_clkout3_duty_cycle=0.500
-CSET pll_clkout3_phase=0.000
-CSET pll_clkout4_divide=1
-CSET pll_clkout4_duty_cycle=0.500
-CSET pll_clkout4_phase=0.000
-CSET pll_clkout5_divide=1
-CSET pll_clkout5_duty_cycle=0.500
-CSET pll_clkout5_phase=0.000
-CSET pll_compensation=SYSTEM_SYNCHRONOUS
-CSET pll_divclk_divide=1
-CSET pll_notes=None
-CSET pll_ref_jitter=0.010
-CSET power_down_port=POWER_DOWN
-CSET prim_in_freq=40.000
-CSET prim_in_jitter=0.010
-CSET prim_source=Single_ended_clock_capable_pin
-CSET primary_port=CLK_IN1
-CSET primitive=MMCM
-CSET primtype_sel=DCM_SP
-CSET psclk_port=PSCLK
-CSET psdone_port=PSDONE
-CSET psen_port=PSEN
-CSET psincdec_port=PSINCDEC
-CSET relative_inclk=REL_PRIMARY
-CSET reset_port=RESET
-CSET secondary_in_freq=100.000
-CSET secondary_in_jitter=0.010
-CSET secondary_port=CLK_IN2
-CSET secondary_source=Single_ended_clock_capable_pin
-CSET status_port=STATUS
-CSET summary_strings=empty
-CSET use_clk_valid=false
-CSET use_clkfb_stopped=false
-CSET use_dyn_phase_shift=false
-CSET use_dyn_reconfig=false
-CSET use_freeze=false
-CSET use_freq_synth=true
-CSET use_inclk_stopped=false
-CSET use_inclk_switchover=false
-CSET use_locked=true
-CSET use_max_i_jitter=false
-CSET use_min_o_jitter=false
-CSET use_min_power=false
-CSET use_phase_alignment=true
-CSET use_power_down=false
-CSET use_reset=true
-CSET use_spread_spectrum=false
-CSET use_status=false
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-12-28T09:11:49Z
-# END Extra information
-GENERATE
-# CRC: e73fbe14
diff --git a/fpga/usrp2/coregen/pll_100_40_75.xdc b/fpga/usrp2/coregen/pll_100_40_75.xdc
deleted file mode 100755
index 4cf03fee7..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75.xdc
+++ /dev/null
@@ -1,67 +0,0 @@
-# file: pll_100_40_75.xdc
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-create_clock -name CLK_IN1 -period 25.000 [get_ports CLK_IN1]
-set_propagated_clock CLK_IN1
-set_input_jitter CLK_IN1 0.25
-
-set_false_path -from [get_ports "RESET"]
-
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
diff --git a/fpga/usrp2/coregen/pll_100_40_75.xise b/fpga/usrp2/coregen/pll_100_40_75.xise
deleted file mode 100644
index 55dbd6ddb..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75.xise
+++ /dev/null
@@ -1,78 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="pll_100_40_75/example_design/pll_100_40_75_exdes.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation"/>
- </file>
- <file xil_pn:name="pll_100_40_75/example_design/pll_100_40_75_exdes.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- <file xil_pn:name="pll_100_40_75.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation"/>
- <association xil_pn:name="Implementation"/>
- <association xil_pn:name="PostMapSimulation"/>
- <association xil_pn:name="PostRouteSimulation"/>
- <association xil_pn:name="PostTranslateSimulation"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|pll_100_40_75_exdes" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="pll_100_40_75/example_design/pll_100_40_75_exdes.v" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pll_100_40_75_exdes" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="pll_100_40_75" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-06-24T18:22:22" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C844C83C3B3DDBC76B212B92126CFCA7" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt b/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt
deleted file mode 100644
index 4e06648c2..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt
+++ /dev/null
@@ -1,183 +0,0 @@
- Core name: Xilinx LogiCORE Clocking Wizard
- Version: 3.5
- Release: ISE 14.1
- Release Date: April 24, 2012
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
- 2.1 ISE
-3. Supported Devices
- 3.1 ISE
-4. Resolved Issues
- 4.1 ISE
-5. Known Issues
- 5.1 ISE
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5
-solution. For the latest core updates, see the product page at:
-
- http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
-
-................................................................................
-
-2. NEW FEATURES
-
-
- 2.1 ISE
-
- - ISE 14.1 software support
-
-................................................................................
-
-3. SUPPORTED DEVICES
-
-
- 3.1 ISE
-
-
- The following device families are supported by the core for this release.
-
- All 7 Series devices
-
-
- Zynq-7000 devices
- Zynq-7000
- Defense Grade Zynq-7000Q (XQ)
-
-
- All Virtex-6 devices
-
-
- All Spartan-6 devices
-
-
-................................................................................
-
-4. RESOLVED ISSUES
-
-
- 4.1 ISE
-
- - NA
-
-................................................................................
-
-5. KNOWN ISSUES
-
-
- 5.1 ISE
-
-
- The most recent information, including known issues, workarounds, and
- resolutions for this version is provided in the IP Release Notes Guide
- located at
-
- www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-
-
-................................................................................
-
-6. TECHNICAL SUPPORT
-
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-
-................................................................................
-
-7. CORE RELEASE HISTORY
-
-
-Date By Version Description
-================================================================================
-04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
-01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
-06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
-03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
-12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
-09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
-07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
-04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
-12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
-09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
-06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
-04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
-================================================================================
-
-................................................................................
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf
deleted file mode 100644
index 998385638..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf
+++ /dev/null
Binary files differ
diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt
deleted file mode 100644
index 4e06648c2..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt
+++ /dev/null
@@ -1,183 +0,0 @@
- Core name: Xilinx LogiCORE Clocking Wizard
- Version: 3.5
- Release: ISE 14.1
- Release Date: April 24, 2012
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
- 2.1 ISE
-3. Supported Devices
- 3.1 ISE
-4. Resolved Issues
- 4.1 ISE
-5. Known Issues
- 5.1 ISE
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5
-solution. For the latest core updates, see the product page at:
-
- http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
-
-................................................................................
-
-2. NEW FEATURES
-
-
- 2.1 ISE
-
- - ISE 14.1 software support
-
-................................................................................
-
-3. SUPPORTED DEVICES
-
-
- 3.1 ISE
-
-
- The following device families are supported by the core for this release.
-
- All 7 Series devices
-
-
- Zynq-7000 devices
- Zynq-7000
- Defense Grade Zynq-7000Q (XQ)
-
-
- All Virtex-6 devices
-
-
- All Spartan-6 devices
-
-
-................................................................................
-
-4. RESOLVED ISSUES
-
-
- 4.1 ISE
-
- - NA
-
-................................................................................
-
-5. KNOWN ISSUES
-
-
- 5.1 ISE
-
-
- The most recent information, including known issues, workarounds, and
- resolutions for this version is provided in the IP Release Notes Guide
- located at
-
- www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-
-
-................................................................................
-
-6. TECHNICAL SUPPORT
-
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-
-................................................................................
-
-7. CORE RELEASE HISTORY
-
-
-Date By Version Description
-================================================================================
-04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
-01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
-06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
-03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
-12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
-09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
-07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
-04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
-12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
-09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
-06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
-04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
-================================================================================
-
-................................................................................
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html
deleted file mode 100644
index 8dc6bb6ba..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html
+++ /dev/null
@@ -1,194 +0,0 @@
-<HTML>
-<HEAD>
-<TITLE>clk_wiz_v3_5_vinfo</TITLE>
-<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
-</HEAD>
-<BODY>
-<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
- Core name: Xilinx LogiCORE Clocking Wizard
- Version: 3.5
- Release: ISE 14.1
- Release Date: April 24, 2012
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
- 2.1 ISE
-3. Supported Devices
- 3.1 ISE
-4. Resolved Issues
- 4.1 ISE
-5. Known Issues
- 5.1 ISE
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
- <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
-
-For system requirements:
-
- <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
-
-This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5
-solution. For the latest core updates, see the product page at:
-
- <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
-
-................................................................................
-
-2. NEW FEATURES
-
-
- 2.1 ISE
-
- - ISE 14.1 software support
-
-................................................................................
-
-3. SUPPORTED DEVICES
-
-
- 3.1 ISE
-
-
- The following device families are supported by the core for this release.
-
- All 7 Series devices
-
-
- Zynq-7000 devices
- Zynq-7000
- Defense Grade Zynq-7000Q (XQ)
-
-
- All Virtex-6 devices
-
-
- All Spartan-6 devices
-
-
-................................................................................
-
-4. RESOLVED ISSUES
-
-
- 4.1 ISE
-
- - NA
-
-................................................................................
-
-5. KNOWN ISSUES
-
-
- 5.1 ISE
-
-
- The most recent information, including known issues, workarounds, and
- resolutions for this version is provided in the IP Release Notes Guide
- located at
-
- <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
-
-
-................................................................................
-
-6. TECHNICAL SUPPORT
-
-
-To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
-Questions are routed to a team with expertise using this product.
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-
-................................................................................
-
-7. CORE RELEASE HISTORY
-
-
-Date By Version Description
-================================================================================
-04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
-01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
-06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
-03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
-12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
-09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
-07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
-04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
-12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
-09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
-06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
-04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
-================================================================================
-
-................................................................................
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
-
-</FONT>
-</PRE>
-</BODY>
-</HTML>
diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
deleted file mode 100755
index 1892548b4..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
+++ /dev/null
@@ -1,72 +0,0 @@
-# file: pll_100_40_75_exdes.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;
-
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
-# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz;
-
-# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
-# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz;
-# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
-# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz;
-
-# FALSE PATH constraints
-PIN "COUNTER_RESET" TIG;
-PIN "RESET" TIG;
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v
deleted file mode 100755
index a79d6ab10..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v
+++ /dev/null
@@ -1,160 +0,0 @@
-// file: pll_100_40_75_exdes.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard example design
-//----------------------------------------------------------------------------
-// This example design instantiates the created clocking network, where each
-// output clock drives a counter. The high bit of each counter is ported.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-module pll_100_40_75_exdes
- #(
- parameter TCQ = 100
- )
- (// Clock in ports
- input CLK_IN1,
- // Reset that only drives logic in example design
- input COUNTER_RESET,
- output [3:1] CLK_OUT,
- // High bits of counters driven by clocks
- output [3:1] COUNT,
- // Status and control signals
- input RESET,
- output LOCKED
- );
-
- // Parameters for the counters
- //-------------------------------
- // Counter width
- localparam C_W = 16;
- // Number of counters
- localparam NUM_C = 3;
- genvar count_gen;
- // When the clock goes out of lock, reset the counters
- wire reset_int = !LOCKED || RESET || COUNTER_RESET;
-
- reg [NUM_C:1] rst_sync;
- reg [NUM_C:1] rst_sync_int;
- reg [NUM_C:1] rst_sync_int1;
- reg [NUM_C:1] rst_sync_int2;
-
-
- // Declare the clocks and counters
- wire [NUM_C:1] clk_int;
- wire [NUM_C:1] clk;
- reg [C_W-1:0] counter [NUM_C:1];
-
- // Instantiation of the clocking network
- //--------------------------------------
- pll_100_40_75 clknetwork
- (// Clock in ports
- .CLK_IN1 (CLK_IN1),
- // Clock out ports
- .CLK_OUT1 (clk_int[1]),
- .CLK_OUT2 (clk_int[2]),
- .CLK_OUT3 (clk_int[3]),
- // Status and control signals
- .RESET (RESET),
- .LOCKED (LOCKED));
-
- assign CLK_OUT = clk_int;
-
- // Connect the output clocks to the design
- //-----------------------------------------
- assign clk[1] = clk_int[1];
- assign clk[2] = clk_int[2];
- assign clk[3] = clk_int[3];
-
-
- // Reset synchronizer
- //-----------------------------------
- generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
- always @(posedge reset_int or posedge clk[count_gen]) begin
- if (reset_int) begin
- rst_sync[count_gen] <= 1'b1;
- rst_sync_int[count_gen]<= 1'b1;
- rst_sync_int1[count_gen]<= 1'b1;
- rst_sync_int2[count_gen]<= 1'b1;
- end
- else begin
- rst_sync[count_gen] <= 1'b0;
- rst_sync_int[count_gen] <= rst_sync[count_gen];
- rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
- rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
- end
- end
- end
- endgenerate
-
-
- // Output clock sampling
- //-----------------------------------
- generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
-
- always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
- if (rst_sync_int2[count_gen]) begin
- counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
- end else begin
- counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
- end
- end
- // alias the high bit of each counter to the corresponding
- // bit in the output bus
- assign COUNT[count_gen] = counter[count_gen][C_W-1];
- end
- endgenerate
-
-
-
-
-
-endmodule
diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc
deleted file mode 100755
index bd0f53e4e..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc
+++ /dev/null
@@ -1,69 +0,0 @@
-# file: pll_100_40_75_exdes.xdc
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-create_clock -name CLK_IN1 -period 25.000 [get_ports CLK_IN1]
-set_propagated_clock CLK_IN1
-set_input_jitter CLK_IN1 0.25
-
-# FALSE PATH constraint added on COUNTER_RESET
-set_false_path -from [get_ports "COUNTER_RESET"]
-set_false_path -from [get_ports "RESET"]
-
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat
deleted file mode 100755
index a362117a4..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat
+++ /dev/null
@@ -1,90 +0,0 @@
-REM file: implement.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM -----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the clocking wizard
-REM -----------------------------------------------------------------------------
-
-REM Clean up the results directory
-rmdir /S /Q results
-mkdir results
-
-REM Copy unisim_comp.v file to results directory
-copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
-
-REM Synthesize the Verilog Wrapper Files
-echo 'Synthesizing Clocking Wizard design with XST'
-xst -ifn xst.scr
-move pll_100_40_75_exdes.ngc results\
-
-REM Copy the constraints files generated by Coregen
-echo 'Copying files from constraints directory to results directory'
-copy ..\example_design\pll_100_40_75_exdes.ucf results\
-
-cd results
-
-echo 'Running ngdbuild'
-ngdbuild -uc pll_100_40_75_exdes.ucf pll_100_40_75_exdes
-
-echo 'Running map'
-map -timing -pr b pll_100_40_75_exdes -o mapped.ncd
-
-echo 'Running par'
-par -w mapped.ncd routed mapped.pcf
-
-echo 'Running trce'
-trce -e 10 routed -o routed mapped.pcf
-
-echo 'Running design through bitgen'
-bitgen -w routed
-
-echo 'Running netgen to create gate level model for the clocking wizard example design'
-netgen -ofmt verilog -sim -sdf_anno false -tm pll_100_40_75_exdes -w routed.ncd routed.v
-cd ..
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh
deleted file mode 100755
index e3ff2ce97..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh
+++ /dev/null
@@ -1,91 +0,0 @@
-#!/bin/sh
-# file: implement.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the clocking wizard
-#-----------------------------------------------------------------------------
-
-# Clean up the results directory
-rm -rf results
-mkdir results
-
-# Copy unisim_comp.v file to results directory
-cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
-
-# Synthesize the Verilog Wrapper Files
-echo 'Synthesizing Clocking Wizard design with XST'
-xst -ifn xst.scr
-mv pll_100_40_75_exdes.ngc results/
-
-# Copy the constraints files generated by Coregen
-echo 'Copying files from constraints directory to results directory'
-cp ../example_design/pll_100_40_75_exdes.ucf results/
-
-cd results
-
-echo 'Running ngdbuild'
-ngdbuild -uc pll_100_40_75_exdes.ucf pll_100_40_75_exdes
-
-echo 'Running map'
-map -timing pll_100_40_75_exdes -o mapped.ncd
-
-echo 'Running par'
-par -w mapped.ncd routed mapped.pcf
-
-echo 'Running trce'
-trce -e 10 routed -o routed mapped.pcf
-
-echo 'Running design through bitgen'
-bitgen -w routed
-
-echo 'Running netgen to create gate level model for the clocking wizard example design'
-netgen -ofmt verilog -sim -sdf_anno false -tm pll_100_40_75_exdes -w routed.ncd routed.v
-
-cd ..
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat
deleted file mode 100755
index 8ac771810..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat
+++ /dev/null
@@ -1,58 +0,0 @@
-REM file: planAhead_ise.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM-----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the clocking wizard
-REM-----------------------------------------------------------------------------
-
-del \f results
-mkdir results
-cd results
-
-planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh
deleted file mode 100755
index 6c8c837d3..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh
+++ /dev/null
@@ -1,59 +0,0 @@
-#!/bin/sh
-# file: planAhead_ise.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the clocking wizard
-#-----------------------------------------------------------------------------
-
-rm -rf results
-mkdir results
-cd results
-
-planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl
deleted file mode 100755
index f4e6c57ae..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl
+++ /dev/null
@@ -1,78 +0,0 @@
-# file: planAhead_ise.tcl
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-set projDir [file dirname [info script]]
-set projName pll_100_40_75
-set topName pll_100_40_75_exdes
-set device xc6slx75csg484-3
-
-create_project $projName $projDir/results/$projName -part $device
-
-set_property design_mode RTL [get_filesets sources_1]
-
-## Source files
-#set verilogSources [glob $srcDir/*.v]
-import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/pll_100_40_75_exdes.v
-import_files -fileset [get_filesets sources_1] -force -norecurse ../../../pll_100_40_75.v
-
-
-#UCF file
-import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/pll_100_40_75_exdes.ucf
-
-set_property top $topName [get_property srcset [current_run]]
-
-launch_runs -runs synth_1
-wait_on_run synth_1
-
-set_property add_step Bitgen [get_runs impl_1]
-launch_runs -runs impl_1
-wait_on_run impl_1
-
-
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat
deleted file mode 100755
index 42273f5d4..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat
+++ /dev/null
@@ -1,58 +0,0 @@
-REM file: planAhead_rdn.sh
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM-----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the XADC wizard
-REM-----------------------------------------------------------------------------
-
-del \f results
-mkdir results
-cd results
-
-planAhead -mode batch -source ..\planAhead_rdn.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh
deleted file mode 100755
index f4c14729e..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/bin/sh
-# file: planAhead_rdn.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the XADC wizard
-#-----------------------------------------------------------------------------
-rm -rf results
-mkdir results
-cd results
-planAhead -mode batch -source ../planAhead_rdn.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl
deleted file mode 100755
index 56f9c65af..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl
+++ /dev/null
@@ -1,69 +0,0 @@
-# file : planAhead_rdn.tcl
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-set device xc6slx75csg484-3
-set projName pll_100_40_75
-set design pll_100_40_75
-set projDir [file dirname [info script]]
-create_project $projName $projDir/results/$projName -part $device -force
-set_property design_mode RTL [current_fileset -srcset]
-set top_module pll_100_40_75_exdes
-set_property top pll_100_40_75_exdes [get_property srcset [current_run]]
-add_files -norecurse {../../../pll_100_40_75.v}
-add_files -norecurse {../../example_design/pll_100_40_75_exdes.v}
-import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/pll_100_40_75_exdes.xdc}
-synth_design
-opt_design
-place_design
-route_design
-write_sdf -rename_top_module pll_100_40_75_exdes -file routed.sdf
-write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module pll_100_40_75_exdes -file routed.v
-report_timing -nworst 30 -path_type full -file routed.twr
-report_drc -file report.drc
-write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj
deleted file mode 100755
index 8409c83dd..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj
+++ /dev/null
@@ -1,2 +0,0 @@
-verilog work ../../pll_100_40_75.v
-verilog work ../example_design/pll_100_40_75_exdes.v
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr
deleted file mode 100755
index af176e2e4..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-run
--ifmt MIXED
--top pll_100_40_75_exdes
--p xc6slx75-csg484-3
--ifn xst.prj
--ofn pll_100_40_75_exdes
--keep_hierarchy soft
--equivalent_register_removal no
--max_fanout 65535
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl
deleted file mode 100755
index 6692a790e..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl
+++ /dev/null
@@ -1,8 +0,0 @@
-# file: simcmds.tcl
-
-# create the simulation script
-vcd dumpfile isim.vcd
-vcd dumpvars -m /pll_100_40_75_tb -l 0
-wave add /
-run 50000ns
-quit
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat
deleted file mode 100755
index 783ddc0e3..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat
+++ /dev/null
@@ -1,59 +0,0 @@
-REM file: simulate_isim.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-vlogcomp -work work %XILINX%\verilog\src\glbl.v
-vlogcomp -work work ..\..\..\pll_100_40_75.v
-vlogcomp -work work ..\..\example_design\pll_100_40_75_exdes.v
-vlogcomp -work work ..\pll_100_40_75_tb.v
-
-REM compile the project
-fuse work.pll_100_40_75_tb work.glbl -L unisims_ver -o pll_100_40_75_isim.exe
-
-REM run the simulation script
-.\pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh
deleted file mode 100755
index cb197ed97..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh
+++ /dev/null
@@ -1,61 +0,0 @@
-# file: simulate_isim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# lin
-# create the project
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work ../../../pll_100_40_75.v
-vlogcomp -work work ../../example_design/pll_100_40_75_exdes.v
-vlogcomp -work work ../pll_100_40_75_tb.v
-
-# compile the project
-fuse work.pll_100_40_75_tb work.glbl -L unisims_ver -o pll_100_40_75_isim.exe
-
-# run the simulation script
-./pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat
deleted file mode 100755
index 756d94e7a..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat
+++ /dev/null
@@ -1,61 +0,0 @@
-REM file: simulate_mti.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM set up the working directory
-vlib work
-
-REM compile all of the files
-vlog -work work %XILINX%\verilog\src\glbl.v
-vlog -work work ..\..\..\pll_100_40_75.v
-vlog -work work ..\..\example_design\pll_100_40_75_exdes.v
-vlog -work work ..\pll_100_40_75_tb.v
-
-REM run the simulation
-vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.pll_100_40_75_tb work.glbl
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do
deleted file mode 100755
index c74e73aa5..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do
+++ /dev/null
@@ -1,65 +0,0 @@
-# file: simulate_mti.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $env(XILINX)/verilog/src/glbl.v
-vlog -work work ../../../pll_100_40_75.v
-vlog -work work ../../example_design/pll_100_40_75_exdes.v
-vlog -work work ../pll_100_40_75_tb.v
-
-# run the simulation
-vsim -t ps -voptargs="+acc" -L unisims_ver work.pll_100_40_75_tb work.glbl
-do wave.do
-log pll_100_40_75_tb/dut/counter
-log -r /*
-run 50000ns
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh
deleted file mode 100755
index a49ca05c6..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh
+++ /dev/null
@@ -1,61 +0,0 @@
-#/bin/sh
-# file: simulate_mti.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $XILINX/verilog/src/glbl.v
-vlog -work work ../../../pll_100_40_75.v
-vlog -work work ../../example_design/pll_100_40_75_exdes.v
-vlog -work work ../pll_100_40_75_tb.v
-
-# run the simulation
-vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.pll_100_40_75_tb work.glbl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh
deleted file mode 100755
index 5978c8eb7..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh
+++ /dev/null
@@ -1,62 +0,0 @@
-#/bin/sh
-# file: simulate_ncsim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-mkdir work
-
-# compile all of the files
-ncvlog -work work ${XILINX}/verilog/src/glbl.v
-ncvlog -work work ../../../pll_100_40_75.v
-ncvlog -work work ../../example_design/pll_100_40_75_exdes.v
-ncvlog -work work ../pll_100_40_75_tb.v
-
-# elaborate and run the simulation
-ncelab -work work -access +wc work.pll_100_40_75_tb work.glbl
-ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.pll_100_40_75_tb
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh
deleted file mode 100755
index bebd99d7d..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh
+++ /dev/null
@@ -1,72 +0,0 @@
-#!/bin/sh
-# file: simulate_vcs.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# remove old files
-rm -rf simv* csrc DVEfiles AN.DB
-
-# compile all of the files
-# Note that -sverilog is not strictly required- You can
-# remove the -sverilog if you change the type of the
-# localparam for the periods in the testbench file to
-# [63:0] from time
-vlogan -sverilog \
- ${XILINX}/verilog/src/glbl.v \
- ../../../pll_100_40_75.v \
- ../../example_design/pll_100_40_75_exdes.v \
- ../pll_100_40_75_tb.v
-
-# prepare the simulation
-vcs +vcs+lic+wait -debug pll_100_40_75_tb glbl
-
-# run the simulation
-./simv -ucli -i ucli_commands.key
-
-# launch the viewer
-dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key
deleted file mode 100755
index b56d68a2d..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key
+++ /dev/null
@@ -1,5 +0,0 @@
-call {$vcdpluson}
-call {$vcdplusmemon(pll_100_40_75_tb.dut.counter)}
-run
-call {$vcdplusclose}
-quit
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl
deleted file mode 100755
index 19b1ea0f5..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-gui_open_window Wave
-gui_sg_create pll_100_40_75_group
-gui_list_add_group -id Wave.1 {pll_100_40_75_group}
-gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.test_phase}
-gui_set_radix -radix {ascii} -signals {pll_100_40_75_tb.test_phase}
-gui_sg_addsignal -group pll_100_40_75_group {{Input_clocks}} -divider
-gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.CLK_IN1}
-gui_sg_addsignal -group pll_100_40_75_group {{Output_clocks}} -divider
-gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.dut.clk}
-gui_list_expand -id Wave.1 pll_100_40_75_tb.dut.clk
-gui_sg_addsignal -group pll_100_40_75_group {{Status_control}} -divider
-gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.RESET}
-gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.LOCKED}
-gui_sg_addsignal -group pll_100_40_75_group {{Counters}} -divider
-gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.COUNT}
-gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.dut.counter}
-gui_list_expand -id Wave.1 pll_100_40_75_tb.dut.counter
-gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do
deleted file mode 100755
index 4178de1c7..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do
+++ /dev/null
@@ -1,60 +0,0 @@
-# file: wave.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-add wave -noupdate -format Literal -radix ascii /pll_100_40_75_tb/test_phase
-add wave -noupdate -divider {Input clocks}
-add wave -noupdate -format Logic /pll_100_40_75_tb/CLK_IN1
-add wave -noupdate -divider {Output clocks}
-add wave -noupdate -format Literal -expand /pll_100_40_75_tb/dut/clk
-add wave -noupdate -divider Status/control
-add wave -noupdate -format Logic /pll_100_40_75_tb/RESET
-add wave -noupdate -format Logic /pll_100_40_75_tb/LOCKED
-add wave -noupdate -divider Counters
-add wave -noupdate -format Literal -radix hexadecimal /pll_100_40_75_tb/COUNT
-add wave -noupdate -format Literal -radix hexadecimal -expand /pll_100_40_75_tb/dut/counter
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv
deleted file mode 100755
index 57e72bdec..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv
+++ /dev/null
@@ -1,119 +0,0 @@
-# file: wave.sv
-#
-# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# Get the windows set up
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
- window geometry "Design Browser 1" 1054x819+536+322
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set \
- -scope nc::pll_100_40_75_tb
-browser yview see nc::pll_100_40_75_tb
-browser timecontrol set -lock 0
-
-if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
- window geometry "Waveform 1" 1010x600+0+541
-}
-window target "Waveform 1" on
-waveform using {Waveform 1}
-waveform sidebar visibility partial
-waveform set \
- -primarycursor TimeA \
- -signalnames name \
- -signalwidth 175 \
- -units ns \
- -valuewidth 75
-cursor set -using TimeA -time 0
-waveform baseline set -time 0
-waveform xview limits 0 20000n
-
-#
-# Define signal groups
-#
-catch {group new -name {Output clocks} -overlay 0}
-catch {group new -name {Status/control} -overlay 0}
-catch {group new -name {Counters} -overlay 0}
-
-set id [waveform add -signals [list {nc::pll_100_40_75_tb.CLK_IN1}]]
-
-group using {Output clocks}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {pll_100_40_75_tb.dut.clk[1]} \
- {pll_100_40_75_tb.dut.clk[2]} \ {pll_100_40_75_tb.dut.clk[3]}
-group using {Counters}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {pll_100_40_75_tb.dut.counter[1]} \
- {pll_100_40_75_tb.dut.counter[2]} \ {pll_100_40_75_tb.dut.counter[3]}
-group using {Status/control}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {nc::pll_100_40_75_tb.RESET} {nc::pll_100_40_75_tb.LOCKED}
-
-
-set id [waveform add -signals [list {nc::pll_100_40_75_tb.COUNT} ]]
-
-set id [waveform add -signals [list {nc::pll_100_40_75_tb.test_phase} ]]
-waveform format $id -radix %a
-
-set groupId [waveform add -groups {{Input clocks}}]
-set groupId [waveform add -groups {{Output clocks}}]
-set groupId [waveform add -groups {{Status/control}}]
-set groupId [waveform add -groups {{Counters}}]
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v b/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v
deleted file mode 100755
index fe800f0cc..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v
+++ /dev/null
@@ -1,143 +0,0 @@
-// file: pll_100_40_75_tb.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard demonstration testbench
-//----------------------------------------------------------------------------
-// This demonstration testbench instantiates the example design for the
-// clocking wizard. Input clocks are toggled, which cause the clocking
-// network to lock and the counters to increment.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-`define wait_lock @(posedge LOCKED)
-
-module pll_100_40_75_tb ();
-
- // Clock to Q delay of 100ps
- localparam TCQ = 100;
-
-
- // timescale is 1ps/1ps
- localparam ONE_NS = 1000;
- localparam PHASE_ERR_MARGIN = 100; // 100ps
- // how many cycles to run
- localparam COUNT_PHASE = 1024;
- // we'll be using the period in many locations
- localparam time PER1 = 25.000*ONE_NS;
- localparam time PER1_1 = PER1/2;
- localparam time PER1_2 = PER1 - PER1/2;
-
- // Declare the input clock signals
- reg CLK_IN1 = 1;
-
- // The high bits of the sampling counters
- wire [3:1] COUNT;
- // Status and control signals
- reg RESET = 0;
- wire LOCKED;
- reg COUNTER_RESET = 0;
-wire [3:1] CLK_OUT;
-//Freq Check using the M & D values setting and actual Frequency generated
-
-
- // Input clock generation
- //------------------------------------
- always begin
- CLK_IN1 = #PER1_1 ~CLK_IN1;
- CLK_IN1 = #PER1_2 ~CLK_IN1;
- end
-
- // Test sequence
- reg [15*8-1:0] test_phase = "";
- initial begin
- // Set up any display statements using time to be readable
- $timeformat(-12, 2, "ps", 10);
- COUNTER_RESET = 0;
- test_phase = "reset";
- RESET = 1;
- #(PER1*6);
- RESET = 0;
- test_phase = "wait lock";
- `wait_lock;
- #(PER1*6);
- COUNTER_RESET = 1;
- #(PER1*20)
- COUNTER_RESET = 0;
-
- test_phase = "counting";
- #(PER1*COUNT_PHASE);
-
- $display("SIMULATION PASSED");
- $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
- $finish;
- end
-
- // Instantiation of the example design containing the clock
- // network and sampling counters
- //---------------------------------------------------------
- pll_100_40_75_exdes
- #(
- .TCQ (TCQ)
- ) dut
- (// Clock in ports
- .CLK_IN1 (CLK_IN1),
- // Reset for logic in example design
- .COUNTER_RESET (COUNTER_RESET),
- .CLK_OUT (CLK_OUT),
- // High bits of the counters
- .COUNT (COUNT),
- // Status and control signals
- .RESET (RESET),
- .LOCKED (LOCKED));
-
-// Freq Check
-
-endmodule
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v
deleted file mode 100755
index 0e6be6e9d..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v
+++ /dev/null
@@ -1,157 +0,0 @@
-// file: pll_100_40_75_tb.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard demonstration testbench
-//----------------------------------------------------------------------------
-// This demonstration testbench instantiates the example design for the
-// clocking wizard. Input clocks are toggled, which cause the clocking
-// network to lock and the counters to increment.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-`define wait_lock @(posedge LOCKED)
-
-module pll_100_40_75_tb ();
-
- // Clock to Q delay of 100ps
- localparam TCQ = 100;
-
-
- // timescale is 1ps/1ps
- localparam ONE_NS = 1000;
- localparam PHASE_ERR_MARGIN = 100; // 100ps
- // how many cycles to run
- localparam COUNT_PHASE = 1024;
- // we'll be using the period in many locations
- localparam time PER1 = 25.000*ONE_NS;
- localparam time PER1_1 = PER1/2;
- localparam time PER1_2 = PER1 - PER1/2;
-
- // Declare the input clock signals
- reg CLK_IN1 = 1;
-
- // The high bits of the sampling counters
- wire [3:1] COUNT;
- // Status and control signals
- reg RESET = 0;
- wire LOCKED;
- reg COUNTER_RESET = 0;
-wire [3:1] CLK_OUT;
-//Freq Check using the M & D values setting and actual Frequency generated
-
- reg [13:0] timeout_counter = 14'b00000000000000;
-
- // Input clock generation
- //------------------------------------
- always begin
- CLK_IN1 = #PER1_1 ~CLK_IN1;
- CLK_IN1 = #PER1_2 ~CLK_IN1;
- end
-
- // Test sequence
- reg [15*8-1:0] test_phase = "";
- initial begin
- // Set up any display statements using time to be readable
- $timeformat(-12, 2, "ps", 10);
- $display ("Timing checks are not valid");
- COUNTER_RESET = 0;
- test_phase = "reset";
- RESET = 1;
- #(PER1*6);
- RESET = 0;
- test_phase = "wait lock";
- `wait_lock;
- #(PER1*6);
- COUNTER_RESET = 1;
- #(PER1*19.5)
- COUNTER_RESET = 0;
- #(PER1*1)
- $display ("Timing checks are valid");
- test_phase = "counting";
- #(PER1*COUNT_PHASE);
-
- $display("SIMULATION PASSED");
- $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
- $finish;
- end
-
-
- always@(posedge CLK_IN1) begin
- timeout_counter <= timeout_counter + 1'b1;
- if (timeout_counter == 14'b10000000000000) begin
- if (LOCKED != 1'b1) begin
- $display("ERROR : NO LOCK signal");
- $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
- $finish;
- end
- end
- end
-
- // Instantiation of the example design containing the clock
- // network and sampling counters
- //---------------------------------------------------------
- pll_100_40_75_exdes
- dut
- (// Clock in ports
- .CLK_IN1 (CLK_IN1),
- // Reset for logic in example design
- .COUNTER_RESET (COUNTER_RESET),
- .CLK_OUT (CLK_OUT),
- // High bits of the counters
- .COUNT (COUNT),
- // Status and control signals
- .RESET (RESET),
- .LOCKED (LOCKED));
-
-
-// Freq Check
-
-endmodule
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file
deleted file mode 100755
index 61dacfed8..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file
+++ /dev/null
@@ -1,2 +0,0 @@
-COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
-SCOPE = pll_100_40_75_tb.dut;
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl
deleted file mode 100755
index 857329884..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl
+++ /dev/null
@@ -1,9 +0,0 @@
-# file: simcmds.tcl
-
-# create the simulation script
-vcd dumpfile isim.vcd
-vcd dumpvars -m /pll_100_40_75_tb -l 0
-wave add /
-run 50000ns
-quit
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh
deleted file mode 100755
index e3b06d7c5..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh
+++ /dev/null
@@ -1,62 +0,0 @@
-# file: simulate_isim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# create the project
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work ../../implement/results/routed.v
-vlogcomp -work work pll_100_40_75_tb.v
-
-# compile the project
-fuse work.pll_100_40_75_tb work.glbl -L secureip -L simprims_ver -o pll_100_40_75_isim.exe
-
-# run the simulation script
-./pll_100_40_75_isim.exe -tclbatch simcmds.tcl -sdfmax /pll_100_40_75_tb/dut=../../implement/results/routed.sdf
-
-# run the simulation script
-#./pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat
deleted file mode 100755
index 7e5890086..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat
+++ /dev/null
@@ -1,59 +0,0 @@
-REM file: simulate_mti.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-# set up the working directory
-set work work
-vlib work
-
-REM compile all of the files
-vlog -work work %XILINX%\verilog\src\glbl.v
-vlog -work work ..\..\implement\results\routed.v
-vlog -work work pll_100_40_75_tb.v
-
-REM run the simulation
-vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do
deleted file mode 100755
index 03f8a3965..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do
+++ /dev/null
@@ -1,65 +0,0 @@
-# file: simulate_mti.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $env(XILINX)/verilog/src/glbl.v
-vlog -work work ../../implement/results/routed.v
-vlog -work work pll_100_40_75_tb.v
-
-# run the simulation
-vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl
-#do wave.do
-#log -r /*
-run 50000ns
-
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh
deleted file mode 100755
index 055768aa8..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh
+++ /dev/null
@@ -1,61 +0,0 @@
-#/bin/sh
-# file: simulate_mti.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $XILINX/verilog/src/glbl.v
-vlog -work work ../../implement/results/routed.v
-vlog -work work pll_100_40_75_tb.v
-
-# run the simulation
-vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh
deleted file mode 100755
index aa3a2b441..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh
+++ /dev/null
@@ -1,64 +0,0 @@
-#!/bin/sh
-# file: simulate_ncsim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-mkdir work
-
-# compile all of the files
-ncvlog -work work ${XILINX}/verilog/src/glbl.v
-ncvlog -work work ../../implement/results/routed.v
-ncvlog -work work pll_100_40_75_tb.v
-
-# elaborate and run the simulation
-ncsdfc ../../implement/results/routed.sdf
-
-ncelab -work work -access +wc -pulse_r 10 -nonotifier work.pll_100_40_75_tb work.glbl -sdf_cmd_file sdf_cmd_file
-ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.pll_100_40_75_tb
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh
deleted file mode 100755
index 3cc21dd69..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh
+++ /dev/null
@@ -1,72 +0,0 @@
-#!/bin/sh
-# file: simulate_vcs.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# remove old files
-rm -rf simv* csrc DVEfiles AN.DB
-
-# compile all of the files
-# Note that -sverilog is not strictly required- You can
-# remove the -sverilog if you change the type of the
-# localparam for the periods in the testbench file to
-# [63:0] from time
- vlogan -sverilog \
- pll_100_40_75_tb.v \
- ../../implement/results/routed.v
-
-
-# prepare the simulation
-vcs -sdf max:pll_100_40_75_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
- +libext+.v -debug pll_100_40_75_tb.v ../../implement/results/routed.v
-
-# run the simulation
-./simv -ucli -i ucli_commands.key
-
-# launch the viewer
-#dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key
deleted file mode 100755
index 0548d1733..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key
+++ /dev/null
@@ -1,5 +0,0 @@
-
-call {$vcdpluson}
-run 50000ns
-call {$vcdplusclose}
-quit
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl
deleted file mode 100755
index 1438f6bed..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl
+++ /dev/null
@@ -1 +0,0 @@
-gui_open_window Wave
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do
deleted file mode 100755
index fe9b59354..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do
+++ /dev/null
@@ -1,72 +0,0 @@
-# file: wave.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /pll_100_40_75_tb/CLK_IN1
-add wave -noupdate /pll_100_40_75_tb/COUNT
-add wave -noupdate /pll_100_40_75_tb/LOCKED
-add wave -noupdate /pll_100_40_75_tb/RESET
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
-configure wave -namecolwidth 238
-configure wave -valuecolwidth 107
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ps
-update
-WaveRestoreZoom {0 ps} {74848022 ps}
diff --git a/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf b/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf
deleted file mode 100644
index ddff6a6e9..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf
+++ /dev/null
@@ -1,73 +0,0 @@
-# file: pll_100_40_75_exdes.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;
-
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
-# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz;
-
-# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
-# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz;
-# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
-# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz;
-
-# FALSE PATH constraints
-PIN "COUNTER_RESET" TIG;
-PIN "RESET" TIG;
-
-
diff --git a/fpga/usrp2/coregen/pll_100_40_75_flist.txt b/fpga/usrp2/coregen/pll_100_40_75_flist.txt
deleted file mode 100644
index 04c7f882d..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75_flist.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-# Output products list for <pll_100_40_75>
-_xmsgs/pn_parser.xmsgs
-pll_100_40_75/clk_wiz_v3_5_readme.txt
-pll_100_40_75/doc/clk_wiz_gsg521.pdf
-pll_100_40_75/doc/clk_wiz_v3_5_readme.txt
-pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html
-pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
-pll_100_40_75/example_design/pll_100_40_75_exdes.v
-pll_100_40_75/example_design/pll_100_40_75_exdes.xdc
-pll_100_40_75/implement/implement.bat
-pll_100_40_75/implement/implement.sh
-pll_100_40_75/implement/planAhead_ise.bat
-pll_100_40_75/implement/planAhead_ise.sh
-pll_100_40_75/implement/planAhead_ise.tcl
-pll_100_40_75/implement/planAhead_rdn.bat
-pll_100_40_75/implement/planAhead_rdn.sh
-pll_100_40_75/implement/planAhead_rdn.tcl
-pll_100_40_75/implement/xst.prj
-pll_100_40_75/implement/xst.scr
-pll_100_40_75/simulation/functional/simcmds.tcl
-pll_100_40_75/simulation/functional/simulate_isim.bat
-pll_100_40_75/simulation/functional/simulate_isim.sh
-pll_100_40_75/simulation/functional/simulate_mti.bat
-pll_100_40_75/simulation/functional/simulate_mti.do
-pll_100_40_75/simulation/functional/simulate_mti.sh
-pll_100_40_75/simulation/functional/simulate_ncsim.sh
-pll_100_40_75/simulation/functional/simulate_vcs.sh
-pll_100_40_75/simulation/functional/ucli_commands.key
-pll_100_40_75/simulation/functional/vcs_session.tcl
-pll_100_40_75/simulation/functional/wave.do
-pll_100_40_75/simulation/functional/wave.sv
-pll_100_40_75/simulation/pll_100_40_75_tb.v
-pll_100_40_75/simulation/timing/pll_100_40_75_tb.v
-pll_100_40_75/simulation/timing/sdf_cmd_file
-pll_100_40_75/simulation/timing/simcmds.tcl
-pll_100_40_75/simulation/timing/simulate_isim.sh
-pll_100_40_75/simulation/timing/simulate_mti.bat
-pll_100_40_75/simulation/timing/simulate_mti.do
-pll_100_40_75/simulation/timing/simulate_mti.sh
-pll_100_40_75/simulation/timing/simulate_ncsim.sh
-pll_100_40_75/simulation/timing/simulate_vcs.sh
-pll_100_40_75/simulation/timing/ucli_commands.key
-pll_100_40_75/simulation/timing/vcs_session.tcl
-pll_100_40_75/simulation/timing/wave.do
-pll_100_40_75.asy
-pll_100_40_75.gise
-pll_100_40_75.ucf
-pll_100_40_75.v
-pll_100_40_75.veo
-pll_100_40_75.xco
-pll_100_40_75.xdc
-pll_100_40_75.xise
-pll_100_40_75_flist.txt
-pll_100_40_75_xmdf.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl b/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl
deleted file mode 100755
index 18eee6e1a..000000000
--- a/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl
+++ /dev/null
@@ -1,144 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide pll_100_40_75_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::pll_100_40_75_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::pll_100_40_75_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name pll_100_40_75
-}
-# ::pll_100_40_75_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::pll_100_40_75_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/clk_wiz_readme.txt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/doc/clk_wiz_ds709.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/doc/clk_wiz_gsg521.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/example_design/pll_100_40_75_exdes.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/implement.bat
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/implement.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/xst.prj
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/xst.scr
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/pll_100_40_75_tb.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simcmds.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_isim.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_mti.do
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_ncsim.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_vcs.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/ucli_commands.key
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/vcs_session.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/wave.do
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/wave.sv
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.ejp
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module pll_100_40_75
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 05:45:04 +0000