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-rw-r--r--fpga/usrp2/coregen/coregen_s6.cgp22
1 files changed, 0 insertions, 22 deletions
diff --git a/fpga/usrp2/coregen/coregen_s6.cgp b/fpga/usrp2/coregen/coregen_s6.cgp
deleted file mode 100644
index 1abd1b021..000000000
--- a/fpga/usrp2/coregen/coregen_s6.cgp
+++ /dev/null
@@ -1,22 +0,0 @@
-# Date: Fri May 4 20:42:23 2012
-
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx75
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-SET workingdirectory = ./tmp/
-
-# CRC: f7d4ca66