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| author | Josh Blum <josh@joshknows.com> | 2010-10-14 16:55:56 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-10-14 16:55:56 -0700 |
| commit | 26b7de0ac0cd64946582b2d52ab0bb3555156039 (patch) | |
| tree | 5dc670eaaab60bf2bda90d905210bc9432cecea3 /fpga/usrp2/coregen/coregen.cgp | |
| parent | 71e1763332141603e9edba097fd19b00e9a76ab8 (diff) | |
| parent | ee03f1d4acf5c7d3359c86baba5085660d63ebae (diff) | |
| download | uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.tar.gz uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.tar.bz2 uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.zip | |
Merge branch 'flow_control' into flow_ctrl
Diffstat (limited to 'fpga/usrp2/coregen/coregen.cgp')
| -rw-r--r-- | fpga/usrp2/coregen/coregen.cgp | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp index 810d64dac..4c9201aff 100644 --- a/fpga/usrp2/coregen/coregen.cgp +++ b/fpga/usrp2/coregen/coregen.cgp @@ -1,20 +1,22 @@ -# Date: Thu Sep 3 17:40:48 2009 -SET addpads = False -SET asysymbol = False +# Date: Mon Jul 26 21:55:33 2010 + +SET addpads = false +SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False +SET createndf = false SET designentry = Verilog SET device = xc3s2000 SET devicefamily = spartan3 SET flowvendor = Other -SET formalverification = False -SET foundationsym = False +SET formalverification = false +SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 -SET removerpms = False +SET removerpms = false SET simulationfiles = Behavioral SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/matt/coregen/tmp +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = /tmp/ +# CRC: 394da717 |