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authorJosh Blum <josh@joshknows.com>2010-11-23 13:36:42 -0800
committerJosh Blum <josh@joshknows.com>2010-11-23 13:36:42 -0800
commitbb0572a960edf54486a4be746c681adaac0fa398 (patch)
tree7afb46e99eaf799a478fcde841eb78d7698e9c39 /fpga/usrp2/control_lib/newfifo/fifo_pacer.v
parent8ce75a3ca7a51f4bdee87d78a610a0f2519473ae (diff)
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fpga: performed a forceful checkout of fpga to overwrite with current fpga code
Diffstat (limited to 'fpga/usrp2/control_lib/newfifo/fifo_pacer.v')
-rw-r--r--fpga/usrp2/control_lib/newfifo/fifo_pacer.v24
1 files changed, 24 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_pacer.v b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
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index 000000000..1bf03ab6e
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+++ b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
@@ -0,0 +1,24 @@
+
+
+module fifo_pacer
+ (input clk,
+ input reset,
+ input [7:0] rate,
+ input enable,
+ input src1_rdy_i, output dst1_rdy_o,
+ output src2_rdy_o, input dst2_rdy_i,
+ output underrun, overrun);
+
+ wire strobe;
+
+ cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
+ .rate(rate), .strobe_fast(1), .strobe_slow(strobe));
+
+ wire all_ready = src1_rdy_i & dst2_rdy_i;
+ assign dst1_rdy_o = all_ready & strobe;
+ assign src2_rdy_o = dst1_rdy_o;
+
+ assign underrun = strobe & ~src1_rdy_i;
+ assign overrun = strobe & ~dst2_rdy_i;
+
+endmodule // fifo_pacer