fpga: performed a forceful checkout of fpga to overwrite with current fpga code

19 files changed, 1138 insertions, 18 deletions

diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index bc8e4d5bc..d3bb7e2c8 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -21,6 +21,7 @@ nsgpio.v \
 ram_2port.v \
 ram_harv_cache.v \
 ram_harvard.v \
+ram_harvard2.v \
 ram_loader.v \
 setting_reg.v \
 settings_bus.v \
@@ -29,6 +30,7 @@ srl.v \
 system_control.v \
 wb_1master.v \
 wb_readback_mux.v \
+quad_uart.v \
 simple_uart.v \
 simple_uart_tx.v \
 simple_uart_rx.v \
@@ -42,4 +44,9 @@ pic.v \
 longfifo.v \
 shortfifo.v \
 medfifo.v \
+s3a_icap_wb.v \
+bootram.v \
+nsgpio16LE.v \
+settings_bus_16LE.v \
+atr_controller16.v \
 ))
diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v
new file mode 100644
index 000000000..3d8b5b1e9
--- /dev/null
+++ b/fpga/usrp2/control_lib/atr_controller16.v
@@ -0,0 +1,60 @@
+
+// Automatic transmit/receive switching of control pins to daughterboards
+// Store everything in registers for now, but could use a RAM for more
+// complex state machines in the future
+
+module atr_controller16
+  (input clk_i, input rst_i,
+   input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input run_rx, input run_tx, input [31:0] master_time,
+   output [31:0] ctrl_lines);
+   
+   reg [3:0] state;
+   reg [31:0] atr_ram [0:15];  // DP distributed RAM
+
+   wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]),
+			  (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) };
+   
+   // WB Interface
+   always @(posedge clk_i)
+     if(we_i & stb_i & cyc_i)
+       begin
+	  if(sel_int[3])
+	    atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8];
+	  if(sel_int[2])
+	    atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0];
+	  if(sel_int[1])
+	    atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
+	  if(sel_int[0])
+	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
+       end // if (we_i & stb_i & cyc_i)
+
+   always @(posedge clk_i)
+     dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+   
+   always @(posedge clk_i)
+     ack_o <= stb_i & cyc_i & ~ack_o;
+
+   // Control side of DP RAM
+   assign     ctrl_lines = atr_ram[state];
+
+   // Put a more complex state machine with time delays and multiple states here
+   //  if daughterboard requires more complex sequencing
+   localparam ATR_IDLE = 4'd0;
+   localparam ATR_TX = 4'd1;
+   localparam ATR_RX = 4'd2;
+   localparam ATR_FULL_DUPLEX = 4'd3;
+   
+   always @(posedge clk_i)
+     if(rst_i)
+       state <= ATR_IDLE;
+     else
+       case ({run_rx,run_tx})
+	 2'b00 : state <= ATR_IDLE;
+	 2'b01 : state <= ATR_TX;
+	 2'b10 : state <= ATR_RX;
+	 2'b11 : state <= ATR_FULL_DUPLEX;
+       endcase // case({run_rx,run_tx})
+   
+endmodule // atr_controller16
diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v
new file mode 100644
index 000000000..668012504
--- /dev/null
+++ b/fpga/usrp2/control_lib/bootram.v
@@ -0,0 +1,250 @@
+
+// Boot RAM for S3A, 8KB, dual port
+
+// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM
+//      Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1
+
+module bootram
+  (input clk, input reset,
+   input [12:0] if_adr,
+   output [31:0] if_data,
+
+   input [12:0] dwb_adr_i,
+   input [31:0] dwb_dat_i,
+   output [31:0] dwb_dat_o,
+   input dwb_we_i,
+   output reg dwb_ack_o,
+   input dwb_stb_i,
+   input [3:0] dwb_sel_i);
+
+   wire [31:0] DOA0, DOA1, DOA2, DOA3;
+   wire [31:0] DOB0, DOB1, DOB2, DOB3;
+   wire        ENB0, ENB1, ENB2, ENB3;
+   wire [3:0]  WEB;
+
+   reg [1:0]   delayed_if_bank;
+   always @(posedge clk)
+     delayed_if_bank <= if_adr[12:11];
+   
+   assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0);
+   assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0);
+
+   always @(posedge clk)
+     if(reset)
+       dwb_ack_o <= 0;
+     else
+       dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
+   
+   assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00);
+   assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01);
+   assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10);
+   assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11);
+
+   assign WEB = {4{dwb_we_i}} & dwb_sel_i;
+   
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM0
+     (.DOA(DOA0),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB0),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB0),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM1
+     (.DOA(DOA1),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB1),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB1),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM2
+     (.DOA(DOA2),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB2),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB2),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM3
+     (.DOA(DOA3),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB3),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB3),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+endmodule // bootram
+
+/*
+       // The following INIT_xx declarations specify the initial contents of the RAM
+       // Address 0 to 127
+       .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       // Address 128 to 255
+       .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       // Address 256 to 383
+       .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       // Address 384 to 511
+       .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       // The next set of INITP_xx are for the parity bits
+       // Address 0 to 127
+       .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       // Address 128 to 255
+       .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       // Address 256 to 383
+       .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       // Address 384 to 511
+       .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000)
+*/
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_pacer.v b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
new file mode 100644
index 000000000..1bf03ab6e
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
@@ -0,0 +1,24 @@
+
+
+module fifo_pacer
+  (input clk,
+   input reset,
+   input [7:0] rate,
+   input enable,
+   input src1_rdy_i, output dst1_rdy_o,
+   output src2_rdy_o, input dst2_rdy_i,
+   output underrun, overrun);
+
+   wire   strobe;
+   
+   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
+			.rate(rate), .strobe_fast(1), .strobe_slow(strobe));
+
+   wire   all_ready = src1_rdy_i & dst2_rdy_i;
+   assign dst1_rdy_o = all_ready & strobe;
+   assign src2_rdy_o = dst1_rdy_o;
+
+   assign underrun = strobe & ~src1_rdy_i;
+   assign overrun = strobe & ~dst2_rdy_i;
+   
+endmodule // fifo_pacer
diff --git a/fpga/usrp2/control_lib/newfifo/packet32_tb.v b/fpga/usrp2/control_lib/newfifo/packet32_tb.v
new file mode 100644
index 000000000..82bb09c29
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet32_tb.v
@@ -0,0 +1,27 @@
+
+
+module packet32_tb();
+
+   wire [35:0] data;
+   wire       src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet32_tb.vcd");
+   initial $dumpvars(0,packet32_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			       .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			      .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet32_tb
diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator.v b/fpga/usrp2/control_lib/newfifo/packet_generator.v
new file mode 100644
index 000000000..6e8b45ccd
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_generator.v
@@ -0,0 +1,59 @@
+
+
+module packet_generator
+  (input clk, input reset, input clear,
+   output reg [7:0] data_o, output sof_o, output eof_o, 
+   output src_rdy_o, input dst_rdy_i);
+
+   localparam len = 32'd2000;
+
+   reg [31:0] state;
+   reg [31:0] seq;
+   wire [31:0] crc_out;
+   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+   
+	
+   always @(posedge clk)
+     if(reset | clear)
+       seq <= 0;
+     else
+       if(eof_o & src_rdy_o & dst_rdy_i)
+	 seq <= seq + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(src_rdy_o & dst_rdy_i)
+	 if(state == (len - 1))
+	   state <= 32'hFFFF_FFFC;
+	 else
+	   state <= state + 1;
+
+   always @*
+     case(state)
+       0 :   data_o <= len[7:0];
+       1 :   data_o <= len[15:8];
+       2 :   data_o <= len[23:16];
+       3 :   data_o <= len[31:24];
+       4 :   data_o <= seq[7:0];
+       5 :   data_o <= seq[15:8];
+       6 :   data_o <= seq[23:16];
+       7 :   data_o <= seq[31:24];
+       32'hFFFF_FFFC : data_o <= crc_out[31:24];
+       32'hFFFF_FFFD : data_o <= crc_out[23:16];
+       32'hFFFF_FFFE : data_o <= crc_out[15:8];
+       32'hFFFF_FFFF : data_o <= crc_out[7:0];
+       default : data_o <= state[7:0];
+     endcase // case (state)
+   
+   assign src_rdy_o = 1;
+   assign sof_o = (state == 0);
+   assign eof_o = (state == 32'hFFFF_FFFF);
+
+   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
+	   .calc(calc_crc), .crc_out(crc_out), .match());
+   
+endmodule // packet_generator
diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator32.v b/fpga/usrp2/control_lib/newfifo/packet_generator32.v
new file mode 100644
index 000000000..6f8004964
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_generator32.v
@@ -0,0 +1,21 @@
+
+
+module packet_generator32
+  (input clk, input reset, input clear,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n;
+   
+   packet_generator pkt_gen
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
+
+   ll8_to_fifo36 ll8_to_f36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof),
+      .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n),
+      .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i));
+   
+endmodule // packet_generator32
diff --git a/fpga/usrp2/control_lib/newfifo/packet_tb.v b/fpga/usrp2/control_lib/newfifo/packet_tb.v
new file mode 100644
index 000000000..3c423d2ba
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_tb.v
@@ -0,0 +1,29 @@
+
+
+module packet_tb();
+
+   wire [7:0] data;
+   wire       sof, eof, src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet_tb.vcd");
+   initial $dumpvars(0,packet_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			     .data_o(data), .sof_o(sof), .eof_o(eof),
+			     .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			    .data_i(data), .sof_i(sof), .eof_i(eof),
+			    .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			    .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_tb
diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier.v b/fpga/usrp2/control_lib/newfifo/packet_verifier.v
new file mode 100644
index 000000000..b49ad1bbb
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_verifier.v
@@ -0,0 +1,61 @@
+
+
+// Packet format --
+//    Line 1 -- Length, 32 bits
+//    Line 2 -- Sequence number, 32 bits
+//    Last line -- CRC, 32 bits
+
+module packet_verifier
+  (input clk, input reset, input clear,
+   input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o,
+
+   output reg [31:0] total, 
+   output reg [31:0] crc_err, 
+   output reg [31:0] seq_err, 
+   output reg [31:0] len_err);
+
+   reg [31:0] 	     seq_num;
+   reg [31:0] 	     length;
+   wire 	     first_byte, last_byte;
+   reg 		     second_byte, last_byte_d1;
+
+   wire 	     calc_crc = src_rdy_i & dst_rdy_o;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
+	   .calc(calc_crc), .crc_out(), .match(match_crc));
+
+   assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
+   assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+   assign dst_rdy_o = ~last_byte_d1;
+
+   // stubs for now
+   wire 	     match_seq = 1;
+   wire 	     match_len = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       last_byte_d1 <= 0;
+     else 
+       last_byte_d1 <= last_byte;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  total <= 0;
+	  crc_err <= 0;
+	  seq_err <= 0;
+	  len_err <= 0;
+       end
+     else
+       if(last_byte_d1)
+	 begin
+	    total <= total + 1;
+	    if(~match_crc)
+	      crc_err <= crc_err + 1;
+	    else if(~match_seq)
+	      seq_err <= seq_err + 1;
+	    else if(~match_len)
+	      seq_err <= len_err + 1;
+	 end
+   
+endmodule // packet_verifier
diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier32.v b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v
new file mode 100644
index 000000000..06a13d242
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v
@@ -0,0 +1,30 @@
+
+
+module packet_verifier32
+  (input clk, input reset, input clear,
+   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy;
+   wire [35:0] 	     data_int;
+   wire 	     src_rdy_int, dst_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));
+   
+   fifo36_to_ll8 f36_to_ll8
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
+      .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy));
+   
+   packet_verifier pkt_ver
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n),
+      .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_verifier32
diff --git a/fpga/usrp2/control_lib/nsgpio16LE.v b/fpga/usrp2/control_lib/nsgpio16LE.v
new file mode 100644
index 000000000..8aef0c7ae
--- /dev/null
+++ b/fpga/usrp2/control_lib/nsgpio16LE.v
@@ -0,0 +1,123 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores Simple General Purpose IO core                   ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+
+module nsgpio16LE
+  (input clk_i, input rst_i, 
+   input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, 
+   output reg [15:0] dat_o, output reg ack_o,
+   input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 
+   inout [31:0] gpio
+   );
+
+   reg [31:0] 	ctrl, line, ddr, dbg, lgpio;
+   
+   wire 	wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire 	wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       begin
+          ctrl <= 32'h0;
+          line <= 32'h0;
+	  ddr <= 32'h0;
+	  dbg <= 32'h0;
+       end
+     else if (wb_wr)
+       case( adr_i[3:1] )
+	 3'b000 : 
+           line[15:0] <= dat_i;
+	 3'b001 : 
+           line[31:16] <= dat_i;
+	 3'b010 :
+	   ddr[15:0] <= dat_i;
+	 3'b011 :
+	   ddr[31:16] <= dat_i;
+	 3'b100 :
+	   ctrl[15:0] <= dat_i;
+	 3'b101 :
+	   ctrl[31:16] <= dat_i;
+	 3'b110 :
+	   dbg[15:0] <= dat_i;
+	 3'b111 :
+	   dbg[31:16] <= dat_i;
+       endcase // case ( adr_i[3:1] )
+   
+   always @(posedge clk_i)
+     case (adr_i[3:1])
+       3'b000 :
+	 dat_o <= lgpio[15:0];
+       3'b001 :
+	 dat_o <= lgpio[31:16];
+       3'b010 :
+	 dat_o <= ddr[15:0];
+       3'b011 :
+	 dat_o <= ddr[31:16];
+       3'b100 :
+	 dat_o <= ctrl[15:0];
+       3'b101 :
+	 dat_o <= ctrl[31:16];
+       3'b110 :
+	 dat_o <= dbg[15:0];
+       3'b111 :
+	 dat_o <= dbg[31:16];
+     endcase // case (adr_i[3:1])
+   
+   
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & !ack_o;
+   
+   // latch GPIO input pins
+   always @(posedge clk_i)
+     lgpio <= gpio;
+   
+   // assign GPIO outputs
+   integer   n;
+   reg [31:0] igpio; // temporary internal signal
+   
+   always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg)
+     for(n=0;n<32;n=n+1)
+       igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : 
+			     (ctrl[n] ?  atr[n] : line[n]) )
+	 : 1'bz;
+   
+   assign     gpio = igpio;
+   
+endmodule
+
diff --git a/fpga/usrp2/control_lib/quad_uart.v b/fpga/usrp2/control_lib/quad_uart.v
new file mode 100644
index 000000000..afa6fae1d
--- /dev/null
+++ b/fpga/usrp2/control_lib/quad_uart.v
@@ -0,0 +1,71 @@
+
+module quad_uart
+  #(parameter TXDEPTH = 1,
+    parameter RXDEPTH = 1)
+    (input clk_i, input rst_i,
+     input we_i, input stb_i, input cyc_i, output reg ack_o,
+     input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+     output [3:0] rx_int_o, output [3:0] tx_int_o, 
+     output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o
+     );
+   
+   // Register Map
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+   
+   wire       wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire       wb_wr  = wb_acc & we_i;            // WISHBONE write access
+   
+   reg [15:0] clkdiv[0:3];
+   wire [7:0] rx_char[0:3];
+   wire  [3:0] tx_fifo_full, rx_fifo_empty;   
+   wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3];
+
+   always @(posedge clk_i)
+     if (rst_i)
+       ack_o 			    <= 1'b0;
+     else
+       ack_o 			    <= wb_acc & ~ack_o;
+
+   integer    i;
+   always @(posedge clk_i)
+     if (rst_i)
+       for(i=0;i<4;i=i+1)
+	 clkdiv[i] <= 0;
+     else if (wb_wr)
+       case(adr_i[2:0])
+	 SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0];
+       endcase // case(adr_i)
+   
+   always @(posedge clk_i)
+     case (adr_i[2:0])
+       SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]];
+       SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]];
+       SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]];
+     endcase // case(adr_i)
+
+   genvar     j;
+   generate
+      for(j=0;j<4;j=j+1)
+	begin : gen_uarts
+	   simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
+	    (.clk(clk_i),.rst(rst_i),
+	     .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)),
+	     .fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]),
+	     .clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j]));
+	   
+	   simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
+	     (.clk(clk_i),.rst(rst_i),
+	      .fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)),
+	      .fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]),
+	      .clkdiv(clkdiv[j]),.rx(rx_i[j]));
+	end // block: gen_uarts
+   endgenerate
+   
+   assign     tx_int_o 	= ~tx_fifo_full;  // Interrupt for those that have space
+   assign     rx_int_o 	= ~rx_fifo_empty; // Interrupt for those that have data
+   
+endmodule // quad_uart
diff --git a/fpga/usrp2/control_lib/ram_2port_mixed_width.v b/fpga/usrp2/control_lib/ram_2port_mixed_width.v
new file mode 100644
index 000000000..fae7d8de3
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_2port_mixed_width.v
@@ -0,0 +1,120 @@
+
+module ram_2port_mixed_width
+  (input clk16,
+   input en16,
+   input we16,
+   input [10:0] addr16,
+   input [15:0] di16,
+   output [15:0] do16,
+   input clk32,
+   input en32,
+   input we32,
+   input [9:0] addr32,
+   input [31:0] di32,
+   output [31:0] do32);
+
+   wire 	 en32a = en32 & ~addr32[9];
+   wire 	 en32b = en32 & addr32[9];
+   wire 	 en16a = en16 & ~addr16[10];
+   wire 	 en16b = en16 & addr16[10];
+
+   wire [31:0] 	 do32a, do32b;
+   wire [15:0] 	 do16a, do16b;
+   
+   assign do32 = addr32[9] ? do32b : do32a;
+   assign do16 = addr16[10] ? do16b : do16a;
+   
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_0 (.DOA(do32a),       // Port A 32-bit Data Output
+			.DOB(do16a),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32a),       // Port A 1-bit RAM Enable Input
+			.ENB(en16a),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_1 (.DOA(do32b),       // Port A 32-bit Data Output
+			.DOB(do16b),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32b),       // Port A 1-bit RAM Enable Input
+			.ENB(en16b),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+endmodule // ram_2port_mixed_width
+
+
+
+   
+// ISE 10.1.03 chokes on the following
+   
+/*
+   
+   reg [31:0] 	       ram [(1<<AWIDTH)-1:0];
+   integer 	       i;
+   initial
+     for(i=0;i<512;i=i+1)
+       ram[i] <= 32'b0;
+   
+   always @(posedge clk16)
+     if (en16)
+       begin
+          if (we16)
+            if(addr16[0])
+	      ram[addr16[10:1]][15:0] <= di16;
+	    else
+	      ram[addr16[10:1]][31:16] <= di16;
+	  do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
+       end
+
+   always @(posedge clk32)
+     if (en32)
+       begin
+          if (we32)
+            ram[addr32] <= di32;
+          do32 <= ram[addr32];
+       end
+
+endmodule // ram_2port_mixed_width
+
+ 
+ */
diff --git a/fpga/usrp2/control_lib/ram_harvard2.v b/fpga/usrp2/control_lib/ram_harvard2.v
new file mode 100644
index 000000000..67777af2a
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_harvard2.v
@@ -0,0 +1,77 @@
+
+
+// Dual ported, Harvard architecture
+
+module ram_harvard2
+  #(parameter AWIDTH=15,
+    parameter RAM_SIZE=32768)
+   (input wb_clk_i, 
+    input wb_rst_i,
+    // Instruction fetch port.
+    input [AWIDTH-1:0] if_adr,
+    output reg [31:0] if_data,
+    // Data access port.
+    input [AWIDTH-1:0] dwb_adr_i,
+    input [31:0] dwb_dat_i, 
+    output reg [31:0] dwb_dat_o,
+    input dwb_we_i,
+    output dwb_ack_o,
+    input dwb_stb_i,
+    input [3:0] dwb_sel_i);
+   
+   reg 	  ack_d1;
+   reg 	  stb_d1;
+   
+   assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       ack_d1 <= 1'b0;
+     else 
+       ack_d1 <= dwb_ack_o;
+
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       stb_d1 <= 0;
+     else
+       stb_d1 <= dwb_stb_i;
+
+   reg [7:0] ram0 [0:(RAM_SIZE/4)-1];
+   reg [7:0] ram1 [0:(RAM_SIZE/4)-1];
+   reg [7:0] ram2 [0:(RAM_SIZE/4)-1];
+   reg [7:0] ram3 [0:(RAM_SIZE/4)-1];
+   
+   // Port 1, Read only
+   always @(posedge wb_clk_i)
+     if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]];
+
+   // Port 2, R/W
+   always @(posedge wb_clk_i)
+     if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]];
+   
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
+       ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
+       ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
+       ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
+       ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
+   
+endmodule // ram_harvard
diff --git a/fpga/usrp2/control_lib/s3a_icap_wb.v b/fpga/usrp2/control_lib/s3a_icap_wb.v
new file mode 100644
index 000000000..83d9f775e
--- /dev/null
+++ b/fpga/usrp2/control_lib/s3a_icap_wb.v
@@ -0,0 +1,59 @@
+
+
+module s3a_icap_wb
+  (input clk, input reset,
+   input cyc_i, input stb_i, input we_i, output ack_o,
+   input [31:0] dat_i, output [31:0] dat_o);//, output [31:0] debug_out);
+
+   assign dat_o[31:8] = 24'd0;
+   
+   wire 	BUSY, CE, WRITE, ICAPCLK;
+   
+   //changed this to gray-ish code to prevent glitching
+   reg [2:0] 	icap_state;
+   localparam ICAP_IDLE  = 0;
+   localparam ICAP_WR0 	 = 1;
+   localparam ICAP_WR1 	 = 5;
+   localparam ICAP_RD0 	 = 2;
+   localparam ICAP_RD1 	 = 3;
+
+   always @(posedge clk)
+     if(reset)
+       icap_state 	<= ICAP_IDLE;
+     else
+       case(icap_state)
+	 ICAP_IDLE :
+	   begin
+	      if(stb_i & cyc_i)
+		if(we_i)
+		  icap_state <= ICAP_WR0;
+		else
+		  icap_state <= ICAP_RD0;
+	   end
+	 ICAP_WR0 :
+	   icap_state <= ICAP_WR1;
+	 ICAP_WR1 :
+	   icap_state <= ICAP_IDLE;
+	 ICAP_RD0 :
+	   icap_state <= ICAP_RD1;
+	 ICAP_RD1 :
+	   icap_state <= ICAP_IDLE;
+       endcase // case (icap_state)
+
+   assign WRITE 	 = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
+   assign CE 		 = (icap_state == ICAP_WR0) | (icap_state == ICAP_RD0);
+   assign ICAPCLK        = CE & (~clk);
+
+   assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+   //assign debug_out = {17'd0, BUSY, dat_i[7:0], ~CE, ICAPCLK, ~WRITE, icap_state};
+   
+   ICAP_SPARTAN3A ICAP_SPARTAN3A_inst 
+     (.BUSY(BUSY),          // Busy output
+      .O(dat_o[7:0]),            // 32-bit data output
+      .CE(~CE),              // Clock enable input
+      .CLK(ICAPCLK),            // Clock input
+      .I(dat_i[7:0]),            // 32-bit data input
+      .WRITE(~WRITE)         // Write input
+      );
+
+endmodule // s3a_icap_wb
diff --git a/fpga/usrp2/control_lib/settings_bus.v b/fpga/usrp2/control_lib/settings_bus.v
index fc960e456..aec179516 100644
--- a/fpga/usrp2/control_lib/settings_bus.v
+++ b/fpga/usrp2/control_lib/settings_bus.v
@@ -10,7 +10,7 @@ module settings_bus
      input wb_stb_i,
      input wb_we_i,
      output reg wb_ack_o,
-     output strobe,
+     output reg strobe,
      output reg [7:0] addr,
      output reg [31:0] data);
 
@@ -19,18 +19,18 @@ module settings_bus
    always @(posedge wb_clk)
      if(wb_rst)
        begin
-	  stb_int <= 1'b0;
+	  strobe <= 1'b0;
 	  addr <= 8'd0;
 	  data <= 32'd0;
        end
-     else if(wb_we_i & wb_stb_i)
+     else if(wb_we_i & wb_stb_i & ~wb_ack_o)
        begin
-	  stb_int <= 1'b1;
+	  strobe <= 1'b1;
 	  addr <= wb_adr_i[9:2];
 	  data <= wb_dat_i;
        end
      else
-       stb_int <= 1'b0;
+       strobe <= 1'b0;
 
    always @(posedge wb_clk)
      if(wb_rst)
@@ -38,11 +38,4 @@ module settings_bus
      else
        wb_ack_o <= wb_stb_i & ~wb_ack_o;
 
-   always @(posedge wb_clk)
-     stb_int_d1 <= stb_int;
-
-   //assign strobe = stb_int & ~stb_int_d1;
-   assign strobe = stb_int & wb_ack_o;
-          
 endmodule // settings_bus
-
diff --git a/fpga/usrp2/control_lib/settings_bus_16LE.v b/fpga/usrp2/control_lib/settings_bus_16LE.v
new file mode 100644
index 000000000..76061e9e0
--- /dev/null
+++ b/fpga/usrp2/control_lib/settings_bus_16LE.v
@@ -0,0 +1,54 @@
+
+// Grab settings off the wishbone bus, send them out to settings bus
+// 16 bits little endian, but all registers need to be written 32 bits at a time.
+// This means that you write the low 16 bits first and then the high 16 bits.
+// The setting regs are strobed when the high 16 bits are written
+
+module settings_bus_16LE
+  #(parameter AWIDTH=16, RWIDTH=8)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [15:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     output strobe,
+     output reg [7:0] addr,
+     output reg [31:0] data);
+
+   reg 		       stb_int;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  stb_int <= 1'b0;
+	  addr <= 8'd0;
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i)
+       begin
+	  addr <= wb_adr_i[RWIDTH+1:2];  // Zero pad high bits
+	  if(wb_adr_i[1])
+	    begin
+	       stb_int <= 1'b1;     // We now have both halves
+	       data[31:16] <= wb_dat_i;
+	    end
+	  else
+	    begin
+	       stb_int <= 1'b0;     // Don't strobe, we need other half
+	       data[15:0] <= wb_dat_i;
+	    end
+       end
+     else
+       stb_int <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+   assign strobe = stb_int & wb_ack_o;
+          
+endmodule // settings_bus_16LE
diff --git a/fpga/usrp2/control_lib/simple_uart.v b/fpga/usrp2/control_lib/simple_uart.v
index 22f0e70a2..0dd58b5f5 100644
--- a/fpga/usrp2/control_lib/simple_uart.v
+++ b/fpga/usrp2/control_lib/simple_uart.v
@@ -1,11 +1,12 @@
 
 module simple_uart
   #(parameter TXDEPTH = 1,
-    parameter RXDEPTH = 1)
-    (input clk_i, input rst_i,
-     input we_i, input stb_i, input cyc_i, output reg ack_o,
-     input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
-     output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+    parameter RXDEPTH = 1,
+    parameter CLKDIV_DEFAULT = 16'd0)
+   (input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+    output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
    
    // Register Map
    localparam SUART_CLKDIV = 0;
@@ -30,7 +31,7 @@ module simple_uart
    
    always @(posedge clk_i)
      if (rst_i)
-       clkdiv <= 0;
+       clkdiv <= CLKDIV_DEFAULT;
      else if (wb_wr)
        case(adr_i)
 	 SUART_CLKDIV : clkdiv <= dat_i[15:0];
diff --git a/fpga/usrp2/control_lib/v5icap_wb.v b/fpga/usrp2/control_lib/v5icap_wb.v
new file mode 100644
index 000000000..c8800285a
--- /dev/null
+++ b/fpga/usrp2/control_lib/v5icap_wb.v
@@ -0,0 +1,54 @@
+
+
+module v5icap_wb
+  (input clk, input reset,
+   input cyc_i, input stb_i, input we_i, output ack_o,
+   input [31:0] dat_i, output [31:0] dat_o);
+
+   wire 	BUSY, CE, WRITE;
+   
+   reg [2:0] 	icap_state;
+   localparam ICAP_IDLE  = 0;
+   localparam ICAP_WR0 	 = 1;
+   localparam ICAP_WR1 	 = 2;
+   localparam ICAP_RD0 	 = 3;
+   localparam ICAP_RD1 	 = 4;
+
+   always @(posedge clk)
+     if(reset)
+       icap_state 	<= ICAP_IDLE;
+     else
+       case(icap_state)
+	 ICAP_IDLE :
+	   begin
+	      if(stb_i & cyc_i)
+		if(we_i)
+		  icap_state <= ICAP_WR0;
+		else
+		  icap_state <= ICAP_RD0;
+	   end
+	 ICAP_WR0 :
+	   icap_state <= ICAP_WR1;
+	 ICAP_WR1 :
+	   icap_state <= ICAP_IDLE;
+	 ICAP_RD0 :
+	   icap_state <= ICAP_RD1;
+	 ICAP_RD1 :
+	   icap_state <= ICAP_IDLE;
+       endcase // case (icap_state)
+
+   assign WRITE 	 = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
+   assign CE 		 = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0);
+
+   assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+   
+   ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst 
+     (.BUSY(BUSY),          // Busy output
+      .O(dat_o),            // 32-bit data output
+      .CE(~CE),              // Clock enable input
+      .CLK(clk),            // Clock input
+      .I(dat_i),            // 32-bit data input
+      .WRITE(~WRITE)         // Write input
+      );
+
+endmodule // v5icap_wb