Add a few readme embellishments

1 files changed, 34 insertions, 33 deletions

diff --git a/README.md b/README.md
index 6e9a6b6..29946d9 100644
--- a/README.md
+++ b/README.md
@@ -35,38 +35,38 @@ PCB Assembly Plan
 =================
 
 1. DCDC converter for 8V and LDOs
-  * Check output voltages
-  * Check drop under load
+   * Check output voltages
+   * Check drop under load
 
 2. STM32F103C8T6
-  * Programming
-  * Sidetone low-pass
-  * Probably need to do a UI proto already
+   * Programming
+   * Sidetone low-pass
+   * Probably need to do a UI proto already
 
 3. Si5153
-  * Check I2C works
+   * Check I2C works
 
 4. 8V and 5V relay
-  * Check switching with microcontroller and validate resistors
+   * Check switching with microcontroller and validate resistors
 
 5. Baseband
-  1. Crystal filter shape
-  2. RX and TX filter shape
-  3. Receive path: IF mixer, crystal filter relay, IF AGC, BFO mixer, AGC measure, AF amp, SPKR
-    * Verify LO levels into SA602A: at least 200mVpp
-  4. Transmit path: Mic amp
+   * Crystal filter shape
+   * RX and TX filter shape
+   * Receive path: IF mixer, crystal filter relay, IF AGC, BFO mixer, AGC measure, AF amp, SPKR
+      * Verify LO levels into SA602A: at least 200mVpp
+   * Transmit path: Mic amp
 
 6. Anglian
-  1. LO filter shape
-  2. LO amp. Mixer needs +7dBm
-  3. All passives
-    * Verify correct voltages for amplifiers
-    * Verify PIN currents (Between 20mA and 60mA, below 0.8V)
-    * Verify filter shapes
-  4. IF amplifiers, both RX and TX
-  5. VHF amplifiers
-  6. VHF bandpass filter
-  7. Mixer
+   *  LO filter shape
+   *  LO amp. Mixer needs +7dBm
+   *  All passives
+      * Verify correct voltages for amplifiers
+      * Verify PIN currents (Between 20mA and 60mA, below 0.8V)
+      * Verify filter shapes
+   *  IF amplifiers, both RX and TX
+   *  VHF amplifiers
+   *  VHF bandpass filter
+   *  Mixer
 
 7. External switching relay
 
@@ -74,15 +74,16 @@ PCB Assembly Plan
 Additional remarks
 ==================
 
-* Very good [explanations](https://groups.io/g/BITX20/topic/si5351a_facts_and_myths/5430607) about DDS vs DPLL from Hans Summers
-
-* Si5153 test before PCB fab:
-  * It seems the desired frequency plan can be achieved:
-    * clk0: LO1 = 28 - 4.9152 + VFO, i.e. from 23 to 25
-    * clk1: VHF-LO = 144 + 28 and 144 - 28, i.e. 116 MHz
-    * clk2: BFO = 4.91521
-    * See `freqplan.py`
-  * If not, generate LO1 and BFO with Si5153, and connect an external LO to the VHF LO u.FL
-    * No 116MHz crystals on mouser, but 114.285MHz are available, HF bandpass filters recalculated.
-    * Other option is using another configurable reference
+Very good [explanations](https://groups.io/g/BITX20/topic/si5351a_facts_and_myths/5430607) about DDS vs DPLL from Hans Summers
+
+Si5153 test before PCB fab:
+
+* It seems the desired frequency plan can be achieved:
+  * clk0: LO1 = 28 - 4.9152 + VFO, i.e. from 23 to 25
+  * clk1: VHF-LO = 144 + 28 and 144 - 28, i.e. 116 MHz
+  * clk2: BFO = 4.91521
+  * See `freqplan.py`
+* If not, generate LO1 and BFO with Si5153, and connect an external LO to the VHF LO u.FL
+  * No 116MHz crystals on mouser, but 114.285MHz are available, HF bandpass filters recalculated.
+  * Other option is using another configurable reference