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author | Matthias P. Braendli <matthias.braendli@mpb.li> | 2019-04-11 16:22:04 +0200 |
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committer | Matthias P. Braendli <matthias.braendli@mpb.li> | 2019-04-11 16:22:04 +0200 |
commit | eed7072d6336a3cfdc8b52eb20166529a4de4d81 (patch) | |
tree | 1505819a1216406e6f15c4315bed93750c7ed68d /src/glutt-o-logique | |
parent | 3555e921a0c743dbc2cc10d8655827be975c61e0 (diff) | |
download | glutte-o-matic-eed7072d6336a3cfdc8b52eb20166529a4de4d81.tar.gz glutte-o-matic-eed7072d6336a3cfdc8b52eb20166529a4de4d81.tar.bz2 glutte-o-matic-eed7072d6336a3cfdc8b52eb20166529a4de4d81.zip |
Add some 1750 detection code to glutt-o-logic
Diffstat (limited to 'src/glutt-o-logique')
-rw-r--r-- | src/glutt-o-logique/analog_input.c | 27 | ||||
-rw-r--r-- | src/glutt-o-logique/analog_input.h | 13 | ||||
-rw-r--r-- | src/glutt-o-logique/audio_in.c | 148 | ||||
-rw-r--r-- | src/glutt-o-logique/pio.c | 2 | ||||
-rw-r--r-- | src/glutt-o-logique/stm32f4discovery-with-stlinkv2.1.cfg | 10 |
5 files changed, 179 insertions, 21 deletions
diff --git a/src/glutt-o-logique/analog_input.c b/src/glutt-o-logique/analog_input.c index 5f0e700..fb9db48 100644 --- a/src/glutt-o-logique/analog_input.c +++ b/src/glutt-o-logique/analog_input.c @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2016 Matthias P. Braendli, Maximilien Cuony + * Copyright (c) 2019 Matthias P. Braendli, Maximilien Cuony * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,15 +30,26 @@ #include "Core/delay.h" #include "Core/common.h" +#include "stm32f4xx_conf.h" #include "stm32f4xx_adc.h" +#include "stm32f4xx_gpio.h" #include <math.h> #include "GPIO/usart.h" +#define PIN_SUPPLY GPIO_Pin_5 +#define PIN_SWR_FWD GPIO_Pin_6 +#define PIN_SWR_REFL GPIO_Pin_7 + +// see doc/pio.txt for allocation +#define PINS_ADC1 /* PA pins */ (GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7) + +#define ADC1_CHANNEL_SUPPLY ADC_Channel_5 +#define ADC1_CHANNEL_SWR_FWD ADC_Channel_6 +#define ADC1_CHANNEL_SWR_REFL ADC_Channel_7 + // Measured on the board itself const float v_ref = 2.965f; -#warning "TODO: initialise ADC2 and use it for NF input" - void analog_init(void) { // Enable ADC and GPIOA clocks @@ -48,7 +59,7 @@ void analog_init(void) // Set analog input pins mode GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_Pin = PINS_ANALOG; + GPIO_InitStructure.GPIO_Pin = PINS_ADC1; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; @@ -77,7 +88,7 @@ void analog_init(void) ADC_Cmd(ADC1, ENABLE); } -static uint16_t analog_read_channel(uint8_t channel) +static uint16_t adc1_read(uint8_t channel) { ADC_RegularChannelConfig(ADC1, channel, @@ -115,7 +126,7 @@ static uint16_t analog_read_channel(uint8_t channel) float analog_measure_12v(void) { - const uint16_t raw_value = analog_read_channel(ADC_CHANNEL_SUPPLY); + const uint16_t raw_value = adc1_read(ADC1_CHANNEL_SUPPLY); const float adc_max_value = (1 << 12); @@ -129,8 +140,8 @@ float analog_measure_12v(void) int analog_measure_swr(int *forward_mv, int* reflected_mv) { - const uint16_t raw_swr_fwd_value = analog_read_channel(ADC_CHANNEL_SWR_FWD); - const uint16_t raw_swr_refl_value = analog_read_channel(ADC_CHANNEL_SWR_REFL); + const uint16_t raw_swr_fwd_value = adc1_read(ADC1_CHANNEL_SWR_FWD); + const uint16_t raw_swr_refl_value = adc1_read(ADC1_CHANNEL_SWR_REFL); const float adc_max_value = (1 << 12); diff --git a/src/glutt-o-logique/analog_input.h b/src/glutt-o-logique/analog_input.h index 0385ec4..635482f 100644 --- a/src/glutt-o-logique/analog_input.h +++ b/src/glutt-o-logique/analog_input.h @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2016 Matthias P. Braendli, Maximilien Cuony + * Copyright (c) 2019 Matthias P. Braendli, Maximilien Cuony * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,17 +24,6 @@ #pragma once -#include "stm32f4xx_conf.h" -#include "stm32f4xx_gpio.h" #include "GPIO/analog.h" -#define PIN_SUPPLY GPIO_Pin_5 -#define PIN_SWR_FWD GPIO_Pin_6 -#define PIN_SWR_REFL GPIO_Pin_7 - -#define PINS_ANALOG (GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7) - -#define ADC_CHANNEL_SUPPLY ADC_Channel_5 -#define ADC_CHANNEL_SWR_FWD ADC_Channel_6 -#define ADC_CHANNEL_SWR_REFL ADC_Channel_7 diff --git a/src/glutt-o-logique/audio_in.c b/src/glutt-o-logique/audio_in.c new file mode 100644 index 0000000..743c79b --- /dev/null +++ b/src/glutt-o-logique/audio_in.c @@ -0,0 +1,148 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Matthias P. Braendli, Maximilien Cuony + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*/ + +#include "stm32f4xx_conf.h" +#include "stm32f4xx_gpio.h" +#include "stm32f4xx_adc.h" + +#include "Core/common.h" +#include "Audio/audio_in.h" +#include "queue.h" + +// APB1 prescaler = 4, see bsp/system_stm32f4xx.c +#define APB1_FREQ (168000000ul / 4) +#define ADC2_SAMPLE_FREQ 16000 +#define ADC2_CHANNEL_AUDIO ADC_Channel_14 + +// see doc/pio.txt for allocation +#define PINS_ADC2 /* PB1 on ADC2 IN9 */ (GPIO_Pin_1) + +#warning "TODO: initialise ADC2 and use it for NF input" + +// The TIM6 ISR reads from ADC2 and writes into this buffer +static int16_t adc2_values[AUDIO_IN_BUF_LEN]; +static int adc2_values_end = 0; + +// ADC2 data from interrupt to userspace goes through the queue +static QueueHandle_t adc2_values_queue; + +/* ISR for Timer6 and DAC1&2 underrun */ +void TIM6_DAC_IRQHandler(void) +{ + if (TIM_GetITStatus(TIM6, TIM_IT_Update)) { + if (ADC_GetFlagStatus(ADC2, ADC_FLAG_EOC) == SET) { + uint16_t value = ADC_GetConversionValue(ADC2); + /* input range: 0 to 65535 + * output range: -32768 to 32767 */ + adc2_values[adc2_values_end++] = (int32_t)value - 32768; + if (adc2_values_end == AUDIO_IN_BUF_LEN) { + int success = xQueueSendToBackFromISR( + adc2_values_queue, + adc2_values, + NULL); + + adc2_values_end = 0; + + if (success == pdFALSE) { + trigger_fault(FAULT_SOURCE_ADC2); + } + } + } + else { +#warning "handle fault" + } + + ADC_SoftwareStartConv(ADC2); + + TIM_ClearITPendingBit(TIM6, TIM_IT_Update); + } +} + +// Timer6 is used for ADC2 sampling +static void enable_timer6(void) +{ + /* TIM6 Periph clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE); + + /* Time base configuration */ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); + TIM_TimeBaseStructure.TIM_Period = (int)(APB1_FREQ/ADC2_SAMPLE_FREQ); + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM6, &TIM_TimeBaseStructure); + + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = TIM6_DAC_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + TIM_Cmd(TIM6, ENABLE); + ADC_SoftwareStartConv(ADC2); + TIM_ITConfig(TIM6, TIM_IT_Update, ENABLE); +} + + +void audio_in_initialize(int rate) +{ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_Pin = PINS_ADC2; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + // Init ADC2 for NF input + ADC_InitTypeDef ADC_InitStruct; + ADC_InitStruct.ADC_Resolution = ADC_Resolution_12b; + ADC_InitStruct.ADC_ScanConvMode = DISABLE; + ADC_InitStruct.ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStruct.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct.ADC_NbrOfConversion = 1; + ADC_Init(ADC2, &ADC_InitStruct); + + ADC_Cmd(ADC2, ENABLE); + + adc2_values_queue = xQueueCreate(4, AUDIO_IN_BUF_LEN); + if (adc2_values_queue == 0) { + while(1); /* fatal error */ + } + + enable_timer6(); +} + +void audio_in_get_buffer(int16_t *buffer /*of length AUDIO_IN_BUF_LEN*/ ) +{ + while (!xQueueReceive(adc2_values_queue, buffer, portMAX_DELAY)) {} +} + diff --git a/src/glutt-o-logique/pio.c b/src/glutt-o-logique/pio.c index e944671..1069886 100644 --- a/src/glutt-o-logique/pio.c +++ b/src/glutt-o-logique/pio.c @@ -304,7 +304,7 @@ void pio_set_mod_off(int mod_off) } int pio_read_button() { - return GPIO_ReadInputDataBit(GPIOA,GPIO_Pin_0) == Bit_SET; + return GPIO_ReadInputDataBit(GPIOA,GPIOA_PIN_PUSHBTN) == Bit_SET; } void pio_set_gps_epps(int on) diff --git a/src/glutt-o-logique/stm32f4discovery-with-stlinkv2.1.cfg b/src/glutt-o-logique/stm32f4discovery-with-stlinkv2.1.cfg new file mode 100644 index 0000000..18369f5 --- /dev/null +++ b/src/glutt-o-logique/stm32f4discovery-with-stlinkv2.1.cfg @@ -0,0 +1,10 @@ +# This is an STM32F4 discovery board with a single STM32F407VGT6 chip. +# http://www.st.com/internet/evalboard/product/252419.jsp + +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +source [find target/stm32f4x.cfg] + +reset_config srst_only |