1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
|
#
# Copyright 2008 Ettus Research LLC
#
# This file is part of GNU Radio
#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
##################################################
# xtclsh Shell and tcl Script Path
##################################################
#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
XTCLSH := xtclsh
ISE_HELPER := ../tcl/ise_helper.tcl
##################################################
# Project Setup
##################################################
BUILD_DIR := build/
export TOP_MODULE := safe_u1plus
export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
##################################################
# Project Properties
##################################################
export PROJECT_PROPERTIES := \
family "Spartan3A" \
device XC3S1400A \
package ft256 \
speed -4 \
top_level_module_type "HDL" \
synthesis_tool "XST (VHDL/Verilog)" \
simulator "ISE Simulator (VHDL/Verilog)" \
"Preferred Language" "Verilog" \
"Enable Message Filtering" FALSE \
"Display Incremental Messages" FALSE
##################################################
# Sources
##################################################
export SOURCE_ROOT := ../../../
export SOURCES := \
top/safe_u1plus/safe_u1plus.ucf \
top/safe_u1plus/safe_u1plus.v
##################################################
# Process Properties
##################################################
export SYNTHESIZE_PROPERTIES := \
"Pack I/O Registers into IOBs" Yes \
"Optimization Effort" High \
"Optimize Instantiated Primitives" TRUE \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto
export TRANSLATE_PROPERTIES := \
"Macro Search Path" "$(shell pwd)/../../coregen/"
export MAP_PROPERTIES := \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
"Perform Timing-Driven Packing and Placement" TRUE \
"Map Effort Level" High \
"Extra Effort" Normal \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE
export PLACE_ROUTE_PROPERTIES := \
"Place & Route Effort Level (Overall)" High
export STATIC_TIMING_PROPERTIES := \
"Number of Paths in Error/Verbose Report" 10 \
"Report Type" "Error Report"
export GEN_PROG_FILE_PROPERTIES := \
"Configuration Rate" 6 \
"Create Binary Configuration File" TRUE \
"Done (Output Events)" 5 \
"Enable Bitstream Compression" TRUE \
"Enable Outputs (Output Events)" 6
export SIM_MODEL_PROPERTIES := ""
##################################################
# Make Options
##################################################
all:
@echo make proj, check, synth, bin, or clean
proj:
PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
check:
PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
synth:
PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
bin:
PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
clean:
rm -rf $(BUILD_DIR)
|
