blob: c8aff230f149b9fafd40cd6c4c0d444097502cad (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
module setting_reg
#(parameter my_addr = 0, parameter at_reset=32'd0)
(input clk, input rst, input strobe, input wire [7:0] addr,
input wire [31:0] in, output reg [31:0] out, output reg changed);
always @(posedge clk)
if(rst)
begin
out <= at_reset;
changed <= 1'b0;
end
else
if(strobe & (my_addr==addr))
begin
out <= in;
changed <= 1'b1;
end
else
changed <= 1'b0;
endmodule // setting_reg
|
