1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
// Modified from code originally by Richard Herveille, his copyright is below
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores Simple General Purpose IO core ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module nsgpio
(input clk_i, input rst_i,
input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0] dat_i,
output reg [31:0] dat_o, output reg ack_o,
input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1,
inout [31:0] gpio
);
reg [63:0] ctrl;
reg [31:0] line;
reg [31:0] lgpio; // LatchedGPIO pins
reg [31:0] ddr;
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
always @(posedge clk_i or posedge rst_i)
if (rst_i)
begin
ctrl <= 64'h0;
line <= 0;
end
else if (wb_wr)
case( adr_i[3:2] )
2'b00 :
line <= dat_i;
2'b01 :
ddr[31:0] <= dat_i;
2'b10 :
ctrl[63:32] <= dat_i;
2'b11 :
ctrl[31:0] <= dat_i;
endcase // case( adr_i[3:2] )
always @(posedge clk_i)
case (adr_i[3:2])
2'b00 :
dat_o <= lgpio;
2'b01 :
dat_o <= ddr;
2'b10 :
dat_o <= ctrl[63:32];
2'b11 :
dat_o <= ctrl[31:0];
endcase // case(adr_i[3:2])
always @(posedge clk_i or posedge rst_i)
if (rst_i)
ack_o <= 1'b0;
else
ack_o <= wb_acc & !ack_o;
// latch GPIO input pins
always @(posedge clk_i)
lgpio <= gpio;
// assign GPIO outputs
integer n;
reg [31:0] igpio; // temporary internal signal
always @(ctrl or line or debug_1 or debug_0 or atr or ddr)
for(n=0;n<32;n=n+1)
igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) :
(ctrl[2*n] ? atr[n] : line[n]) )
: 1'bz;
assign gpio = igpio;
endmodule
|
