blob: fb64cdeae114f733d9961d754b654ab8d058cc37 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
|
module ram (input clock, input write,
input [4:0] wr_addr, input [15:0] wr_data,
input [4:0] rd_addr, output reg [15:0] rd_data);
reg [15:0] ram_array [0:31];
always @(posedge clock)
rd_data <= #1 ram_array[rd_addr];
always @(posedge clock)
if(write)
ram_array[wr_addr] <= #1 wr_data;
endmodule // ram
|
