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vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/dpMem_dc.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/fifoRTL.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/RxFifoBI.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/TxFifoBI.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/RxFifo.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/TxFifo.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/initSD.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSPIWireData.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSDBlock.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sendCmd.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiCtrl.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiTxRxData.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiMaster.v
vlog +define+SIM_COMPILE +incdir+../rtl ../model/wb_master_model.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/wishBoneBI.v
vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/ctrlStsRegBI.v
vlog +define+SIM_COMPILE +incdir+../rtl ../model/sdModel.v
vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testHarness.v
vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testCase0.v
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