1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
|
//
// Copyright 2010 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
#ifndef INCLUDED_USRP2_FW_COMMON_H
#define INCLUDED_USRP2_FW_COMMON_H
/*!
* Structs and constants for usrp2 communication.
* This header is shared by the firmware and host code.
* Therefore, this header may only contain valid C code.
*/
#ifdef __cplusplus
#include <boost/cstdint.hpp>
#define _SINS_ boost:://stdint namespace when in c++
extern "C" {
#else
#include <stdint.h>
#endif
// size of the vrt header and trailer to the host
#define USRP2_HOST_RX_VRT_HEADER_WORDS32 5
#define USRP2_HOST_RX_VRT_TRAILER_WORDS32 1 //FIXME fpga sets wrong header size when no trailer present
// udp ports for the usrp2 communication
// Dynamic and/or private ports: 49152-65535
#define USRP2_UDP_CTRL_PORT 49152
#define USRP2_UDP_DATA_PORT 49153
typedef enum{
USRP2_CTRL_ID_HUH_WHAT,
//USRP2_CTRL_ID_FOR_SURE, //TODO error condition enums
//USRP2_CTRL_ID_SUX_MAN,
USRP2_CTRL_ID_GIVE_ME_YOUR_IP_ADDR_BRO,
USRP2_CTRL_ID_THIS_IS_MY_IP_ADDR_DUDE,
USRP2_CTRL_ID_HERE_IS_A_NEW_IP_ADDR_BRO,
USRP2_CTRL_ID_GIVE_ME_YOUR_MAC_ADDR_BRO,
USRP2_CTRL_ID_THIS_IS_MY_MAC_ADDR_DUDE,
USRP2_CTRL_ID_HERE_IS_A_NEW_MAC_ADDR_BRO,
USRP2_CTRL_ID_GIVE_ME_YOUR_DBOARD_IDS_BRO,
USRP2_CTRL_ID_THESE_ARE_MY_DBOARD_IDS_DUDE,
USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO,
USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE,
USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO,
USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE,
USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO,
USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE,
USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO,
USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE,
USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO,
USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE,
USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO,
USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE,
USRP2_CTRL_ID_DO_AN_I2C_READ_FOR_ME_BRO,
USRP2_CTRL_ID_HERES_THE_I2C_DATA_DUDE,
USRP2_CTRL_ID_WRITE_THESE_I2C_VALUES_BRO,
USRP2_CTRL_ID_COOL_IM_DONE_I2C_WRITE_DUDE,
USRP2_CTRL_ID_WRITE_THIS_TO_THE_AUX_DAC_BRO,
USRP2_CTRL_ID_DONE_WITH_THAT_AUX_DAC_DUDE,
USRP2_CTRL_ID_READ_FROM_THIS_AUX_ADC_BRO,
USRP2_CTRL_ID_DONE_WITH_THAT_AUX_ADC_DUDE,
USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO,
USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE,
USRP2_CTRL_ID_CONFIGURE_STREAMING_FOR_ME_BRO,
USRP2_CTRL_ID_CONFIGURED_THAT_STREAMING_DUDE,
USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO,
USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE,
USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO,
USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE,
USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO,
USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE,
USRP2_CTRL_ID_PEACE_OUT
} usrp2_ctrl_id_t;
typedef enum{
USRP2_PPS_SOURCE_SMA,
USRP2_PPS_SOURCE_MIMO
} usrp2_pps_source_t;
typedef enum{
USRP2_PPS_POLARITY_POS,
USRP2_PPS_POLARITY_NEG
} usrp2_pps_polarity_t;
typedef enum{
USRP2_REF_SOURCE_INT,
USRP2_REF_SOURCE_SMA,
USRP2_REF_SOURCE_MIMO
} usrp2_ref_source_t;
typedef enum{
USRP2_DIR_RX,
USRP2_DIR_TX
} usrp2_dir_which_t;
typedef enum{
USRP2_CLK_EDGE_RISE,
USRP2_CLK_EDGE_FALL
} usrp2_clk_edge_t;
typedef struct{
_SINS_ uint32_t id;
_SINS_ uint32_t seq;
union{
_SINS_ uint32_t ip_addr;
_SINS_ uint8_t mac_addr[6];
struct {
_SINS_ uint16_t rx_id;
_SINS_ uint16_t tx_id;
} dboard_ids;
struct {
_SINS_ uint8_t pps_source;
_SINS_ uint8_t pps_polarity;
_SINS_ uint8_t ref_source;
_SINS_ uint8_t _pad;
} clock_config;
struct {
_SINS_ uint8_t bank;
_SINS_ uint8_t _pad[3];
_SINS_ uint16_t value;
_SINS_ uint16_t mask;
} gpio_config;
struct {
_SINS_ uint8_t bank;
_SINS_ uint8_t _pad[3];
_SINS_ uint16_t tx_value;
_SINS_ uint16_t rx_value;
_SINS_ uint16_t mask;
} atr_config;
struct {
_SINS_ uint8_t dev;
_SINS_ uint8_t latch;
_SINS_ uint8_t push;
_SINS_ uint8_t readback;
_SINS_ uint8_t bytes;
_SINS_ uint8_t data[sizeof(_SINS_ uint32_t)];
} spi_args;
struct {
_SINS_ uint8_t addr;
_SINS_ uint8_t bytes;
_SINS_ uint8_t data[sizeof(_SINS_ uint32_t)];
} i2c_args;
struct {
_SINS_ uint8_t dir;
_SINS_ uint8_t which;
_SINS_ uint8_t _pad[2];
_SINS_ uint32_t value;
} aux_args;
struct {
_SINS_ uint32_t freq_word;
_SINS_ uint32_t decim;
_SINS_ uint32_t scale_iq;
} ddc_args;
struct {
_SINS_ uint8_t enabled;
_SINS_ uint8_t _pad[3];
_SINS_ uint32_t secs;
_SINS_ uint32_t ticks;
_SINS_ uint32_t samples;
} streaming;
struct {
_SINS_ uint32_t freq_word;
_SINS_ uint32_t interp;
_SINS_ uint32_t scale_iq;
} duc_args;
struct {
_SINS_ uint32_t secs;
_SINS_ uint32_t ticks;
_SINS_ uint8_t now;
} time_args;
struct {
_SINS_ uint32_t rx_mux;
_SINS_ uint32_t tx_mux;
} mux_args;
} data;
} usrp2_ctrl_data_t;
#ifdef __cplusplus
}
#endif
#endif /* INCLUDED_USRP2_FW_COMMON_H */
|
