blob: f1d65350ab7445321fa1a3dc45cb2eccf0ff4885 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
//
// Copyright 2014 Ettus Research LLC
// Copyright 2018 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: GPL-3.0-or-later
//
#include <uhd/rfnoc/constants.hpp>
#include <uhd/rfnoc/sink_block_ctrl_base.hpp>
#include <uhd/utils/log.hpp>
#include <uhdlib/rfnoc/utils.hpp>
using namespace uhd;
using namespace uhd::rfnoc;
/***********************************************************************
* Stream signatures
**********************************************************************/
stream_sig_t sink_block_ctrl_base::get_input_signature(size_t block_port) const
{
if (not _tree->exists(_root_path / "ports" / "in" / block_port)) {
throw uhd::runtime_error(str(boost::format("Invalid port number %d for block %s")
% block_port % unique_id()));
}
return _resolve_port_def(
_tree->access<blockdef::port_t>(_root_path / "ports" / "in" / block_port).get());
}
std::vector<size_t> sink_block_ctrl_base::get_input_ports() const
{
std::vector<size_t> input_ports;
input_ports.reserve(_tree->list(_root_path / "ports" / "in").size());
for (const std::string port : _tree->list(_root_path / "ports" / "in")) {
input_ports.push_back(boost::lexical_cast<size_t>(port));
}
return input_ports;
}
/***********************************************************************
* FPGA Configuration
**********************************************************************/
size_t sink_block_ctrl_base::get_fifo_size(size_t block_port) const
{
if (_tree->exists(_root_path / "input_buffer_size" / std::to_string(block_port))) {
return _tree
->access<size_t>(
_root_path / "input_buffer_size" / std::to_string(block_port))
.get();
}
return 0;
}
size_t sink_block_ctrl_base::get_mtu(size_t block_port) const
{
if (_tree->exists(_root_path / "mtu" / std::to_string(block_port))) {
return _tree->access<size_t>(_root_path / "mtu" / std::to_string(block_port))
.get();
}
return 0;
}
void sink_block_ctrl_base::configure_flow_control_in(
const size_t bytes, const size_t block_port)
{
UHD_RFNOC_BLOCK_TRACE()
<< boost::format("sink_block_ctrl_base::configure_flow_control_in(bytes=%d)")
% bytes;
uint32_t bytes_word = 0;
if (bytes) {
// Bit 32 enables flow control
bytes_word = (1 << 31) | bytes;
}
sr_write(SR_FLOW_CTRL_BYTES_PER_ACK, bytes_word, block_port);
}
void sink_block_ctrl_base::set_error_policy(const std::string& policy)
{
if (policy == "next_packet") {
sr_write(SR_ERROR_POLICY, (1 << 2) | 1);
} else if (policy == "next_burst") {
sr_write(SR_ERROR_POLICY, (1 << 3) | 1);
} else if (policy == "continue") {
sr_write(SR_ERROR_POLICY, (1 << 1) | 1);
} else if (policy == "wait") {
sr_write(SR_ERROR_POLICY, 1);
} else
throw uhd::value_error(
"Block input cannot handle requested error policy: " + policy);
}
/***********************************************************************
* Hooks
**********************************************************************/
size_t sink_block_ctrl_base::_request_input_port(
const size_t suggested_port, const uhd::device_addr_t&) const
{
const std::set<size_t> valid_input_ports =
utils::str_list_to_set<size_t>(_tree->list(_root_path / "ports" / "in"));
return utils::node_map_find_first_free(
_upstream_nodes, suggested_port, valid_input_ports);
}
// vim: sw=4 et:
|
